JPH0459944U - - Google Patents

Info

Publication number
JPH0459944U
JPH0459944U JP1990102301U JP10230190U JPH0459944U JP H0459944 U JPH0459944 U JP H0459944U JP 1990102301 U JP1990102301 U JP 1990102301U JP 10230190 U JP10230190 U JP 10230190U JP H0459944 U JPH0459944 U JP H0459944U
Authority
JP
Japan
Prior art keywords
semiconductor substrate
semiconductor device
subjected
connected via
utility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990102301U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990102301U priority Critical patent/JPH0459944U/ja
Publication of JPH0459944U publication Critical patent/JPH0459944U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第１図乃至第３図は本考案の実施例を説明する
ためのもので、第１図及び第２図は本考案のＰＮ
接合の具体的二例を示す回路模式図、第３図は本
考案のＰＮ接合を示す半導体基板の部分断面図で
ある。第４図は半導体装置の内部構造を示す正面
図、第５図は第４図の平面図である。第６図は従
来の半導体装置における半導体基板を示す部分断
面図である。 １……半導体基板、３′……電極パツド、１１
……配線パターン、１３……ＰＮ接合。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体基板の表面に形成されてワイヤボンデイ
    ングされない電極パツドと、上記半導体基板に構
    成された内部回路に延びる配線パターンとをＰＮ
    接合構造を介して接続したことを特徴とする半導
    体装置。
JP1990102301U 1990-09-29 1990-09-29 Pending JPH0459944U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990102301U JPH0459944U (ja) 1990-09-29 1990-09-29

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990102301U JPH0459944U (ja) 1990-09-29 1990-09-29

Publications (1)

Publication Number Publication Date
JPH0459944U true JPH0459944U (ja) 1992-05-22

Family

ID=31846425

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990102301U Pending JPH0459944U (ja) 1990-09-29 1990-09-29

Country Status (1)

Country Link
JP (1) JPH0459944U (ja)

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