JPH0460335B2 - - Google Patents
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- Publication number
- JPH0460335B2 JPH0460335B2 JP58072923A JP7292383A JPH0460335B2 JP H0460335 B2 JPH0460335 B2 JP H0460335B2 JP 58072923 A JP58072923 A JP 58072923A JP 7292383 A JP7292383 A JP 7292383A JP H0460335 B2 JPH0460335 B2 JP H0460335B2
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- Prior art keywords
- layer
- melting point
- point metal
- high melting
- oxide film
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
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- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、半導体装置、特に高融点金属を電極
として用いる半導体装置の製造方法に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to a method for manufacturing a semiconductor device using a high melting point metal as an electrode.
従来、半導体装置においては、電極・配線等の
材料としてはアルミニウム(以下「Al」という)
等の低融点金属、モリブデン(以下「Mo」とい
う)、タングステン(以下「W」という)等の高
融点金属、または多結晶シリコン(以下「poly
Si」という)等の半導体材料が用いられていた。
これらの材料はそれぞれ一長一短を有していた。
即ち、Alは比抵抗が約3×10-6Ω−cmと低い利
点はあるものの、その融点が660℃と低いため通
常1000℃程度の熱処理行程が必要とされる半導体
製造プロセスにAlを導入するには種々の制約が
あつた。一方poly Siは1000℃程度の熱処理にも
耐えうること及び基板として用いるシリコンとの
親和性も大きいことから半導体装置の製造プロセ
スの自由度を大きくとれるという利点をもつてい
る。更にpoly Siを酸化雰囲気で単に熱処理する
のみでpoly Si表面に絶縁性のよいシリコン酸化
膜(以下「SiO2膜」という)を簡単に形成する
ことができ、poly Si及びSiO2膜が共にH2SO4,
HOl,HNO3,H2O2等の各溶液の適当な混合液
での酸洗浄(以下単に「酸洗浄」という)に耐え
られることから素子表面の清浄化が容易に行える
ので、電極・配線等にpoly Siを用いた場合には
半導体装置の製造歩留りがよいという利点があつ
た。しかし、poly Siの比抵抗は金属に比べると
2桁ないし3桁高いので、電極・配線等にpoly
Siを用いた半導体装置では配線抵抗による伝搬遅
延を増大し、高集積化、高速化を実現することは
困難であつた。
Conventionally, aluminum (hereinafter referred to as "Al") has been used as the material for electrodes, wiring, etc. in semiconductor devices.
low melting point metals such as molybdenum (hereinafter referred to as "Mo"), high melting point metals such as tungsten (hereinafter referred to as "W"), or polycrystalline silicon (hereinafter referred to as "polysilicone").
Semiconductor materials such as "Si" were used.
Each of these materials had advantages and disadvantages.
In other words, although Al has the advantage of having a low specific resistance of approximately 3×10 -6 Ω-cm, its melting point is low at 660°C, so it is difficult to introduce Al into the semiconductor manufacturing process, which normally requires a heat treatment process of about 1000°C. There were various restrictions to do so. On the other hand, polySi has the advantage of being able to withstand heat treatment at about 1000° C. and having a high affinity with silicon used as a substrate, allowing a greater degree of freedom in the manufacturing process of semiconductor devices. Furthermore, a silicon oxide film (hereinafter referred to as "SiO 2 film") with good insulation can be easily formed on the surface of poly Si by simply heat-treating poly Si in an oxidizing atmosphere, and both poly Si and SiO 2 films are 2SO4 ,
Since it can withstand acid cleaning (hereinafter simply referred to as "acid cleaning") with an appropriate mixture of solutions such as HOl, HNO 3 , H 2 O 2 , etc., the surface of the element can be easily cleaned. When poly Si is used for semiconductor devices, etc., there is an advantage that the manufacturing yield of semiconductor devices is high. However, the resistivity of polySi is two to three orders of magnitude higher than that of metals, so polySi is used for electrodes, wiring, etc.
In semiconductor devices using Si, the propagation delay due to wiring resistance increases, making it difficult to achieve high integration and high speed.
これらに対して、高融点金属、例えばMoは融
点が約2600℃と高く、1000℃程度の熱処理に耐え
うることからMoを電極・配線等に用いると半導
体装置の製造プロセスの自由度を大きくでき、高
融点金属は比抵抗も小さいことから半導体装置の
高速化には適している。このことから高融点金属
を備えた半導体装置は脚光を浴びてきた。しか
し、poly Siに比べ高融点金属の場合には、その
表面にシリコンの熱酸化膜のように安定で良質な
絶縁層を備えた構造の半導体装置及びそれを簡単
に製造する方法が実現されていなかつたため、高
融点金属を電極・配線等に用いた半導体装置は半
導体技術の主流には今までなり得なかつた。 On the other hand, high-melting point metals such as Mo have a high melting point of about 2600℃ and can withstand heat treatment of about 1000℃, so using Mo for electrodes, wiring, etc. can increase the degree of freedom in the manufacturing process of semiconductor devices. Since high melting point metals have low specific resistance, they are suitable for increasing the speed of semiconductor devices. For this reason, semiconductor devices including high-melting point metals have been in the spotlight. However, in the case of high-melting-point metals compared to poly-Si, a semiconductor device with a structure that has a stable and high-quality insulating layer like a silicon thermal oxide film on its surface, and a method for easily manufacturing it, have not been realized. As a result, semiconductor devices using high-melting point metals for electrodes, wiring, etc. could not become mainstream in semiconductor technology until now.
本出願人は上記問題を解決する方法として、高
融点金属の表面に安定で良質な絶縁層を備えた構
造の半導体装置を製造する方法を既に出願した
(特願昭57−51383号)。すなわち、基体上に設け
られた高融点金属層上に高融点金属酸化物層、シ
リコン層及びシリコン酸化膜を順次積層し、この
基体を水素を含む雰囲気中で熱処理することで、
高融点金属層とシリコン層との間に内部シリコン
酸化膜を形成するものである。 As a method for solving the above-mentioned problem, the present applicant has already applied for a method for manufacturing a semiconductor device having a structure in which a stable and high-quality insulating layer is provided on the surface of a high-melting point metal (Japanese Patent Application No. 51383/1983). That is, by sequentially laminating a high melting point metal oxide layer, a silicon layer, and a silicon oxide film on a high melting point metal layer provided on a base body, and heat-treating this base body in an atmosphere containing hydrogen,
An internal silicon oxide film is formed between the high melting point metal layer and the silicon layer.
第1図に上記方法の行程を示す。第1−A図は
基板2上に絶縁層3が形成されてなる基体1に高
融点金属層4を形成する工程、第1−B図は高融
点金属酸化物層20の形成工程、第1−C図はシ
リコン層6の形成工程、第1−D図はシリコン酸
化膜5れい形成工程、第1−E図は水素雰囲気中
の熱処理工程で高融点金属酸化物層20が内部シ
リコン酸化膜5に変化したことを示すものであ
る。次に上述の内部シリコン酸化膜形成工程での
構造の変化を第2図に示すオージエ電子分光法の
測定結果に基づいて説明する。第2−A図は内部
シリコン酸化膜形成前、即ち第1−D図の構造に
ついて、第2−B図は水素雰囲気中の熱処理工程
後(900℃,10分)、第2−C図はさらに熱処理し
た後(900℃,30分)の構造について、表面から
基板方向への構成元素の深さ方向分布をそれぞれ
示している。poly Si層の厚さは約1100Åである。
横軸は試料をスパツタエツチングした時間で、表
面からの深さに対応している。a,b,cはそれ
ぞれ、シリコン、酸素、Moを示す曲線である。
第2−B図を第2−A図と比較してみると、熱処
理前はpoly SiとMoの界面にひとつのピークだつ
た0信号が、ふたつのピークをもつている。poly
Si側のピークが内部シリコン酸化膜に対応し、残
りのピークがMoO2層に対応している。第2−C
図ではMoO2層はなくなり、poly Si層とMoの界
面に内部シリコン酸化膜が形成される。poly Si
層の厚みに注目すると熱処理するにつれてだんだ
ん薄くなつている。即ち、水素雰囲気中で熱処理
するのに従いMoO2は徐々に還元されかつpoly
SiはMo側から徐々に酸化される。 FIG. 1 shows the steps of the above method. Fig. 1-A shows a step of forming a high melting point metal layer 4 on a substrate 1 having an insulating layer 3 formed on a substrate 2, and Fig. 1-B shows a step of forming a high melting point metal oxide layer 20. Fig. 1-C shows the process of forming the silicon layer 6, Fig. 1-D shows the process of forming the silicon oxide film 5, and Fig. 1-E shows the heat treatment process in a hydrogen atmosphere so that the high melting point metal oxide layer 20 becomes the internal silicon oxide film. This shows that the number has changed to 5. Next, changes in the structure in the above-mentioned internal silicon oxide film forming step will be explained based on the measurement results of Auger electron spectroscopy shown in FIG. Figure 2-A shows the structure before internal silicon oxide film formation, that is, the structure shown in Figure 1-D, Figure 2-B shows the structure after heat treatment in a hydrogen atmosphere (900°C, 10 minutes), and Figure 2-C shows the structure shown in Figure 1-D. The depth distribution of constituent elements from the surface toward the substrate is shown for the structure after further heat treatment (900°C, 30 minutes). The thickness of the poly Si layer is approximately 1100 Å.
The horizontal axis is the time for sputter etching the sample, which corresponds to the depth from the surface. a, b, and c are curves representing silicon, oxygen, and Mo, respectively.
Comparing Figure 2-B with Figure 2-A, the 0 signal, which had one peak at the interface between poly Si and Mo before heat treatment, now has two peaks. poly
The peak on the Si side corresponds to the internal silicon oxide film, and the remaining peaks correspond to the MoO 2 layer. 2nd-C
In the figure, the MoO2 layer is gone and an internal silicon oxide film is formed at the interface between the polySi layer and Mo. poly Si
Looking at the thickness of the layer, it becomes gradually thinner as it is heat treated. That is, as the heat treatment is carried out in a hydrogen atmosphere, MoO 2 is gradually reduced and the poly
Si is gradually oxidized starting from the Mo side.
第3図は内部酸化法の酸化特性を、バーニング
酸化法(H2:O2=1:1)及び通常の熱酸化法
(以後「ドライ酸化法」という)の酸化特性と比
較したものである。●は内部酸化法を、○はバー
ニング酸化法を、×印はドライ酸化法を示してい
る。酸化温度はすべて900℃であり、poly Si層の
膜厚は約1900Åである。内部酸化法の酸化速度は
ドライ酸化法の酸化速度より大きく、バーニング
酸化法の酸化速度はほぼ一致している。内部酸化
法において酸化速度のプロセスパラメータとして
は熱処理温度、熱処理時の水素分圧、poly Siの
膜厚等がある。poly Si層の膜厚が厚くなる程、
酸化速度は小さくなる傾向をもつが、いずれにし
ろpoly Si層の膜厚が1000−3200Åの範囲ではド
ライ酸化法よりはかなり速かつた。 Figure 3 compares the oxidation characteristics of the internal oxidation method with those of the burning oxidation method (H 2 :O 2 =1:1) and the normal thermal oxidation method (hereinafter referred to as "dry oxidation method"). . ● indicates the internal oxidation method, ○ indicates the burning oxidation method, and × indicates the dry oxidation method. The oxidation temperature was 900°C in all cases, and the thickness of the polySi layer was approximately 1900 Å. The oxidation rate of the internal oxidation method is higher than the oxidation rate of the dry oxidation method, and the oxidation rate of the burning oxidation method is almost the same. In the internal oxidation method, process parameters for oxidation rate include heat treatment temperature, hydrogen partial pressure during heat treatment, polySi film thickness, etc. The thicker the poly Si layer, the more
Although the oxidation rate tends to decrease, in any case, it was considerably faster than the dry oxidation method when the thickness of the poly Si layer was in the range of 1000-3200 Å.
B.E. Deal等のSiの酸化の理論によれば、酸化
速度を決める要因は酸化剤の酸化膜中の拡散速
度、酸化膜表面の酸化剤の濃度、酸化膜とSi界面
での反応係数等いくつかあるが、ドライ酸化法と
バーニング酸化法の酸化速度の違いは主に酸化剤
の酸化膜中の拡散速度の差による。従つて第3図
は内部酸化法における酸化剤がH2Oであること
を示しているものと思われる。つまりMoO2の還
元反応
MoO2+2H2→Mo+2H2O
で生成されたH2Oによつてpoly Siが酸化されて
いると考えることができる。ここでシリコン層の
表面に形成されたSiO2層でなるキヤツプ層(以
下「キヤツプ層」という)はシリコン層のピンホ
ールや結晶性の悪い部分を通して酸化剤である
H2Oが抜けていくのを防ぐ役目を果していると
思われる。 According to the theory of Si oxidation by BE Deal et al., there are several factors that determine the oxidation rate, such as the diffusion rate of the oxidant in the oxide film, the concentration of the oxidant on the oxide film surface, and the reaction coefficient at the interface between the oxide film and the Si. However, the difference in oxidation rate between the dry oxidation method and the burning oxidation method is mainly due to the difference in the diffusion rate of the oxidizing agent in the oxide film. Therefore, it seems that FIG. 3 shows that the oxidizing agent in the internal oxidation method is H 2 O. In other words, it can be considered that polySi is oxidized by H 2 O generated by the MoO 2 reduction reaction MoO 2 +2H 2 →Mo+2H 2 O. Here, the cap layer (hereinafter referred to as "cap layer") consisting of two SiO layers formed on the surface of the silicon layer is an oxidizing agent that passes through pinholes and areas with poor crystallinity in the silicon layer.
It seems to play a role in preventing H 2 O from escaping.
上記方法を用いると高融点金属層の表面上のみ
に通常のシリコンの熱酸化膜と同等の膜質の内部
シリコン酸化膜を選択的に簡単に形成できる。こ
れに関連して他に次のように種々の効果を得るこ
とができる。 By using the above method, it is possible to selectively and easily form an internal silicon oxide film of the same quality as a normal silicon thermal oxide film only on the surface of the high melting point metal layer. In connection with this, various other effects can be obtained as follows.
(1) 内部シリコン酸化膜は絶縁性がすぐれてお
り、高融点金属層とシリコン層との間の絶縁特
性がよい半導体装置を簡単に製造できる。(1) The internal silicon oxide film has excellent insulating properties, making it easy to manufacture semiconductor devices with good insulating properties between the high-melting point metal layer and the silicon layer.
(2) 内部シリコン酸化膜はむらなく一様に形成さ
れオーバーハング状にはならないので、短絡及
び断線の少ない半導体装置を高歩留りで製造で
きる。(2) Since the internal silicon oxide film is formed evenly and uniformly without overhanging, semiconductor devices with fewer short circuits and disconnections can be manufactured with high yield.
(3) 内部シリコン酸化膜を層間絶縁膜として利用
しシリコン層と高融点金属層を配線として利用
することにより、多層配線構造を簡単に実現で
きる。(3) A multilayer wiring structure can be easily realized by using the internal silicon oxide film as an interlayer insulating film and using the silicon layer and high melting point metal layer as wiring.
(4) 内部シリコン酸化膜は薄くても良好な絶縁特
性を有するため段差部の側面を覆う絶縁層の厚
さが少なくてすみ、半導体装置の高密度化を図
ることができる。(4) Since the internal silicon oxide film has good insulating properties even if it is thin, the thickness of the insulating layer covering the side surfaces of the step portion can be reduced, and the density of the semiconductor device can be increased.
(5) 内部シリコン酸化膜又は高融点金属酸化物層
を一旦外部にさらす工程を製造プロセスの途中
で採用する場合には、素子の酸洗浄が可能とな
り素子の清浄化が容易になり製造歩留りを向上
できると共に、製造装置の汚染軽減が図れる。(5) When adopting a process in which the internal silicon oxide film or high-melting point metal oxide layer is exposed to the outside once during the manufacturing process, the device can be cleaned with acid, making it easier to clean the device and improving the manufacturing yield. In addition, it is possible to reduce contamination of manufacturing equipment.
しかしながら、上記方法の検討を進めた結果下
記の点が明らかになつた。 However, as a result of further investigation of the above method, the following points became clear.
第1−D図の工程においてSiO2膜を形成する
方法としてシリコン層の表面を酸化する方法を用
いるとクレータ状の欠陥が発生する。その大きさ
は直径20〜数100μmであり、その密度はおよそ
70〜100個/cm2である。第4図に欠陥の光学顕微
鏡写真を示す。クレータ状の欠陥が発生するのは
シリコン膜のピンホールあるいは結晶性の悪い部
分を通して酸素が侵入しMoO3を生成し、これが
昇華したためと考えられる。 If a method of oxidizing the surface of the silicon layer is used to form the SiO 2 film in the process shown in FIG. 1-D, crater-shaped defects occur. Its size is 20 to several 100 μm in diameter, and its density is approximately
The number is 70-100 pieces/ cm2 . FIG. 4 shows an optical micrograph of the defect. It is thought that the crater-shaped defects occur because oxygen enters through pinholes or areas with poor crystallinity in the silicon film, generates MoO 3 , and sublimes it.
このようなクレータ状の欠陥が発生すると、第
1−D図の工程に続いて水素雰囲気中で熱処理を
行い内部シリコン酸化膜を形成した場合、クレー
タ状の欠陥が内部シリコン酸化膜のリークの原因
となり、半導体装置の歩留りを下げる原因となる
欠点があつた。 If such a crater-shaped defect occurs, if an internal silicon oxide film is formed by heat treatment in a hydrogen atmosphere following the process shown in Figure 1-D, the crater-shaped defect will cause leakage of the internal silicon oxide film. This resulted in a drawback that lowered the yield of semiconductor devices.
本発明は、高融点金属層の表面にだけ選択的に
シリコン酸化膜を形成する半導体装置の製造方法
において、シリコン層の表面にクレータ状の欠陥
を誘起させずに内部シリコン酸化膜を形成するこ
とを特徴とし、その目的は内部シリコン酸化膜の
膜質を向上させることにある。
The present invention provides a method for manufacturing a semiconductor device in which a silicon oxide film is selectively formed only on the surface of a high melting point metal layer, in which an internal silicon oxide film is formed without inducing crater-like defects on the surface of the silicon layer. Its purpose is to improve the quality of the internal silicon oxide film.
すなわち、本出願人は上記クレータ状の欠陥の
原因となるMoO3が生成しない条件でキヤツプ層
を形成するためには、キヤツプ層を酸素を含まな
い非金属化合物層で形成することであるとの知験
に基づき、以下に示す改善をなしたものである。
本発明に係る半導体装置の製造方法の代表的な態
様は、絶縁層を備えた基板から成る基体上に高融
点金属層を形成する工程と、前記高融点金属層の
表面に高融点金属酸化物層を形成する工程と前記
高融点金属酸化物層上にシリコン層を形成する工
程と、前記シリコン層上に酸素を含まない非金属
化合物層を形成する工程と、前記高融点金属層、
前記高融点金属酸化物層、前記シリコン層及び前
記非金属化合物層を有する基体を水素を含む雰囲
気中で熱処理し前記高融点金属層と前記シリコン
層との間に内部シリコン酸化膜を形成する工程と
を含むことを特徴とする。
In other words, the applicant believes that in order to form the cap layer under conditions in which MoO 3 , which causes the above-mentioned crater-like defects, is not generated, the cap layer must be formed of a non-metallic compound layer that does not contain oxygen. Based on our knowledge and experience, we have made the following improvements.
A typical aspect of the method for manufacturing a semiconductor device according to the present invention includes a step of forming a high-melting point metal layer on a base consisting of a substrate provided with an insulating layer, and a step of forming a high-melting point metal oxide on the surface of the high-melting point metal layer. a step of forming a silicon layer on the high melting point metal oxide layer; a step of forming an oxygen-free nonmetallic compound layer on the silicon layer; and the high melting point metal layer.
forming an internal silicon oxide film between the high melting point metal layer and the silicon layer by heat-treating the substrate having the high melting point metal oxide layer, the silicon layer, and the nonmetallic compound layer in an atmosphere containing hydrogen; It is characterized by including.
以下本発明に係る半導体装置の製造方法を実施
例に基づいて詳細に説明する。
The method for manufacturing a semiconductor device according to the present invention will be described in detail below based on examples.
第5図は本発明の一実施例である。単結晶シリ
コン基板12とこの上に絶縁層13として例えば
厚さ500Åのシリコン酸化膜を備えた構造から成
る基体11上に高融点金属層14を形成し第5−
A図の構造を得る。ここでは高融点金属層14と
して用いる材料としては、低抵抗で耐熱性が高く
その材料の酸化物が水素を含む雰囲気中で熱処理
することにより容易に還元されるものであること
が必要であり、例えばMo,W,Ta,Ti等があ
る。本実施例では以下Moを例に挙げて詳細に説
明する。第5−A図の高融点金属層14はスパツ
タ法で形成した厚さ約3000ÅのMoである。 FIG. 5 shows an embodiment of the present invention. A high melting point metal layer 14 is formed on a base body 11 having a structure including a single crystal silicon substrate 12 and a silicon oxide film having a thickness of, for example, 500 Å thereon as an insulating layer 13.
Obtain the structure shown in diagram A. Here, the material used for the high melting point metal layer 14 needs to be one that has low resistance, high heat resistance, and whose oxide is easily reduced by heat treatment in an atmosphere containing hydrogen. For example, there are Mo, W, Ta, Ti, etc. This embodiment will be described in detail below using Mo as an example. The high melting point metal layer 14 in FIG. 5-A is Mo with a thickness of about 3000 Å formed by sputtering.
次に高融点金属層14の表面を酸化して高融点
金属酸化物層21を形成し第5−B図の構造を得
る。高融点金属層14としてMoを用いた場合に
一般に安定に得られるMoの酸化物としては二酸
化モリブデン(以下「MoO2」という)と三酸化
モリブデン(以下「MoO3」という)とがある。
MoO3はMoを酸素を含む雰囲気中で低温熱処理
して容易に得られるが、このMoO3は約800℃以
上の高温になると昇華し始める。このため高融点
金属酸化物層21としてMoO3を用いた場合には
後の工程での熱処理によりMoO3の剥離等がおこ
つてしまい不都合である。従つて高融点酸化物層
21としては融点が約1900℃と高く高温で安定な
MoO2を用いる必要がある。本実施例ではMoを
備えた基体を酸素雰囲気中で390℃の温度で15分
間熱処理しMoO3をMo上に形成した後、窒素雰
囲気中で700℃の温度で30分間熱処理しMoの表
面に約700Åの厚さのMoO2を形成した。この方
法で得られたMoの酸化物がMoO2であることは
X線回折と電子回折により確認した。 Next, the surface of the high melting point metal layer 14 is oxidized to form a high melting point metal oxide layer 21 to obtain the structure shown in FIG. 5-B. Molybdenum dioxide (hereinafter referred to as "MoO 2 ") and molybdenum trioxide (hereinafter referred to as "MoO 3 ") are Mo oxides that are generally stably obtained when Mo is used as the high melting point metal layer 14.
MoO 3 can be easily obtained by heat-treating Mo at a low temperature in an oxygen-containing atmosphere, but this MoO 3 begins to sublimate at high temperatures of about 800°C or higher. For this reason, when MoO 3 is used as the high melting point metal oxide layer 21, peeling of MoO 3 may occur due to heat treatment in a later step, which is inconvenient. Therefore, the high melting point oxide layer 21 has a high melting point of about 1900°C and is stable at high temperatures.
It is necessary to use MoO2 . In this example, a substrate with Mo was heat-treated at a temperature of 390°C for 15 minutes in an oxygen atmosphere to form MoO 3 on the Mo, and then heat-treated at a temperature of 700°C for 30 minutes in a nitrogen atmosphere to form a layer on the Mo surface. A MoO 2 with a thickness of about 700 Å was formed. It was confirmed by X-ray diffraction and electron diffraction that the Mo oxide obtained by this method was MoO 2 .
次に高融点金属酸化物層の上にシリコン層16
を形成し第5−C図の構造を得る。本実施例では
電子ビーム蒸着法によりpoly Siを3200Åの厚さ
に形成した。シリコン層として用いるpoly Siの
形成には他の形成法、例えばCVD法等を用いて
もよく形成時に不純物を添加してもよい。 Next, a silicon layer 16 is placed on the high melting point metal oxide layer.
is formed to obtain the structure shown in FIG. 5-C. In this example, polySi was formed to a thickness of 3200 Å by electron beam evaporation. Other formation methods such as CVD may be used to form the polySi used as the silicon layer, and impurities may be added at the time of formation.
次にシリコン層16の上にキヤツプ層51を形
成し第5−D図の構造を得る。 Next, a cap layer 51 is formed on the silicon layer 16 to obtain the structure shown in FIG. 5-D.
次に第5−D図の構造のものを水素雰囲気また
は水素を含む不活性ガス(例えばアルゴンガス)
雰囲気中で熱処理することにより高融点酸化物層
を還元し同時にシリコン層16を内部、即ち高融
点金属層14側から酸化して高融点金属層とシリ
コン層16との間に内部シリコン酸化膜15を形
成し第5−E図の構造を得る。このとき内部シリ
コン酸化膜15は高融点金属層14の全表面に形
成される。本実施例においては、水素雰囲気中で
900℃の温度で30分間の熱処理を行いMoO2を還
元しMoとし、同時に内部シリコン酸化膜15を
形成した。上記の例では900℃・30分の熱処理を
行つているが、この熱処理条件は高融点金属酸化
物層の還元と同時にシリコン層16が内部から酸
化される条件であればよく、800℃程度の熱処理
温度であつてもかまわない。 Next, the structure shown in Figure 5-D is exposed to a hydrogen atmosphere or an inert gas containing hydrogen (for example, argon gas).
By heat treatment in an atmosphere, the high melting point oxide layer is reduced, and at the same time, the silicon layer 16 is oxidized from inside, that is, from the high melting point metal layer 14 side, to form an internal silicon oxide film 15 between the high melting point metal layer and the silicon layer 16. is formed to obtain the structure shown in FIG. 5-E. At this time, the internal silicon oxide film 15 is formed on the entire surface of the high melting point metal layer 14. In this example, in a hydrogen atmosphere
A heat treatment was performed at a temperature of 900° C. for 30 minutes to reduce MoO 2 to Mo, and at the same time, an internal silicon oxide film 15 was formed. In the above example, heat treatment is performed at 900°C for 30 minutes, but the heat treatment conditions only need to be such that the silicon layer 16 is oxidized from within at the same time as the high melting point metal oxide layer is reduced. It does not matter if it is at the heat treatment temperature.
次に本発明の具体的な実施例について説明す
る。本実施例ではキヤツプ層としてプラズマ窒化
膜を用いた。第5−C図の工程で約1000Åのpoly
Si層を形成した後、プラズマ窒化膜を基板温度:
350℃、ガス圧:1.28Torrで5%のAr希釈のSiH4
ガスを600c.c./分、アンモニアガスを50c.c./分流
した雰囲気中で約330Åの厚さに形成した。次に
密着性を向上させるためにさらにpoly Si層を約
2000Åの厚さに形成した後、水素雰囲気中で900
℃の温度で30分間熱処理した。第6図はプラズマ
窒化膜のキヤツプ層をもつ試料を水素雰囲気熱処
理した後の構造をオージエ電子分光法で測定した
ものである。poly SiとMoの界面に内部シリコン
酸化膜が形成されているのがわかる。従つてキヤ
ツプ層としてプラズマ窒化膜を用いて、試料表面
に欠陥を発生させることなく内部シリコン酸化膜
を形成できる。尚本実施例では窒化膜の形成法と
してプラズマ法を用いたが、酸素が存在しない非
金属化合物層でキヤツプ層を形成すれば良いの
で、他の方法、例えばCVD法でも直接熱窒化し
てもよいことは言うまでもない。さらに窒化膜以
外にも酸素を含まない非金属化合物膜を用いても
膜形時の温度条件を限定することなく、良質の内
部酸化膜が得られることは勿論である。なお、キ
ヤツプ層形成時の雰囲気について述べるならば、
本出願人はMoO3を形成せずMoO2だけを形成す
る条件としては酸素濃度が1%以下であれば良い
ことを既に提案している(特願昭57−40109)。こ
れより、本発明の実施例においても、略々上記し
た条件の酸素濃度の条件が必要となる。 Next, specific examples of the present invention will be described. In this example, a plasma nitride film was used as the cap layer. In the process of Figure 5-C, about 1000 Å of poly
After forming the Si layer, plasma nitride film is applied to the substrate temperature:
SiH4 diluted with 5% Ar at 350℃, gas pressure: 1.28Torr
It was formed to a thickness of about 330 Å in an atmosphere in which gas was flowed at 600 c.c./min and ammonia gas was flowed at 50 c.c./min. Next, add a further poly Si layer to improve adhesion.
After forming to a thickness of 2000 Å, 900 Å in a hydrogen atmosphere
Heat treated at a temperature of 30 minutes. FIG. 6 shows the structure of a sample having a plasma nitride cap layer subjected to heat treatment in a hydrogen atmosphere, as measured by Auger electron spectroscopy. It can be seen that an internal silicon oxide film is formed at the interface between poly Si and Mo. Therefore, by using a plasma nitride film as a cap layer, an internal silicon oxide film can be formed without generating defects on the sample surface. In this example, a plasma method was used to form the nitride film, but since it is sufficient to form the cap layer with a non-metallic compound layer in which oxygen does not exist, other methods such as CVD or direct thermal nitridation may also be used. Needless to say, it's a good thing. Furthermore, it goes without saying that a high-quality internal oxide film can be obtained by using a non-metallic compound film that does not contain oxygen in addition to the nitride film without limiting the temperature conditions during film formation. Regarding the atmosphere during the formation of the cap layer,
The present applicant has already proposed that the oxygen concentration should be 1% or less as a condition for forming only MoO 2 without forming MoO 3 (Japanese Patent Application No. 57-40109). Therefore, in the embodiments of the present invention, oxygen concentration conditions approximately equal to those described above are required.
さらにpoly Si層に発生する応力について注目
すると、表面にキヤツプ層としてpoly Siよりも
熱膨張係数の小さなもの(Si3N4等)を形成する
とpoly Si層の応力は緩和する方向になる。これ
は熱膨張係数がMo>poly Si>キヤツプ層と小さ
くなつているためである。従つて、キヤツプ層の
応力緩和の効果がpoly Si層にクラツクの発生を
防止する働きを生じさせ、その結果として酸化剤
であるH2Oが抜けて行くのを防いでいる点も欠
陥が発生しないことに寄与しているものと考えら
れる。 Furthermore, focusing on the stress generated in the poly Si layer, if a cap layer with a thermal expansion coefficient smaller than that of poly Si (such as Si 3 N 4 ) is formed on the surface, the stress in the poly Si layer tends to be relaxed. This is because the coefficient of thermal expansion decreases as Mo>polySi>cap layer. Therefore, the stress relaxation effect of the cap layer works to prevent the occurrence of cracks in the polySi layer, and as a result, the oxidizing agent H 2 O is prevented from escaping, which also causes defects. It is thought that this contributes to the fact that this is not the case.
以上説明したように、本発明を用いると高融点
金属層の表面上のみに内部シリコン酸化膜を選択
的に形成する際、キヤツプ層の形成に伴なう欠陥
の発生を解決できる。従つて次のような効果を得
ることができる。
As explained above, by using the present invention, it is possible to solve the problem of defects caused by the formation of a cap layer when an internal silicon oxide film is selectively formed only on the surface of a high melting point metal layer. Therefore, the following effects can be obtained.
(1) キヤツプ層の形成に伴なう欠陥がなくなれ
ば、内部シリコン酸化膜のリーク電流の減少、
絶縁耐圧の増大を招くので膜質を向上できる。(1) If the defects associated with the formation of the cap layer are eliminated, the leakage current of the internal silicon oxide film will decrease,
Since the dielectric strength increases, the film quality can be improved.
(2) キヤツプ層の形成に伴なう欠陥がなくなる
分、半導体装置を高歩留りで製造できる。(2) Since defects associated with the formation of the cap layer are eliminated, semiconductor devices can be manufactured at a high yield.
第1−A図〜第1−E図は本出願人が提案した
内部酸化法に係る半導体装置の製造方法の工程を
示す図、第2図は本出願人が提案した製造方法で
製造された半導体装置をオージエ電子分光測定し
求めた構成元素の深さ方向分布を示す図、第3図
は「内部酸化法」における酸化特性、第4図は本
出願人が提案した製造方法による製造方法で製造
された半導体装置の表面の光学顕微鏡写真、第5
−A図〜第5−E図は本発明に係る製造方法の各
工程を示す断面図、第6図は本発明に係る製造方
法で製造された半導体装置をオージエ電子分光測
定し求めた構成元素の深さ方向分布を示す図であ
る。
1,11……基体、2,12……基板、3,1
3……絶縁層、4,14……高融点金属層、5,
15……内部シリコン酸化膜、6,16……シリ
コン層、20,21……高融点金属酸化物層、5
0……シリコン酸化膜、51……キヤツプ層。
Figures 1-A to 1-E are diagrams showing the steps of a method for manufacturing a semiconductor device using the internal oxidation method proposed by the applicant, and Figure 2 is a diagram showing the steps of a method for manufacturing a semiconductor device using the internal oxidation method proposed by the applicant. A diagram showing the depth distribution of constituent elements determined by Auger electron spectroscopy of a semiconductor device. Figure 3 shows the oxidation characteristics in the "internal oxidation method" and Figure 4 shows the oxidation characteristics in the manufacturing method proposed by the applicant. Optical micrograph of the surface of the manufactured semiconductor device, No. 5
Figures -A to 5-E are cross-sectional views showing each step of the manufacturing method according to the present invention, and Figure 6 is the constituent elements determined by Auger electron spectroscopy of a semiconductor device manufactured by the manufacturing method according to the present invention. FIG. 3 is a diagram showing the depth distribution of 1, 11... Base, 2, 12... Substrate, 3, 1
3... Insulating layer, 4, 14... High melting point metal layer, 5,
15... Internal silicon oxide film, 6, 16... Silicon layer, 20, 21... High melting point metal oxide layer, 5
0...Silicon oxide film, 51...Cap layer.
Claims (1)
融点金属酸化物層を形成する工程と、前記高融点
金属酸化物層上にシリコン層を形成する工程と、
前記シリコン層の表面に酸素を含まない非金属化
合物層を堆積させる工程と、前記高融点金属層、
前記高融点金属酸化物層、前記シリコン層及び前
記非金属化合物層を有する基体を水素を含む雰囲
気中で熱処理し前記高融点金属層と前記シリコン
層との間に内部シリコン酸化膜を形成する工程と
を含むことを特徴とする半導体装置の製造方法。1. A step of forming a high melting point metal oxide layer on the surface of the high melting point metal layer provided on the substrate, and a step of forming a silicon layer on the high melting point metal oxide layer,
a step of depositing an oxygen-free nonmetallic compound layer on the surface of the silicon layer; and the high melting point metal layer;
forming an internal silicon oxide film between the high melting point metal layer and the silicon layer by heat-treating the substrate having the high melting point metal oxide layer, the silicon layer, and the nonmetallic compound layer in an atmosphere containing hydrogen; A method for manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58072923A JPS59200417A (en) | 1983-04-27 | 1983-04-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58072923A JPS59200417A (en) | 1983-04-27 | 1983-04-27 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59200417A JPS59200417A (en) | 1984-11-13 |
| JPH0460335B2 true JPH0460335B2 (en) | 1992-09-25 |
Family
ID=13503354
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58072923A Granted JPS59200417A (en) | 1983-04-27 | 1983-04-27 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59200417A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0752727B2 (en) * | 1986-02-06 | 1995-06-05 | 日本電信電話株式会社 | Manufacturing method of semiconductor device |
| FR2922364B1 (en) * | 2007-10-12 | 2014-08-22 | Saint Gobain | PROCESS FOR PRODUCING A MOLYBDENE OXIDE ELECTRODE |
| JP7570529B2 (en) * | 2021-02-24 | 2024-10-21 | 株式会社Screenホールディングス | How to Etch Molybdenum |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2745543B2 (en) * | 1988-07-05 | 1998-04-28 | ブラザー工業株式会社 | Image forming device |
-
1983
- 1983-04-27 JP JP58072923A patent/JPS59200417A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59200417A (en) | 1984-11-13 |
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