JPH0465432B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the simplification of a presettable counter that can be preset to any state. In general, a presettable counter is 1/N
When a preset enable signal is applied to a counter that performs a frequency division operation, each bit can be set or reset in accordance with preset data to preset to one of N states. As a specific example, FIG. 3 shows a circuit diagram in which a Johnson counter is constructed using a 4-bit delay flip-flop with set and reset functions and is presettable. In order to configure a Johnson counter with a frequency division ratio of 1/10 to 1/2 in the circuit configuration shown in the figure, it is sufficient to apply each signal to the data input terminal 1 according to Table 1. The preset operation in this circuit is performed by setting or resetting each bit according to the state of the preset data inputs 3, 4, 5, 6, and 7 for each bit when the preset enable input 2 is applied. It will be done. However, this circuit has a disadvantage in that it is not suitable for integration because it has a large number of constituent elements. The present invention simplifies the preset circuit in order to alleviate such drawbacks, and will be described in detail below with reference to the drawings. A specific example of the circuit of the present invention is shown in FIG. 1. The configuration of the counter in this figure is the same Johnson counter as in FIG. 3, and the delay flip-flop used has priority on the set function as shown in FIG. The difference is that In the circuit of FIG. 1, when the preset enable input 2 is applied, each flip-flop is reset uniformly, and at the same time, among the preset data inputs 3, 4, 5, 6, and 7, the bits to which a high level input is applied are reset. will be set. For flip-flops in which set and reset are performed at the same time, each flip-flop has set priority as shown in FIG. 2, and in FIG. Since there is an element delay of one AND gate compared to the propagation time to R, it can be set reliably.
That is, the bits whose preset data input is at a high level are set, and the bits whose preset data input is at a low level are reset. Therefore, as is clear from a comparison between FIGS. 1 and 3, the present invention allows the number of elements to be reduced while obtaining exactly the same results. On the other hand, in Figures 1 and 2, we have explained an example in which all bits are uniformly reset using the set priority function, but if the delay flip-flop in Figure 2 is changed to give reset priority, the configuration in Figure 1 can also be reset. uniformly set, preset data input and
It goes without saying that the structure of the AND gate is changed to be connected to the reset input R. In the explanation of the circuit example shown in FIG. 1 above, it was stated that since each set input S has a propagation delay of one AND gate with respect to the reset input R, it can be set reliably even if set and reset are performed at the same time. However, in order to further increase reliability, the preset enable signal is divided into one for setting and one for resetting, and the pulse width of the enable signal for set is made longer than that of the enable signal for reset, so that even after the reset signal ends, It is conceivable that the set signal remains. The present invention is applicable not only to the above-mentioned Johnson counter, but also to counters with other frequency division modes such as binary code counters, and not only delay flip-flops but also JK flip-flops, etc.
It can also be applied to circuits using other flip-flops. Note that Table 1 is a connection table when constructing a Johnson counter in FIGS. 1 and 3. 【table】

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the configuration of a presettable counter according to the present invention. FIG. 2 is a circuit diagram of a delay flip-flop that prioritizes the set function used in the present invention. FIG. 3 is a diagram showing an example of the configuration of a conventional presettable counter. 1...Data input terminal, 2...Preset enable input terminal, 3, 4, 5, 6, 7...Preset data input terminal, 8...Clock input terminal.

Claims (1)

[Scope of Claims] 1. In a presettable counter formed by cascading delay flip-flops, each delay flip-flop has a set terminal whose set operation has priority over a reset operation, and a reset terminal of each delay flip-flop. The terminals are commonly connected to a preset enable input terminal, and the set terminals of each delay flip-flop independently serve as set data input terminals, so that a predetermined input is applied to the preset enable input terminal. 1. A presettable counter which sets a bit specified by the set terminal of each delay flip-flop after uniformly resetting each of the delay flip-flops. 2. In a presettable counter formed by cascading delay flip-flops, each delay flip-flop gives priority to a reset operation over a set operation and has a reset terminal and a set terminal, and the set terminal of each delay flip-flop has a preset enable function. The reset terminals of each of the delay flip-flops are connected in common to the input terminal, and each of the reset terminals of each of the delay flip-flops independently serves as a reset data input terminal. 1. A presettable counter, which resets the bit specified by the reset terminal of each of the delay flip-flops after uniformly setting the delay flip-flop.