JPH0465543B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a pin or grid array package, and more specifically, a non-alloy composition made of copper-tungsten or copper-molybdenum is used as a semiconductor element mounting portion of a pin or grid array package. It uses [Prior art] Conventionally, ceramic packages for semiconductors have been produced by printing the necessary metal layers on green ceramic sheets using a screen printing method, laminating them, sintering them into one piece, and brazing the necessary metal members to the metal layers of the ceramic body. A ceramic frame is formed by a method of attaching the ceramic frame by a method of attaching the ceramic frame by a method of attaching the ceramic frame to a ceramic frame, or a method of attaching the ceramic frame by a press method, metallizing the frame, and bonding it to a metal member through the metallized portion by a brazing method to form a package. However, among laminated packages, in packages where the part to which the semiconductor element is bonded, the so-called semiconductor element mounting part, is composed of a metallized part on the ceramic, the sheet itself is distorted when the ceramic is sintered and integrated. Another drawback is that distortion caused by external forces during stacking may cause warping or waviness in the ceramic of the semiconductor element mounting area, and the adhesive strength of the semiconductor element may be weak, or the semiconductor element may be mounted horizontally. However, an invention proposed in Japanese Patent Application No. 56-214341 has already been made in order to manufacture a flat package for a semiconductor element mounting portion. Recently, with the development of technology, there has been a demand for packages that can mount large devices, and the packages themselves have also become larger. It has become increasingly difficult to eliminate the difference in expansion. FIG. 2 is a cross-sectional view of the main part of a package called a pin grid array, which is a package for mounting a VLSI manufactured by a conventional method. The pin grid array is a large package with an outer diameter of approximately 25 mm square or more, and the number of pins 4 that are implanted on the top surface of the ceramic 1 and are to become leads ranges from 70 or more to several hundred. The semiconductor elements sealed inside are also large. Since the conventional method shown in Fig. 2 cannot bond the oxygen-free copper plate 2 to the ceramic, a proposal was made to interpose Kovar 3 in the middle, but there were many problems due to the large difference in expansion coefficient between Kovar and oxygen-free copper. It was. Furthermore, even when oxygen-free copper and ceramic were bonded directly, cracks occurred in the ceramic and production was impossible. In addition, in the pin crid array as shown in Fig. 2, a thin plate of Kovar, molybdenum, or tungsten is also bonded to the semiconductor element bonding part 5 on the oxygen-free copper plate 2 to reduce the difference in thermal expansion between silicon and oxygen-free copper of the semiconductor element. It was necessary to take measures. On the other hand, in a semiconductor device having a structure in which a silicon element and a terminal plate mainly made of copper are connected, a device is also known in which an electrode made by dispersing tungsten or molybdenum in copper and sintering it is interposed between the two. (Refer to Japanese Unexamined Patent Publication No. 1983-62776). [Problems to be Solved by the Invention] An object of the present invention is to not only solve the above-mentioned drawbacks and problems all at once, but also to provide a pin and grid array package that can be made larger.
Regarding the material used, in the technology described in JP-A-50-62776, since a mixture of copper and tungsten or molybdenum is a sintered body, both the coefficient of thermal expansion and the thermal conductivity are W (or Mo)/Cu. The composite rule does not apply, and there are essentially pores, which poses problems in terms of properties required of the substrate, such as plating properties, airtightness, and heat conduction. The present invention also solves this problem in W (or Mo)/Cu composite materials. [Means for Solving the Problems] The present invention provides a semiconductor element mounting member/heat dissipation plate in which copper is melt-filled in the void of a tungsten or molybdenum porous core material by an infiltration method, and is 99 to 70% by weight.
is made of tungsten or molybdenum, the remainder is copper, the coefficient of thermal expansion corresponds to that of the semiconductor element and ceramic frame on which it is mounted, and the non-alloy composition has high thermal conductivity. A pre-metalized ceramic frame is directly soldered to the upper part of the semiconductor mounting member and heat sink, and
Furthermore, the pin and grid array package is characterized in that a lead-out lead pin is implanted in the upper part of the ceramic frame by brazing to form an integral structure. As described above, the non-alloy composition used in the present invention is a composite material in which a tungsten or molybdenum porous body is used as a core material and a copper material is melted and filled therein. This is a method called infiltration method,
According to this method, the porosity of the tungsten or molybdenum porous body is almost completely filled with molten copper due to capillarity, so that the density of the non-alloyed composition becomes substantially 100%. Among the properties of the materials, the coefficient of thermal expansion and thermal conductivity are shown in Table 1 for the copper-tungsten composition and in Table 2 for the copper-molybdenum composition.

【table】

[Table] As is clear from Tables 1 and 2, copper-tungsten and copper-molybdenum compositions have a thermal expansion coefficient of 50 to 75×10 ^- which has ceramic in the region where the copper content is relatively low. ⁷ , and its value almost matches the theoretical value based on the compound law of W (or Mo)/Cu, so it can be adjusted arbitrarily by changing the copper content A composite metal material having the following properties can be obtained. Therefore, it is possible to obtain a metal material whose coefficient of thermal expansion matches that of ceramics better than the currently used metals. [Example] FIG. 1 is a sectional view of the main parts of a pin and grid array manufactured according to the present invention. The ceramic frame portion 11 in Fig. 1 is made of 3 to 4 layers of ceramic sheets with the necessary metallization pattern applied using a conventional ceramic sheet lamination method (Fig. 1 shows a 3-layer ceramic sheet). Laminated and sintered to integrate. On the other hand, a composition of 15% copper and 85% tungsten prepared by the dipping method is prepared and molded into a predetermined plate shape, and 1 to 3 μm of nickel plating is applied to this. Next, the metal composition is bonded to the surface of the ceramic frame 11 to be bonded by brazing to form the semiconductor element mounting portion 12. During this brazing, the pin 13 installed above is also brazed at the same time. After that, nickel plating and gold plating were applied to complete the piece. [Effects of the Invention] As explained above, the present invention is a pin or grid array package in which a metal material is attached to a ceramic material as a semiconductor element mounting member, and the present invention is a pin/grid array package in which a metal material is attached to a ceramic material as a semiconductor element mounting member. It approximates the theoretical value of , and is also compatible with ceramics such as mullite, so this metal material can be easily replaced with ceramic parts, making it possible to create a package with a flat semiconductor mounting part without warping or distortion. Therefore, it is easy to increase the size. Furthermore, due to its high thermal conductivity, it can be used as a heat dissipation member, making it ideal for large-capacity semiconductor devices and packages that require high heat dissipation. Since semiconductor elements can be directly bonded, the number of parts in the package can be reduced and the shape can be simplified, making it essential for future pin and grid array packages.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a main part of a pin and grid array package according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a main part of a pin and grid array package according to the prior art. DESCRIPTION OF SYMBOLS 1... Ceramic, 2... Oxygen-free copper plate, 3... Kovar, 4... Pin, 5... Semiconductor element adhesion part, 11... Ceramic frame, 12... Semiconductor element mounting part, 13...
pin.

Claims (1)

[Claims] 1. The semiconductor element mounting member/heat sink is made of tungsten or molybdenum porous core material, which is melted and filled with copper by infiltration method, and has a composition in which 99 to 70% by weight is tungsten or molybdenum, and the remainder is copper. It is constructed by applying nickel plating to a non-alloy composition having a thermal expansion coefficient corresponding to that of the semiconductor element and ceramic frame to be mounted, and having high thermal conductivity, and which also serves as a semiconductor mounting member and heat dissipation member. A pin characterized in that a pre-metallized ceramic frame is directly brazed to the top of the plate, and a lead-out lead pin is implanted in the top of the ceramic frame by brazing to form an integral structure. Grid array packaging.