JPH0467635A - Formation of wiring - Google Patents

Formation of wiring

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Publication number
JPH0467635A
JPH0467635A JP17961890A JP17961890A JPH0467635A JP H0467635 A JPH0467635 A JP H0467635A JP 17961890 A JP17961890 A JP 17961890A JP 17961890 A JP17961890 A JP 17961890A JP H0467635 A JPH0467635 A JP H0467635A
Authority
JP
Japan
Prior art keywords
crystal grains
wiring
forming
film
alloy film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17961890A
Other languages
Japanese (ja)
Inventor
Hitoshi Ito
仁 伊藤
Haruo Okano
晴雄 岡野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP17961890A priority Critical patent/JPH0467635A/en
Publication of JPH0467635A publication Critical patent/JPH0467635A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To lengthen the wiring life by a method wherein a conductive thin film containing crystal grains mainly comprising Al is formed on a substrate and then a layer comprising crystal grains of different kind of conductive element is formed on the parts whereon a part of the crystal grains is selectively removed. CONSTITUTION:A thermal oxide film 2 is deposited on a p type single crystal Si substrate 1 and after depositing an AlSi alloy film 3 by ordinary high speed sputtering process, a part of the Al alloy film 3 is selectively removed from the grain boundary by processing in ammonia fluoride solution. Next, Cu films 4 are formed and after the heat treatment in nitrogen atmosphere, the Cu films 4 are polished until the surface of the Al alloy film 3 is exposed by coating with resist and using Ar sputtering process. The crystal grains comprising this conductive element restrain the movement of the component atoms in the crystal grains mainly comprising Al due to the electrical stress so that the electromigration may hardly occur. Accordingly, the wiring having high electromigration resistance can be formed.

Description

【発明の詳細な説明】 [発明の目的コ (産業上の利用分野) この発明は半導体装置の製造方法に関わり、特に、配線
の形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Industrial Application Field) The present invention relates to a method of manufacturing a semiconductor device, and particularly relates to a method of forming wiring.

(従来の技術) 半導体装置の高集積化は、構成素子の微細化によっても
たらされている。例えば、IMDRAM、256KSR
AMなどの超LSIは1.0〜1.2μmの設計基準で
作られており、更に高集積化を目的としてサブミクロン
の設計基準の超LSIが作られようとしている。半導体
装置の微細化により配線の幅はますます小さくなり、高
集・積比により配線長は著しく増大するため、配線の信
頼性を維持することが特に重要になっている。
(Prior Art) High integration of semiconductor devices is brought about by miniaturization of constituent elements. For example, IMDRAM, 256KSR
Very large scale integrated circuits such as AM are manufactured with a design standard of 1.0 to 1.2 μm, and very large scale integrated circuits with a submicron design standard are being created for the purpose of higher integration. With the miniaturization of semiconductor devices, the width of interconnects is becoming smaller and smaller, and the length of interconnects is significantly increasing due to higher integration and integration ratios, making it particularly important to maintain the reliability of interconnects.

超LSIの配線には、通常アルミニウム(All )を
主成分とした合金膜が用いられる。先に述べたように配
線形状は細くなるが印加電圧は直流5Vと変わらないた
め、Al1合金配線の単位断面積にかかる電流ストレス
は相対的に増大する。大きな電流ストレスを印加したA
g合金配線では、従来生じなかった種々の現象が顕著に
なってくる。例えば、電子の流れのためにAj7原子が
電子の流れ方向に輸送され、Ag合金配線が部分的に細
り、しまいには断線する現象(エレクトロ・マイグレー
ション)やAg合金配線上に形成した絶縁膜のストレス
のために、放置しておくだけでAg合金配線が断線して
しまう現象(ストレスマイグレーション)等である。こ
れらの現象が生じるとA1合金膜が断線してしまうため
、配線の信頼性が著しく低下する。
An alloy film containing aluminum (All) as a main component is usually used for wiring in VLSIs. As mentioned above, although the wiring shape becomes thinner, the applied voltage remains the same as 5 V DC, so the current stress applied to the unit cross-sectional area of the Al1 alloy wiring increases relatively. A with large current stress applied
With g-alloy wiring, various phenomena that have not occurred in the past become noticeable. For example, due to the flow of electrons, Aj7 atoms are transported in the direction of the electron flow, causing the Ag alloy wiring to become partially thin and eventually break (electromigration), and the phenomenon of the insulating film formed on the Ag alloy wiring. This is a phenomenon (stress migration) in which Ag alloy wiring breaks due to stress if left unattended. When these phenomena occur, the A1 alloy film is disconnected, and the reliability of the wiring is significantly reduced.

これらの断線は、おもにAj7合金膜の粒界で生じてお
り、Ag合金膜を用いる場合は、その粒界を強化する必
要があった。
These disconnections mainly occur at the grain boundaries of the Aj7 alloy film, and when an Ag alloy film is used, it is necessary to strengthen the grain boundaries.

(発明が解決しようとする課題) 以上のように、超LSI用の配線は通電したときに断線
しやすいという問題があった。本発明は上記実情に鑑み
てなされたものであり、エレクトロ・マイグレーション
等耐性の大きい配線を形成する配線の形成方法を提供す
ることを目的とする。
(Problems to be Solved by the Invention) As described above, there is a problem in that the wiring for VLSI is easily disconnected when energized. The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a method for forming a wire that is highly resistant to electromigration and the like.

[発明の構成] (課題を解決するための手段) 前述した問題を解決するため、本発明は、基体上にアル
ミニウムを主成分とする結晶粒を含む導電性薄膜を形成
する工程と、前記導電性薄膜の結晶粒の一部を選択的に
除去する工程と、前記除去した部分に前記導電性薄膜と
は異種の導電性元素の結晶粒からなる層を形成する工程
とを含むことを特徴とする配線の形成方法を提供する。
[Structure of the Invention] (Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a process of forming a conductive thin film containing crystal grains mainly composed of aluminum on a substrate, and the method comprises the steps of: selectively removing a part of the crystal grains of the conductive thin film; and forming a layer consisting of crystal grains of a conductive element different from the conductive thin film in the removed portion. A method for forming wiring is provided.

(作  用) 本発明による配線の形成方法であれば、アルミニウムを
主成分とする結晶粒の粒界にこの結晶粒とは異種の導電
性元素からなる結晶粒が形成される。
(Function) According to the wiring forming method according to the present invention, crystal grains made of a conductive element different from the crystal grains are formed at the grain boundaries of crystal grains whose main component is aluminum.

この導電性元素からなる結晶粒は、電気的ストレスによ
り生じる前記アルミニウムを主成分とする結晶粒内の構
成原子の移動を抑制するので、エレクトロ・マイグレー
ションは起こりにくい。従ってエレクトロφマイグレー
ション耐性の大きい配線を形成することができる。
The crystal grains made of the conductive element suppress the movement of constituent atoms within the crystal grains mainly composed of aluminum caused by electrical stress, so that electromigration is less likely to occur. Therefore, it is possible to form a wiring having high electro-φ migration resistance.

(実施例) 以下、本発明の詳細を実施例を用いて詳細に説明する。(Example) Hereinafter, the details of the present invention will be explained in detail using examples.

第1の実施例 第1図は本発明による配線の形成方法の一実施例を説明
するための工程断面図である。
First Embodiment FIG. 1 is a process sectional view for explaining an embodiment of the method for forming wiring according to the present invention.

p形単結晶St基板1に熱酸化膜2を0.2μm堆積し
、さらに通常の高速スパッタリング法でAr1・1%S
i合金膜3を0.8μm堆積した(第1図(a))。し
かる後にフッ化アンモニア溶液で処理して、粒界部から
選択的にAfi合金膜のグレインの一部を除去した(第
1図(b))。さらに、フッ化アンモニア溶液の濃度と
処理時間を適当に選ぶことにより、A1合金膜3の形状
を第1図(C)に示すように所望の形状に制御する。次
に、Cu膜4を0.2μm形成し、この積層薄膜を45
0℃窒素雰囲気で30分熱処理した(第1図(d))。
A thermal oxide film 2 with a thickness of 0.2 μm is deposited on a p-type single crystal St substrate 1, and an Ar1.1% S film is further deposited using a normal high-speed sputtering method.
An i-alloy film 3 was deposited to a thickness of 0.8 μm (FIG. 1(a)). Thereafter, it was treated with an ammonia fluoride solution to selectively remove some of the grains of the Afi alloy film from the grain boundaries (FIG. 1(b)). Furthermore, by appropriately selecting the concentration of the ammonium fluoride solution and the treatment time, the shape of the A1 alloy film 3 is controlled to a desired shape as shown in FIG. 1(C). Next, a Cu film 4 with a thickness of 0.2 μm was formed, and this laminated thin film was
Heat treatment was performed in a nitrogen atmosphere at 0° C. for 30 minutes (FIG. 1(d)).

しかる後に、レジストを塗布してArスパッタリングで
表面からAl1合金膜3の表面がでるまで削った(第1
図(e))。この試料表面を上面から走査型電子顕微鏡
(SEM)で観察すると、第2図の上面図に示すように
結晶粒を単位として光りかたが異なり、Ag合金からな
る結晶粒6とCuからなる結晶粒5がそれぞれ形成され
ていることがわかった。確認のため、この薄膜の表面を
マイクロAES (電子プローブの照射面積が約1μm
であるので、結晶粒単位の表面分析ができる。)で分析
すると、電子プローブを走査するに従ってAD SS 
iが主に検出される結晶粒とCuが主に検出される結晶
粒とが存在した。このことから、結晶粒を単位としてA
g合金からなる結晶粒6とCuからなる結晶粒5がそれ
ぞれ熱酸化膜2上に形成されていることが確認された。
After that, a resist was applied and the surface was scraped by Ar sputtering until the surface of the Al1 alloy film 3 was exposed (first
Figure (e)). When the surface of this sample is observed from above using a scanning electron microscope (SEM), as shown in the top view of Figure 2, the way each crystal grain shines differs as a unit, with crystal grains 6 made of Ag alloy and crystals made of Cu. It was found that grains 5 were formed respectively. For confirmation, the surface of this thin film was subjected to micro-AES (electronic probe irradiation area is approximately 1 μm).
Therefore, surface analysis can be performed on a grain-by-crystal grain basis. ), AD SS according to the scanning electron probe
There were crystal grains in which i was mainly detected and crystal grains in which Cu was mainly detected. From this, it can be seen that A
It was confirmed that crystal grains 6 made of g alloy and crystal grains 5 made of Cu were formed on thermal oxide film 2, respectively.

さらに、熱処理によって、Ag合金膜とCu各々の結晶
粒が接触している粒界では、それぞれAr1.Si、C
uが相互拡散していることが確認された。
Furthermore, due to the heat treatment, Ar1. Si,C
It was confirmed that u were interdiffused.

この合金膜をバターニングして、通電試験をした。比較
のため、通常のAg−8i合金膜の通電試験もした。配
線幅0,5〜2.0μm、スペース1μm1配線長12
關のIc)配線を形成し、電流ストレス1.0X10 
 A/Cl11  、温度150℃で加速試験をした。
This alloy film was buttered and subjected to a current conduction test. For comparison, a current test was also conducted on a normal Ag-8i alloy film. Wiring width 0.5 to 2.0 μm, space 1 μm 1 wire length 12
Ic) Form wiring and apply current stress 1.0X10
An accelerated test was conducted at A/Cl11 and a temperature of 150°C.

Cu結晶粒を混在させたA47合金膜の寿命は、通常の
A1合金膜よりも約20〜30倍長かった。また、Cu
をドーピング又はスパッタ堆積した後、シンターして形
成したA11St−Cu合金膜と比べても約3〜10倍
長かった。
The life of the A47 alloy film mixed with Cu crystal grains was about 20 to 30 times longer than that of the normal A1 alloy film. Also, Cu
The length was about 3 to 10 times longer than that of an A11St-Cu alloy film formed by doping or sputter deposition and then sintering.

第2の実施例 第1の実施例では、Afi合金膜の部分を選択的にエツ
チングした後、Cu膜を堆積して熱処理した後に上層の
Cu膜を下層のAg合金膜の表面が露出するまでエツチ
ングした。第2の実施例では、このCu膜も残しておき
配線に利用した。次に図面を用いて詳細に説明する。第
3図は本発明による配線の形成方法の他の実施例を説明
するための工程断面図である。p形単結晶Si基板7に
熱酸化膜8を0.2μm堆積し、さらに通常の高速スパ
ッタリング法で1 ・1%Si合金膜9を0.8μm堆
積した(第3図(a))。しかる後にフッ化アンモニア
溶液で処理して、粒界部から選択的にAj)合金膜のグ
レインの一部を除去した(第3図(b))。フッ化アン
モニア溶液の濃度と処理時間を適当に選ぶことによりA
I合金M9の形状は所望の形状に制御できることは第1
の実施例で示した通りである。次に、Cu膜10を0.
15μm形成し、この積層薄膜を450℃窒素雰囲気で
30分熱処理をした(第2図(C))。
Second Embodiment In the first embodiment, after selectively etching a portion of the AFi alloy film, a Cu film is deposited and heat treated, and the upper Cu film is removed until the surface of the lower Ag alloy film is exposed. Etched. In the second example, this Cu film was also left and used for wiring. Next, a detailed explanation will be given using the drawings. FIG. 3 is a process sectional view for explaining another embodiment of the wiring forming method according to the present invention. A thermal oxide film 8 was deposited to a thickness of 0.2 μm on a p-type single crystal Si substrate 7, and a 1.1% Si alloy film 9 was further deposited to a thickness of 0.8 μm using a conventional high-speed sputtering method (FIG. 3(a)). Thereafter, it was treated with an ammonia fluoride solution to selectively remove part of the grains of the Aj) alloy film from the grain boundaries (FIG. 3(b)). A by appropriately selecting the concentration of ammonium fluoride solution and treatment time.
The first thing is that the shape of I alloy M9 can be controlled to a desired shape.
This is as shown in the example. Next, the Cu film 10 was
A thickness of 15 μm was formed, and the laminated thin film was heat-treated at 450° C. in a nitrogen atmosphere for 30 minutes (FIG. 2(C)).

しかる後に、レジストを塗布して通常の光露光法でバタ
ーニングし、塩素系のエツチングガスを用いて反応性イ
オンエツチング(RI E)でCu膜10およびA11
合金膜9をエツチングし、所望の配線パターンを形成し
た。この時、Cuのエツチングは加工精度は一般によく
ないが、前記0.15μm程度の膜厚であれば十分に加
工できた。
After that, a resist is applied and patterned using a normal light exposure method, and the Cu films 10 and A11 are etched by reactive ion etching (RIE) using a chlorine-based etching gas.
The alloy film 9 was etched to form a desired wiring pattern. At this time, the processing accuracy of Cu etching is generally not good, but the film thickness of about 0.15 μm could be processed satisfactorily.

この試料については、特に分析を試みなかったが、第1
の実施例からの類推で、島状のAN合金の結晶粒の上に
Cuの結晶粒か積層しており、さらにCuの結晶粒の上
層は互いの粒界が接触していると考えられる。また、A
i1合金膜とCu各々の結晶粒が接触している粒界では
、それぞれAg、Si、Cuが相互拡散していると考え
られる。
No particular analysis was attempted for this sample, but the first
By analogy with the example described above, it is considered that Cu crystal grains are stacked on top of the island-shaped AN alloy crystal grains, and that the grain boundaries of the upper layer of the Cu crystal grains are in contact with each other. Also, A
It is considered that Ag, Si, and Cu are interdiffused at the grain boundaries where the i1 alloy film and the Cu crystal grains are in contact with each other.

この合金膜をバターニングして、通電試験をした。比較
のため、通常のA11−Si合金膜の通電試験もした。
This alloy film was buttered and subjected to a current conduction test. For comparison, a normal A11-Si alloy film was also subjected to an electrical conduction test.

配線幅0.5〜2.0μm1スペ一ス1μm、配線長1
2鶴のAl配線を形成し、電流ストレス1.0xlOA
/csn  、温度150℃で加速試験をした。Cu結
晶粒とA1合金の結晶粒を混在させ更に上層はCu膜で
つながっているこの試料での寿命は、通常の1合金膜よ
りも50倍以上長かった。またCuをドーピング又はス
パッタ堆積した後、シンターして形成したAl−5i−
Cu合金膜と比べても約5〜20倍以上は長かった。
Wiring width 0.5-2.0μm 1 space 1μm, wire length 1
Two cranes of Al wiring are formed and the current stress is 1.0xlOA.
/csn, and an accelerated test was conducted at a temperature of 150°C. The life of this sample, in which Cu crystal grains and A1 alloy crystal grains were mixed and connected by a Cu film in the upper layer, was more than 50 times longer than that of a normal single alloy film. Also, after doping or sputter depositing Cu, Al-5i-
It was about 5 to 20 times longer than the Cu alloy film.

尚、これまでの実施例では、第二の導電性元素の例とし
てCuの場合を示したが、タングステン。
Incidentally, in the examples so far, the case of Cu was shown as an example of the second conductive element, but tungsten.

チタン、タンタル、マグネシウムでも試したところ配線
層のシート抵抗の変化は用いる第二の導電性元素によっ
て変動するものの、配線パターンを形成して、電気寿命
を測定するといずれの場合も八Ω・Si合金の場合より
も一桁以上改善された。
When we tested titanium, tantalum, and magnesium, the change in sheet resistance of the wiring layer varied depending on the second conductive element used, but when we formed a wiring pattern and measured the electrical life, in all cases it was found that 8Ω/Si alloy This is an order of magnitude improvement over the previous case.

また、前記実施例では、Aj7のグレインの一部の選択
的除去を、フッ化アンモニア溶液で行ったが、塩素系ガ
スを用いたケミカルドライエツチングなどで行ってもよ
い。
Further, in the above embodiment, selective removal of a portion of the grains of Aj7 was performed using an ammonia fluoride solution, but it may also be performed using chemical dry etching using a chlorine gas.

また、用いるSi基板の種類や、酸化膜の種類等、本発
明の主旨から逸脱しない範囲で、適宜実施できることは
いうまでもない。
Furthermore, it goes without saying that the type of Si substrate used, the type of oxide film, etc. can be modified as appropriate without departing from the gist of the present invention.

[発明の効果コ 本発明による配線の形成方法によれば、電気的ストレス
により生じるアルミニウムを主成分とする結晶粒内の構
成原子の移動を抑制する配線を形成することができる。
[Effects of the Invention] According to the method for forming a wiring according to the present invention, it is possible to form a wiring that suppresses movement of constituent atoms within crystal grains mainly composed of aluminum caused by electrical stress.

従って、配線寿命は従来よりも長くなり、電気的信頼性
の高い配線が形成できる。
Therefore, the life of the wiring is longer than that of the conventional wiring, and wiring with high electrical reliability can be formed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第3図は本発明の詳細な説明するための工程
断面図である。 1・・・Si基板、2・・・熱酸化膜、3・・・Al1
・1%Si合金膜、4・・・Cu膜、5・・・Cuから
なる結晶粒、6・・・AfI合金からなる結晶粒、7・
・・Si基板、8・・・熱酸化膜、9・・・All ・
1%Si合金膜、10・・・Cu膜。
1 to 3 are process sectional views for explaining the present invention in detail. 1...Si substrate, 2...thermal oxide film, 3...Al1
・1% Si alloy film, 4... Cu film, 5... Crystal grains made of Cu, 6... Crystal grains made of AfI alloy, 7.
...Si substrate, 8...thermal oxide film, 9...All ・
1% Si alloy film, 10...Cu film.

Claims (4)

【特許請求の範囲】[Claims] (1)基体上にアルミニウムを主成分とする結晶粒を含
む導電性薄膜を形成する工程と、前記導電性薄膜の結晶
粒の一部を選択的に除去する工程と、前記除去した部分
に前記導電性薄膜とは異種の導電性元素の結晶粒からな
る層を形成する工程とを含むことを特徴とする配線の形
成方法。
(1) A step of forming a conductive thin film containing crystal grains mainly composed of aluminum on a substrate, a step of selectively removing a part of the crystal grains of the conductive thin film, and a step of forming a 1. A method for forming wiring, comprising the step of forming a layer made of crystal grains of a different type of conductive element than the conductive thin film.
(2)前記アルミニウムを主成分とする結晶粒はシリコ
ンを含むことを特徴とする請求項(1)記載の配線の形
成方法。
(2) The method for forming a wiring according to claim 1, wherein the crystal grains containing aluminum as a main component contain silicon.
(3)前記除去した部分に前記導電性薄膜とは異種の導
電性元素の結晶粒からなる層を形成する工程の後に、熱
処理を行ない、粒界の部分を合金化することを特徴とす
る請求項(1)記載の配線の形成方法。
(3) A claim characterized in that, after the step of forming a layer made of crystal grains of a conductive element different from the conductive thin film in the removed portion, heat treatment is performed to alloy the grain boundary portion. The method for forming the wiring according to item (1).
(4)前記異種の導電性元素は、銅、タングステン、チ
タン、タンタル、マグネシウムのうち少なくとも一つ以
上を含む物質であることを特徴とする請求項(1)記載
の配線の形成方法。
(4) The method for forming a wiring according to claim (1), wherein the different type of conductive element is a substance containing at least one of copper, tungsten, titanium, tantalum, and magnesium.
JP17961890A 1990-07-09 1990-07-09 Formation of wiring Pending JPH0467635A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17961890A JPH0467635A (en) 1990-07-09 1990-07-09 Formation of wiring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17961890A JPH0467635A (en) 1990-07-09 1990-07-09 Formation of wiring

Publications (1)

Publication Number Publication Date
JPH0467635A true JPH0467635A (en) 1992-03-03

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP17961890A Pending JPH0467635A (en) 1990-07-09 1990-07-09 Formation of wiring

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JP (1) JPH0467635A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5470788A (en) * 1994-02-28 1995-11-28 International Business Machines Corporation Method of making self-aligned, lateral diffusion barrier in metal lines to eliminate electromigration
US6597067B1 (en) 1994-02-28 2003-07-22 International Business Machines Corporation Self-aligned, lateral diffusion barrier in metal lines to eliminate electromigration

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5470788A (en) * 1994-02-28 1995-11-28 International Business Machines Corporation Method of making self-aligned, lateral diffusion barrier in metal lines to eliminate electromigration
US6597067B1 (en) 1994-02-28 2003-07-22 International Business Machines Corporation Self-aligned, lateral diffusion barrier in metal lines to eliminate electromigration

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