JPH0472736A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0472736A
JPH0472736A JP18619790A JP18619790A JPH0472736A JP H0472736 A JPH0472736 A JP H0472736A JP 18619790 A JP18619790 A JP 18619790A JP 18619790 A JP18619790 A JP 18619790A JP H0472736 A JPH0472736 A JP H0472736A
Authority
JP
Japan
Prior art keywords
semiconductor device
vacuum
inert gas
irradiated
electron beam
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18619790A
Other languages
Japanese (ja)
Inventor
Hajime Akiyama
肇 秋山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP18619790A priority Critical patent/JPH0472736A/en
Publication of JPH0472736A publication Critical patent/JPH0472736A/en
Pending legal-status Critical Current

Links

Landscapes

  • Thyristors (AREA)

Abstract

PURPOSE:To enhance the controllability of life time and the reliability by a method wherein a semiconductor device is arranged in vacuum or inert gas atmosphere to be irradiated with a high energy electron beam or gamma rays. CONSTITUTION:A semiconductor device 10 having multiple main electrodes and at least one control electrode is arranged in vacuum or inert gas atmosphere to be irradiated with a high energy electron beam or gamma rays 50 in the atmosphere. Through these procedures, the chemically active species produced in open air can be prevented from entering the vacuum region 41 due to the irradiation with the electron beams 50 so that the surface of the semiconductor device 10 need not be oxidized and the new level need not be deeply led inside.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は電力用半導体のライフタイム制御にoff 
Thyristor ) 、 SI Th (5Lat
istia IaduationThyristor 
) 、 IGBT (In5ulat@d Gate 
BipolatTransiaLor )等各種の動作
原理に基づいた素子が開発されている。これらはいずn
も少数キャリアを導入するためスイッチング速度を向上
させる為にはライフタイム制御を行なう必要がある。ラ
イフタ、イムを制御する為には、金、白金等の重金属を
素子内に拡散させる方法、電子線、rdAs中性子線等
の透過力の大きい放熱線を照射する方法、プロトン・ヘ
リウム等、のイオンを照射する方法が知られている。こ
nらのうち、再現性、均一性に優れ、製造が比較的簡便
なことから電子線、γ線を照射することによるライフタ
・イム制御が多く行なわれている。
[Detailed Description of the Invention] [Field of Industrial Application] This invention is applicable to lifetime control of power semiconductors.
Thyristor), SI Th (5Lat
istia Iduration Thyristor
), IGBT (In5ulat@d Gate
Elements based on various operating principles, such as BipolatTransiaLor), have been developed. These are Izun
Since minority carriers are also introduced, lifetime control is required to improve switching speed. In order to control the life stage and im, there are methods of diffusing heavy metals such as gold and platinum into the element, methods of irradiating heat radiation with high penetrating power such as electron beams and rdAs neutron beams, and methods of irradiating ions such as protons and helium. A method of irradiating is known. Among these, life time control by irradiation with electron beams or gamma rays is often performed because it has excellent reproducibility and uniformity and is relatively simple to manufacture.

第4図に従来の電子線照射によるIGBTのライフタイ
ム制御を行う場合の断面模式図を示す。このものは、P
“コレクタ層(1)の−主面にはN−エピタキシャル層
(匂が形成さnている。N−エピタキシャル層(2)の
表面の一部領域にはP形不純物を選択的に拡散すること
によりN+エミフタ領域(4)が形成さnている。N−
エピタキシャル層(2)の表面とN+エミフタ領域(4
)の表面とで挾tnたPウェル領域(3)の表面上には
ゲート絶縁膜(5)が形成さnlこのゲート絶縁膜(6
)は隣接するIGBTセル間で一体となるようにN−エ
ピタキシャル層(2)の表面上にも形成さnている。ゲ
ート絶縁膜(5)上には、例えばポリシリコンから成る
ゲート電極(6)が形成され、また、Pウェル領域(3
)及びN工くツタ領域(4)の両方に(気的に接続する
ように、例えばアルミニウムなどの金属のエミッタ重重
(7)が形成さnている。なお、ゲート重重(6)及び
エミッタt J! (7)は絶縁膜(的を介した多層構
造とすることにより全IGBTセルに対してそnぞれ共
通に電気的につながった構造となっている。Pコレクタ
層(1)の他主面には金属のコレクタ電If (1)が
全fGBTセルに対し一体となるよう形成さnている。
FIG. 4 shows a schematic cross-sectional view when lifetime control of an IGBT is performed using conventional electron beam irradiation. This one is P
“An N-epitaxial layer is formed on the main surface of the collector layer (1).P-type impurities are selectively diffused into a part of the surface of the N-epitaxial layer (2). An N+ emifter region (4) is formed by N-.
The surface of the epitaxial layer (2) and the N+ emifter region (4)
A gate insulating film (5) is formed on the surface of the P well region (3) sandwiched between the surface of the gate insulating film (6) and the surface of the P well region (3).
) are also formed on the surface of the N-epitaxial layer (2) so as to be integrated between adjacent IGBT cells. A gate electrode (6) made of polysilicon, for example, is formed on the gate insulating film (5), and a P well region (3) is formed on the gate insulating film (5).
) and the N-shaped ivy region (4) (for example, an emitter layer (7) made of metal such as aluminum is formed so as to be electrically connected to the gate layer (6) and the emitter layer (7). J! (7) is an insulating film (by having a multilayer structure with a target in between, it has a structure in which it is electrically connected in common to all IGBT cells. In addition to the P collector layer (1) A metal collector electrode If (1) is formed on the main surface so as to be integral with all fGBT cells.

次に動作について説明する。N−エピタキシャル層(2
)とN工ζツタ領域(4)とで挾tf′したPウェル領
域(3)の表面近傍は、nチャンネルのMO5構造にな
っており、ゲート端子Gを通じてゲート電極(6)に正
電圧を印加することによりゲート電[(6)の直下のP
ウェル領域(3)の表面近傍に形成さしたチャネルを通
じて、電子がN+エミッタ領域(4)よりN−エピタキ
シャル層(2)へと流れる。図中、■。はこのようにし
て流れる電子電流を示す。一方、P コレクタ層ωから
は少数キャリアである正孔がN″″″エピタキシヤル層
)に注入さnlその一部は上記電子と再結合して消滅し
、残りは図中の正孔電流1h  としてPウェル領域(
3)を流nる。このようにIGBTは基本的にバイポー
ラ動作をし、Nエピタキシャル層(2)では電導度変調
の効果から移導度が増大することにより、従来のパワー
MO5に比べて、低いオン電圧、大きい電流容量を実現
できる利点がある。しかし反面、ターンオフ時には正孔
電流Ihの減少がg□5FIT等に比べて時間的にゆっ
くりしているため動作周波数を上げられない嫌いがある
Next, the operation will be explained. N-epitaxial layer (2
) and the N-type vine region (4), the vicinity of the surface of the P-well region (3) has an n-channel MO5 structure, and a positive voltage is applied to the gate electrode (6) through the gate terminal G. By applying the gate voltage [P directly below (6)
Electrons flow from the N+ emitter region (4) to the N- epitaxial layer (2) through a channel formed near the surface of the well region (3). In the figure, ■. represents the electron current flowing in this way. On the other hand, holes, which are minority carriers, are injected from the P collector layer ω into the N″″″ epitaxial layer), a part of which recombines with the electrons and disappears, and the rest is the hole current 1 h in the figure. as the P-well region (
3). In this way, the IGBT basically operates in a bipolar manner, and the N epitaxial layer (2) has a lower on-voltage and larger current capacity than the conventional power MO5 because the conductivity increases due to the effect of conductivity modulation. It has the advantage of being able to achieve However, on the other hand, during turn-off, the decrease in hole current Ih is slower than in g□5FIT, so the operating frequency cannot be increased.

こnは内蔵PNP )ランジスタがオン状態のとき、そ
のベース領域となるN−エピタキシャル層(2)内には
電子と正孔とが充満しており、MOS)ランジスタをオ
フさせて、N″″″エピタキシヤル層)への電子の注入
を遮断しても、正孔はその移動度かつ小さいため、急に
は減少しないことに起因している。
When the built-in PNP transistor is in the on state, the N- epitaxial layer (2) serving as its base region is filled with electrons and holes, which turns off the MOS) transistor and turns the N'''' This is because even if injection of electrons into the epitaxial layer is blocked, holes do not suddenly decrease because of their small mobility.

このターンオフ時間を短縮させるためにはライムタイム
制御を行なうのが有効であることが知られている。その
方法として、いくつか提案さnているが、多く用いらn
ているのは電子線を照射することによるものである。こ
こで、電子MA鱒は加速エネルギーINhV又はそn以
上である。この電子線類はN−エピタキシャル層(2)
内に格子欠陥を発生させるが、こnは深いトラップ準位
としてキャリアに対する再結合中心となるため、ターン
オフ時にはキャリアを短時間内に消滅させることができ
る。高エネルギー電子縁は透過力が大きいため、外気−
が全くの大気であっても、被照射サンプル全体へ均一照
射を行なう上での支障は無く、更にサンプルの設置、回
収が簡便に行なえるという利点がある。
It is known that performing time-time control is effective in shortening this turn-off time. Several methods have been proposed, but they are not widely used.
This is done by irradiating it with an electron beam. Here, the electron MA trout has an acceleration energy of INhV or more. These electron beams are N-epitaxial layer (2)
Although lattice defects are generated within the lattice defect, since this n serves as a recombination center for carriers as a deep trap level, carriers can be annihilated within a short time at the time of turn-off. The high-energy electron edge has a large penetrating power, so the outside air
Even if the sample is completely in the atmosphere, there is no problem in uniformly irradiating the entire sample to be irradiated, and there is an advantage that the sample can be easily installed and recovered.

しかしながら、空気中で電子線又はT線を照射した際、
空気中の酸素分子と衝突して反応した結果生成さnたオ
ゾン(0,)や活性酸素原子の被照射サンプルに与える
効果が、デバイス特性の劣化、あるいはライフタイム制
御を行なう上で、不安定になってしまうものである。
However, when irradiated with electron beam or T-ray in air,
The effects of ozone (0. It will become.

以下、こnを具体的に説明する。This will be explained in detail below.

オゾンの化学的性質として強酸化力が知らnており、酸
性下での還元電位は2.07Vとフリーラジカルや原子
のような不安定物質を除くと弗素についで2番目に高く
、又アルカリ性下でも1.24Vを示す。従って、金と
白金とを除いたすべての金属を酸化し、その他多くの元
素と反応する。
Ozone is known to have a strong oxidizing power as a chemical property, and its reduction potential under acidic conditions is 2.07V, which is the second highest after fluorine when unstable substances such as free radicals and atoms are excluded, and under alkaline conditions. But it shows 1.24V. Therefore, it oxidizes all metals except gold and platinum and reacts with many other elements.

幅射場におけるオゾンの分解反応は種々のものが知らn
ており、例えば紫外光によっては0、+b、/ (λ>
8 10  n、)−+0(”P)十〇、  (’ Δ
g)−(1)03+bν(λ<810 nm ) →Q
 (I D ) + 02 (Δg) ・・・(2)の
反応が起こる。
Various types of ozone decomposition reactions are known at firing ranges.
For example, depending on the ultraviolet light, 0, +b, / (λ>
8 10 n, )−+0(”P) 〇, (' Δ
g)-(1)03+bν(λ<810 nm) →Q
(ID) + 02 (Δg)...The reaction (2) occurs.

反応(1)では8重項の基底酸素原子と1重項の励起酸
素分子が生成し、反応(2)では1重項の励起状態酸素
原子と1重項の励起酸素分子が生成する。
In reaction (1), an octet base oxygen atom and a singlet excited oxygen molecule are generated, and in reaction (2), a singlet excited state oxygen atom and a singlet excited oxygen molecule are generated.

電子線が介在する状態ではオゾンが生成する反応経路の
他に Q2 +eleatron snsrgy →0 (”
P) +OCIF>     ・・・(3)OH+ s
l*etr*n @n@rgy −*O(”D) +O
(”P )   −(4)OB + el*atron
 @n@rgy→Oj+         ・・・(6
)の反応が起ξる。
In addition to the reaction path in which ozone is generated in the presence of an electron beam, Q2 +eleatron snsrgy →0 (”
P) +OCIF> ...(3)OH+s
l*etr*n @n@rgy −*O(”D) +O
(”P) −(4)OB + el*atron
@n@rgy→Oj+...(6
) reaction ξ occurs.

特に反応(5)はしきい値エネルギーがl 2eVと高
(02は化学的活性度が非常に高い。第4図番こ示した
ような高エネルギー電子線が存在する場合では支配的に
なると思わnる。
In particular, reaction (5) has a high threshold energy of 12 eV (02 has very high chemical activity. It is thought that it will become dominant in the presence of a high-energy electron beam as shown in Figure 4). nru.

このように副次的に発生した活性オゾン、活性酸素が5
iに与えろ影響を調べた結果を第5図に示す。予め75
0人の酸化膜が形成さnたSi基板に、空気中テI M
e V (7)電子線ヲI X l g14〜I X 
10”m/ r4照射した後の変化をpositron
 消滅性を用いて評価したものである。Po5itro
n消減法の詳細は、例えば、「月刊fQNI(S=イオ
ンの科学と技術= 1988年7月号」に記載さnてい
る。ここでは、第5図の要点のみを説明する。
The active ozone and active oxygen generated secondarily in this way
Figure 5 shows the results of examining the influence on i. 75 in advance
A Si substrate on which an oxide film was formed was exposed to heat in the air.
e V (7) Electron beam I X l g14~I X
Changes after irradiation at 10”m/r4 with positron
This is an evaluation using extinction property. Po5itro
The details of the n reduction method are described in, for example, "Monthly fQNI (S=Ion Science and Technology=July 1988 issue").Here, only the main points of FIG. 5 will be explained.

縦軸はS−param@*srであり、生のSiは約0
.585の値を示す。Sin、/Si界面ではこnより
低い値を示す。横軸はサンプルに注入されたP・sit
rom の加速エネルギーであり、深さ方向のパラメー
タを反映する。未照射サンプルの測定データよりPo5
itr@nの加速エネルギーが11KsVのとき、S−
piram@cerの値は最も低下しているが、とnが
750人の厚さをもったSJO,膜の界面の情報を与え
ている。電子線の照射量が増加するにっCて5−par
afflII&srの最も低下したポイントが高エネル
ギー側へ移動していることより、5iQ膜が成長してい
るのがわかる。
The vertical axis is S-param@*sr, and raw Si is approximately 0
.. It shows the value of 585. At the Sin, /Si interface, a value lower than this is shown. The horizontal axis is P-sit injected into the sample.
It is the acceleration energy of rom and reflects the parameters in the depth direction. Po5 from measurement data of unirradiated sample
When the acceleration energy of itr@n is 11KsV, S-
The value of piram@cer decreases the most, but it gives information on the interface of the SJO film with a thickness of n of 750. As the electron beam irradiation dose increases, C is 5-par.
It can be seen that the 5iQ film is growing from the fact that the point at which afflII&sr has decreased the most has moved to the higher energy side.

次に、デバイスの電気特性に与える影響を調べるため、
同じIGBTを同じ条件で電子線照射し、Vthの変化
を空気中の場合及び後述の発明に関わる真空中の場合で
比軟したのが第6図である。同図より真空中で照射した
サンプルの方が全体的にVtkが低めになっている違い
がわかる。この違いが活性オゾン、又は活性酸素に起因
するとした場合、該活性種が絶縁ゲートStO,とSi
界面まで侵入し、界面単位を形成する可能性が考えらn
る。
Next, to investigate the effect on the electrical characteristics of the device,
The same IGBT was irradiated with an electron beam under the same conditions, and the change in Vth was compared between the case in air and the case in vacuum related to the invention described later, as shown in FIG. From the figure, it can be seen that the Vtk of the sample irradiated in vacuum is lower overall. If this difference is due to active ozone or active oxygen, then the active species may be
There is a possibility that it may penetrate to the interface and form an interfacial unit.
Ru.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

このように、空気中で電子線又はγ線を照射した際、空
気中の酸素分子と衝突して反応した結果生成されたオゾ
ン(Os)や活性酸素原子の被照射サンプルに与える効
果が、デバイス特性の劣化、あるいはライフタイム制御
を行なう上での不安定要因に結びつく、という問題点が
あったぁこの発明は上記のような問題点を解消するため
になさnたもので、電子線を照射中に、空気中より発生
する活性オゾン、活性酸素その他の活性態がデバイスに
影響を及ぼさないようにすることを目的とする。
In this way, when electron beams or gamma rays are irradiated in the air, the effects of ozone (Os) and active oxygen atoms, which are generated as a result of collisions and reactions with oxygen molecules in the air, on the irradiated sample are There was a problem that it led to deterioration of characteristics or unstable factors in performing lifetime control.This invention was made to solve the above problems. The purpose is to prevent active ozone, active oxygen, and other active forms generated from the air from affecting the device.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体装置の製造方法は、複数の主電極
及び少なくとも一つの制御電場を有する半導体装置を真
空中あるいは不活性気体雰囲気中におき、その状態で高
エネルギー電子線又はγ線を照射するようにしたもので
ある。
A method for manufacturing a semiconductor device according to the present invention includes placing a semiconductor device having a plurality of main electrodes and at least one control electric field in a vacuum or an inert gas atmosphere, and irradiating the semiconductor device with high-energy electron beams or gamma rays in that state. This is how it was done.

〔作用〕[Effect]

この発明における真空、不活性気体雰囲気の導入は電子
線、γ線の照射中に副次的に発生する活性オゾン活性酸
素等と半導体装置とが接触することなく絶縁するように
作用するので、前記電子線、γ線は前記半導体装置内に
もっばら格子欠陥を形成する影響のみを与えるようにな
る。
In this invention, the introduction of a vacuum or an inert gas atmosphere acts to insulate the semiconductor device from the active ozone, active oxygen, etc. generated as a by-product during irradiation with electron beams and γ-rays without contacting the semiconductor device. Electron beams and gamma rays only have the effect of forming lattice defects within the semiconductor device.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第1図において、(ト)は半導体装置、(2)はこの半
導体装置USの支持台、(7)は半導体装置α0の処理
を行うテLンバー、(財)はチLンバー四内の排気を行
う真空ポンプ、4はマイラーなどの照射窓、−は真空領
域、■は高エネルギー電そ線である。#f縁員の照射に
よって外気−で発生した化学的活性種は真空領域(転)
に侵入できないので、半導体装置(至)の表面を酸化し
たり、内部に入り込んで新たな単位を導入する心配がな
くなる。
In Figure 1, (g) is a semiconductor device, (2) is a support stand for this semiconductor device US, (7) is a chamber for processing the semiconductor device α0, and (Foundation) is an exhaust gas inside chamber 4. 4 is an irradiation window such as Mylar, - is a vacuum area, and ■ is a high-energy electric wire. #f The chemically active species generated in the outside air by the irradiation of the edge member are transferred to the vacuum region (transfer).
Since it cannot penetrate into the semiconductor device, there is no need to worry about oxidizing the surface of the semiconductor device or entering the inside and introducing new units.

第2図はこの発明の他の実施例を示す図である。FIG. 2 is a diagram showing another embodiment of the invention.

図において、弼は給気口、−は不活性気体、(2)は排
気口、である。電子@SOの照射によって外気−で発生
した化学的活性種は不活性気体領域−に侵入できず、か
つ不活性気体領域−内では化学的活性種が発生しないの
で、上記実施例と同様、半導体装置[相]の表面が酸化
さnたり、内部に新たな単位が導入さnたりする心配が
なくなる。
In the figure, (b) is an air supply port, - is an inert gas, and (2) is an exhaust port. Chemically active species generated in the outside air by electron @SO irradiation cannot enter the inert gas region, and no chemically active species are generated within the inert gas region. There is no need to worry about the surface of the device [phase] being oxidized or new units being introduced into the interior.

第8図はこの発明のさらに他の実施例を示す図である。FIG. 8 is a diagram showing still another embodiment of the present invention.

図において、(2)は導電性厚膜材、−は真空領域又は
不活性気体充填領域である。こnは予め、導電性厚膜材
(2)で半導体装置(転)を密封する。
In the figure, (2) is a conductive thick film material, and - is a vacuum region or an inert gas filled region. In this case, the semiconductor device (transfer) is sealed in advance with a conductive thick film material (2).

その後の工程は基本的1こ上述の方法と同一であり、電
子線を用いたライフタイム制御の利点の一つである工程
作業の簡便さは同じである。
The subsequent steps are basically the same as the first method described above, and the simplicity of process work, which is one of the advantages of lifetime control using electron beams, is the same.

なお、こnらの方法により形成さnた半導体装置の電気
特性は、第6図に従来のものと比較して示しである。
The electrical characteristics of the semiconductor device formed by these methods are shown in FIG. 6 in comparison with a conventional one.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によnば、半導体装置を真空中又
は不活性気体雰囲気中に設置し、高エネルギー電子線、
又はγ線を照射するようにしたので、照射後、高エネル
ギー電子線又はγ線によって影譬を受けた外気と半導体
装置とが接触することがないのでライフタイム制御の制
御性、信頼性が向上された半導体装置を得ることができ
る。
As described above, according to the present invention, a semiconductor device is installed in a vacuum or an inert gas atmosphere, and a high-energy electron beam,
Or, since γ-rays are irradiated, the semiconductor device does not come into contact with the outside air affected by high-energy electron beams or γ-rays after irradiation, improving the controllability and reliability of lifetime control. A semiconductor device can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例による半導体装置の製造方
法を示す断面模式図、第2図はこの発明の他の実施例に
よる半導体装置の製造方法を示す断面模式図、第8図は
この発明によるさらに他の実施例による半導体装置の製
造方法を示す断面模式図、第4図は従来の技術による半
導体装置の製造方法を示す断面模式図、第5図は空気中
での電子線照射により、副次的に発生した活性種が5i
表面に与える影響をpogf龜ron消減法を用いて測
定したデータを示す図、第6図は従来例における空気中
及びこの発明に関する真空中でIGBTに電子線を照射
した際のVtbの変化のデータを比較して示した図であ
る。 図において、QOは半導体装置、(1)はチェンバー(
2)は導電性唖膜材、−は外気、−は真空、−は不活性
気体、−は真空領域又は不活性気体充填領域、輪は高エ
ネルギー電子線又はγ線である。 なお、各図中同一符号は同一、又は相当部分を示す。
FIG. 1 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to another embodiment of the invention, and FIG. FIG. 4 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to still another embodiment of the invention, FIG. 4 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to the conventional technique, and FIG. , the secondary generated active species are 5i
Figure 6 shows the data of the influence on the surface measured using the POGF Ron extinction method. Figure 6 shows the data on the change in Vtb when an IGBT is irradiated with an electron beam in the air in the conventional example and in vacuum in the present invention. FIG. In the figure, QO is a semiconductor device, (1) is a chamber (
2) is a conductive membrane material, - is outside air, - is a vacuum, - is an inert gas, - is a vacuum region or an inert gas filled region, and the ring is a high-energy electron beam or gamma ray. Note that the same reference numerals in each figure indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims]  複数の主電極及び少なくとも1つの制御電極を有する
半導体装置を真空中あるいは不活性気体雰囲気中におき
、その状態で高エネルギー電子線又はγ線を照射するよ
うにしたことを特徴とする半導体装置の製造方法。
A semiconductor device having a plurality of main electrodes and at least one control electrode is placed in a vacuum or an inert gas atmosphere, and is irradiated with high-energy electron beams or gamma rays in that state. Production method.
JP18619790A 1990-07-13 1990-07-13 Manufacture of semiconductor device Pending JPH0472736A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18619790A JPH0472736A (en) 1990-07-13 1990-07-13 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18619790A JPH0472736A (en) 1990-07-13 1990-07-13 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0472736A true JPH0472736A (en) 1992-03-06

Family

ID=16184082

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18619790A Pending JPH0472736A (en) 1990-07-13 1990-07-13 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0472736A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011155068A (en) * 2010-01-26 2011-08-11 Oki Semiconductor Co Ltd Method of manufacturing semiconductor device, and substrate housing structure

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4869480A (en) * 1971-12-22 1973-09-20
JPS4919775A (en) * 1972-03-01 1974-02-21
JPS5338988A (en) * 1976-09-21 1978-04-10 Nec Corp Manufacture of semiconductor control rectifier
JPS54140461A (en) * 1978-04-24 1979-10-31 Hitachi Ltd Manufacture of semiconductor device
JPS5533020A (en) * 1978-08-28 1980-03-08 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS5919090A (en) * 1982-07-22 1984-01-31 Toshiba Corp Sealing method of semiconductor element
JPS5923743B2 (en) * 1981-12-24 1984-06-04 旭化成株式会社 Resin composition for polyethylene powder coating
JPS63117442A (en) * 1986-11-05 1988-05-21 Nec Corp Electron-beam measuring instrument
JPH0235007B2 (en) * 1981-11-23 1990-08-08 Yunion Shideryurujiku Deyu Nooru E Do Resuto Do Ra Furansu Usinor

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4869480A (en) * 1971-12-22 1973-09-20
JPS4919775A (en) * 1972-03-01 1974-02-21
JPS5338988A (en) * 1976-09-21 1978-04-10 Nec Corp Manufacture of semiconductor control rectifier
JPS54140461A (en) * 1978-04-24 1979-10-31 Hitachi Ltd Manufacture of semiconductor device
JPS5533020A (en) * 1978-08-28 1980-03-08 Mitsubishi Electric Corp Manufacture of semiconductor device
JPH0235007B2 (en) * 1981-11-23 1990-08-08 Yunion Shideryurujiku Deyu Nooru E Do Resuto Do Ra Furansu Usinor
JPS5923743B2 (en) * 1981-12-24 1984-06-04 旭化成株式会社 Resin composition for polyethylene powder coating
JPS5919090A (en) * 1982-07-22 1984-01-31 Toshiba Corp Sealing method of semiconductor element
JPS63117442A (en) * 1986-11-05 1988-05-21 Nec Corp Electron-beam measuring instrument

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011155068A (en) * 2010-01-26 2011-08-11 Oki Semiconductor Co Ltd Method of manufacturing semiconductor device, and substrate housing structure

Similar Documents

Publication Publication Date Title
US5900652A (en) Apparatus for the localized reduction of the lifetime of charge carriers, particularly in integrated electronic devices
CN102054876B (en) Fast recovery diode
US8450777B2 (en) Method for manufacturing a reverse-conducting insulated gate bipolar transistor
CN1106686C (en) Semiconductor apparatus with crystal defects and process for its fabrication
US8999824B2 (en) Method for manufacturing semiconductor device by performing multiple ion implantation processes
JPH09121052A (en) Semiconductor device and manufacturing method thereof
US8637328B2 (en) Integrated circuit having doped semiconductor body and method
US20250201563A1 (en) Semiconductor device and method of manufacturing semiconductor device
US5219773A (en) Method of making reoxidized nitrided oxide MOSFETs
US5883403A (en) Power semiconductor device
WO2010050130A1 (en) Semiconductor device and method for manufacturing same
CN101847579B (en) For the method manufacturing power semiconductor
US20240282845A1 (en) Method of manufacturing semiconductor device
JP2004165619A (en) Semiconductor substrate and its manufacturing method, and semiconductor device and its manufacturing method
JP2007012972A (en) Semiconductor device and manufacturing method thereof
JPH0722198B2 (en) Insulated gate type bipolar transistor
JPH09232332A (en) Semiconductor device
JPH10261704A (en) Semiconductor device and manufacturing method thereof
JPH0472736A (en) Manufacture of semiconductor device
JP3211874B2 (en) Method for manufacturing semiconductor device
US20020031889A1 (en) Method for manufacturing a semiconductor device
KR950001170B1 (en) Manufacturing Method of Switching Semiconductor Device
CN117690964A (en) Semiconductor device and manufacturing method thereof
KR100914280B1 (en) Gate forming method of semiconductor device using heterogeneous ion implantation
US20240304664A1 (en) Fast recovery diode and method for manufacturing the same