JPH0480063U - - Google Patents
Info
- Publication number
- JPH0480063U JPH0480063U JP1990124420U JP12442090U JPH0480063U JP H0480063 U JPH0480063 U JP H0480063U JP 1990124420 U JP1990124420 U JP 1990124420U JP 12442090 U JP12442090 U JP 12442090U JP H0480063 U JPH0480063 U JP H0480063U
- Authority
- JP
- Japan
- Prior art keywords
- insulating substrate
- lower electrode
- semiconductor device
- hole
- metallization
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
第１図はこの考案の一実施例である半導体装置
のキヤパシタンス部の斜視図、第２図は第１図の
−線における断面図、第３図は従来の半導体
装置のキヤパシタンス部の斜視図、第４図は第３
図の断面図である。図において、２は絶縁体基板
、３はメタライズパターン、４はトランジスタ、
６は誘電体層、７はキヤパシタンス上部電極、８
はキヤパシタンス下部電極、９はスルーホールを
示す。なお、図中、同一符号は同一、又は相当部
分を示す。
FIG. 1 is a perspective view of a capacitance section of a semiconductor device that is an embodiment of this invention, FIG. 2 is a sectional view taken along the - line in FIG. 1, and FIG. 3 is a perspective view of a capacitance section of a conventional semiconductor device. Figure 4 is the third
FIG. In the figure, 2 is an insulator substrate, 3 is a metallized pattern, 4 is a transistor,
6 is a dielectric layer, 7 is a capacitance upper electrode, 8
9 indicates a capacitance lower electrode, and 9 indicates a through hole. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
された混成集積回路において、前記絶縁体基板内
に設けられた誘電体に上部電極、下部電極を設け
、前記下部電極と前記絶縁体基板上メタライズと
をスルーホールによつて接続することにより形成
されたキヤパシタンスを利用したことを特徴とす
る半導体装置。 In a hybrid integrated circuit in which various active elements and passive elements are mounted on an insulating substrate, an upper electrode and a lower electrode are provided on a dielectric provided in the insulating substrate, and the lower electrode and the metallization on the insulating substrate are provided. A semiconductor device characterized in that it utilizes capacitance formed by connecting the two through a through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990124420U JPH0480063U (en) | 1990-11-26 | 1990-11-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990124420U JPH0480063U (en) | 1990-11-26 | 1990-11-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0480063U true JPH0480063U (en) | 1992-07-13 |
Family
ID=31872072
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990124420U Pending JPH0480063U (en) | 1990-11-26 | 1990-11-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0480063U (en) |
-
1990
- 1990-11-26 JP JP1990124420U patent/JPH0480063U/ja active Pending