JPH042054U - - Google Patents

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Publication number
JPH042054U
JPH042054U JP4294690U JP4294690U JPH042054U JP H042054 U JPH042054 U JP H042054U JP 4294690 U JP4294690 U JP 4294690U JP 4294690 U JP4294690 U JP 4294690U JP H042054 U JPH042054 U JP H042054U
Authority
JP
Japan
Prior art keywords
chip
integrated circuit
circuit device
semiconductor integrated
active element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4294690U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4294690U priority Critical patent/JPH042054U/ja
Publication of JPH042054U publication Critical patent/JPH042054U/ja
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本考案による半導体集積回路装置の
一実施例の断面図、第2図a〜gは第1図に示す
実施例の製造プロセスを示す断面図である。 1……半導体基板、2……バイアホール構造引
き出し電極、3……キヤパシタ上部電極、4……
誘電膜、5……キヤパシタ下部電極、6……フオ
トレジスト、6a……リフトオフ用開口パターン
、7……フオトレジスト、7a……バイアホール
形成用開口パターン、8……バイアホール、9…
…半導体集積回路装置。
FIG. 1 is a sectional view of an embodiment of a semiconductor integrated circuit device according to the present invention, and FIGS. 2a to 2g are sectional views showing the manufacturing process of the embodiment shown in FIG. 1... Semiconductor substrate, 2... Via hole structure extraction electrode, 3... Capacitor upper electrode, 4...
Dielectric film, 5... Capacitor lower electrode, 6... Photoresist, 6a... Opening pattern for lift-off, 7... Photoresist, 7a... Opening pattern for via hole formation, 8... Via hole, 9...
...Semiconductor integrated circuit device.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体チツプの表面に能動素子又は能動素子及
び抵抗パターンを有するとともに、チツプ裏面に
キヤパシタ素子又はインダクタ素子等の受動素子
を有することを特徴とする半導体集積回路装置。
A semiconductor integrated circuit device comprising an active element or an active element and a resistance pattern on the front surface of a semiconductor chip, and a passive element such as a capacitor element or an inductor element on the back surface of the chip.
JP4294690U 1990-04-20 1990-04-20 Pending JPH042054U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4294690U JPH042054U (en) 1990-04-20 1990-04-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4294690U JPH042054U (en) 1990-04-20 1990-04-20

Publications (1)

Publication Number Publication Date
JPH042054U true JPH042054U (en) 1992-01-09

Family

ID=31554935

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4294690U Pending JPH042054U (en) 1990-04-20 1990-04-20

Country Status (1)

Country Link
JP (1) JPH042054U (en)

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