JPH048100A - Audio signal processing unit provided with directivity emphasis - Google Patents

Abstract

PURPOSE:To reduce the number of steps processed for each sampling period by dividing the processing for left and right channel digital data inputted for each prescribed sampling period into a block completed for each sampling period and a block completed at a period being a multiple of N of the period. CONSTITUTION:First and 3rd blocks 11, 13 are operated at a sampling frequency fS. Then the execution of a program for processing both blocks is finished till a succeeding data is inputted every time digital data LIN, RIN of left and right channels are inputted. On the other hand, a 2nd block 12 is operated at 1/N of the sampling frequency fS. Then the program is divided almost uniformly into 1/N and each of the program is implemented before and after the execution of the program for the 1st and 3rd blocks for each sampling period. Since the data processing circuit is controlled simultaneously by the same program, the number of program steps is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a signal processing device for audio signals, and particularly to an audio signal processing device having directional emphasis.

(b) Conventional technology In recent years, stereo systems have been developed that effectively realize three-dimensional sound field reproduction in movie theaters. Stereo devices have been developed that add surround channels to the rear of the left and right channels of conventional stereo devices, making it possible to reproduce a three-dimensional sound field even at home.

Furthermore, a more advanced surround stereo system has recently been announced that can produce a three-dimensional sound field reproduction effect almost equivalent to that of a movie theater. A major feature of this is that the audio signals of the left and right channels of the original sound are subjected to signal processing called directional enhancement to clarify the localization of the sound. In this method of reproduction, the left channel is created from the left and right audio signals, and a right channel R, surround channel S, and center channel C are created. Moreover, at that time, directional emphasis is added based on the level difference between the left and right signals.

FIG. 8 is a circuit block diagram of a signal processing device that performs directionality enhancement.

The audio signals of each channel L and R are input to a bandpass filter (1), and bands unnecessary for level detection are removed. From the output of the bandpass filter (1), an addition and subtraction circuit (2) creates LR (surround channel S) and L+RC center channel C) signals. Then, the audio signal of each channel is rectified by a full-wave rectifier circuit (3) and converted into voltages Lv, Rv, Sv, Cv indicating the level of each channel, and further the level of each channel Lv, Rv, Sv, For Cv, the level difference of each channel, LvRv, and Cv Sv are logarithmically converted by a differential input logarithmic conversion circuit (4). The logarithmically converted level differences Lv Rv and Cv Sv are integrated by an integrating circuit (5). The integrating circuit (5) is
The integration time constant is switched by a time constant switching circuit (6) that detects the speed of change in the level differences Lv-Rv and CV-Sv. Integrated level difference Lv Rv, Cv
Sv is divided into four control signals E by the polarity determination circuit (7).
L, ER, Eo, and Es are created. That is, R/L〉1
In the case of , a voltage according to the integral value of Lv-Rv is output to EL, and when R/L<1, a voltage according to the integral value of Lv-Rv is output to ER, and S/C>1 In the case of Ec, C
A voltage corresponding to the integral value of vSv is output, and if S/C<1, a voltage according to the integral value of CvS9 is output to E8.

VCA (voltage controlled amplifier) (8)
amplifies the input left channel L and right channel R audio signals by amplifiers controlled by control signals EL, EFI, Eo, and Es, respectively, and outputs eight signals. These 8 signals, left channel L and right channel R
The audio signals of L
, R, C, and S channel signals are created and output. This output becomes a directionally emphasized signal.

This technique is described in detail in Nikkei Electronics, June 27, 1988 (No. 450), pages 88 to 89.

(C) Problems to be Solved by the Invention The audio signal processing device having directional emphasis shown in FIG. 8 processes left and right channel audio signals input in analog form as they are in analog form.

However, recently, a DSP (digital signal processor) for audio signals has been developed, and it has become possible to easily perform processing such as a graphic equalizer and reverberation digitally without deteriorating the sound quality. That is, an analog audio signal is converted into a digital signal, this digital signal is processed to realize various sound effects inside the DSP, and the resulting digital pressure is converted back into an analog signal. Here, the sampling frequency of AD and DA conversion is 48KH, 44, 1KH2 or 3KH2.
2 KHz is used.

Therefore, it has been considered to use DSP to realize an audio signal processing device with directional emphasis as shown in Fig. 8. However, for example, the DSP Executing all the processes shown in FIG. 8 requires an enormous number of steps, making it difficult to implement L. Or a DSP that operates at very high speeds
Because of the high cost required, it is not possible to create an audio device that is acceptable to general consumers.

Further, when the integrating circuit (5) and the time constant switching circuit (6) in FIG. 8 are constructed using a DSP, both are constructed using a digital low-pass filter. However, the integrating circuit (5) and the time constant switching circuit (6)
Since the cutoff frequency is very low at 782 or 0.34Hz, at a sampling frequency of 44.1KHz,
There is a problem in that the multiplication constant of the digital filter constituting this is insufficient even for an L32-bit DSP, which has a very large number of points of focus on data representing the L multiplication constant, which has a long number of significant digits after the decimal point.

(d) Means for Solving the Problems The present invention has been created in view of the above-mentioned points.The present invention has been created in view of the above-mentioned points. In an audio signal processing device that performs directional enhancement by detecting and amplifying or attenuating the level of each output channel based on the detection result, digital data of the left channel and right channel input at every predetermined sampling period is input. By dividing the processing of the digital data into blocks that are completed in each sampling period and blocks that are completed in a period that is N times the sampling period, data representing a multiplication constant of a digital filter with a low cutoff frequency is obtained. The number of bits can be reduced, and the number of steps processed in each sampling period can also be reduced.

(e) Effect: According to the above-mentioned means, L+R, (C) and L-R(S) are calculated from the digital audio data L and R of the left channel and right channel that are input every sampling period, and If the operation of full-wave rectification and integration of L5, R, C, and S is performed every sampling period, the eight factors of full-wave rectification and integration do not change much in the sampling period (because of this, the full-wave rectification and integration The operation of calculating eight coefficients based on the pressure of A level difference calculating means for calculating a level difference, a level detecting means for integrating each output of the level difference calculating means with a first digital low-pass filter and detecting that a predetermined level has been reached, a second digital low-pass filter whose constant is controlled to be switched and receives the output of the level difference calculating means; a polarity determining means for distributing the output according to the sign of the output of the second digital low-pass filter; and an output of the polarity determining means. The operations of the anti-logarithmic conversion means for anti-logarithmic conversion and the coefficient creation means for creating a plurality of coefficients based on the pressure of the anti-logarithm conversion means can be performed at a period N times the sampling period. , the number of bits of the multiplication coefficients constituting the first digital low-pass filter and the second digital low-pass filter can be reduced (and these operations can be reduced to 1/2).
The number of steps per sampling period can be reduced.

(F) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention. (
Reference numeral 11) is a first block which receives L left channel digital data LIN and right channel digital data RI and operates at every sampling period of 1/fs. (
12) is the second block that inputs and processes the digital data output from the first block, and has an L sampling period of 1.
This block operates at a cycle that is N times /fs. (
13) is the third block, which operates at every sampling period of 1/f8, like the first L block.

Each block will be explained in detail below.

The first block has a sampling period of 1/f8, for example,
fs = 44.1KHz), add the digital bandpass filter (14) that inputs the left channel digital data LIN and right channel digital data RIN, and the 8 forces and R of the digital bandpass filter (14). and an adder (1) that creates center channel data C.
5), a subtracter (16) that subtracts L−R from the output of the digital bandpass filter (14) to create surround channel data S, and a subtracter (16) that creates surround channel data S. R. C.
It is composed of a digital bypass filter (+7) that inputs S, and a full-wave rectifier (18) that full-wave rectifies the output data of each digital bypass filter (17).

Here, the digital band pass filter (14) is for removing unnecessary frequency components for level detection of each channel, and is a 3-stage continuously connected IIR digital filter as shown in FIG. Consists of. In FIG. 2, (19) is a delay element that holds data from one sampling ago, +29) is a multiplier that multiplies input data by a predetermined constant, and (21) is an adder. In this embodiment, the first and second stage digital filters are bypass filters with a cutoff frequency of 10 Hz, and the third stage digital filter has a cutoff frequency of 5 kHz. It is a ronos filter.

The digital bypass filter (17) of the first block is
It has the same configuration as the first stage of the digital filter shown in FIG. 2, and the L cutoff frequency is set to 21,887.

Further, the full-wave rectifier (18), as shown in FIG.
It is composed of an absolute value calculation circuit (22) and a low-pass filter (23). The absolute value calculation circuit (22) determines whether the most significant bit of the input digital data is 0''' or 1''.
In the case of "o", the input digital data is output as is, and in the case of "1", the complement of the manually input digital data is calculated and output. The 80-bass filter (23), which functions to perform full-wave rectification of digital data, is a digital low-pass filter with a cant-off frequency of 14H2, which functions as an integrator for full-wave rectification, and which functions as an absolute value calculation circuit (22). Smooth the full-wave rectified output. Furthermore, the low-pass filter (23) also acts as an antialias filter, and when the second block operates at a sampling period of N/f8, the frequency of the output signal of the first block and the sampling frequency of the second block are f8/N. It also serves as a filter to prevent interference.

Further, the low-pass filter (23) is formed in a format different from the digital filter format shown in FIG. 2 (referred to as a 2D type). That is, the low-pass filter (23) has a 14H
Since it is a low-pass filter of z, it is configured to prevent deterioration of multiplication accuracy, and like the digital filter in Figure 2, it adds the result of multiplying input data by a coefficient and the result of multiplying delayed data by a coefficient. Instead, by adding the result of multiplying the delayed data by a coefficient to the input data, a reduction in the number of effective digits can be prevented.

The second bronch (12) operates at a period N times the sampling period 1/f. That is, the sampling period 1/f
, the pressure of the full-wave rectifier (18) outputted every time is the integration result of the low-pass filter (23), so the change in data is gradual, that is, the frequency is low. (12) allows the sampling frequency to be lowered. In this example, a full-wave rectifier (
Considering the output frequency of 18), a sampling frequency of 1/16, 275 KH, is adopted.

Here, the second block (12) is a logarithmic converter (2) which inputs the digital data of each channel outputted from the first block every 16 pieces and logarithmically converts the digital data.
4) and the outputs Le, Re, Ce of each logarithmic converter (24)
, a subtractor (25) for calculating the level difference Le-Re and Ce-9e of Se, a level detector (26) for inputting Le-Re and CeSe, respectively, and a subtracter (25) for calculating the level difference Le-Re and Ce-9e,
a digital low-pass filter (27) that inputs each of Logarithmic converter (29
) and a coefficient calculator (30) that calculates eight coefficients based on the output of the anti-logarithm converter (29).

Here, the logarithmic converter (24) uses a table in which input data and logarithmic output data are stored in a memory such as a ROM in advance. Alternatively, the logarithmic output may be obtained by an approximation operation based on the input data, that is, an operation such as Tievisiev approximation or Taylor approximation.

Level detection R (26) and digital low-pass filter (
27) is formed as shown in FIG. Level detector (2
6) includes a digital low-pass filter (31) with a cutoff frequency of 7 Hz, a level determiner (32) that detects when the output data of each digital low-pass filter (31) is below a predetermined value, and a level determiner. AND gate (
33). The digital low-pass filter (27) is composed of a digital low-pass filter (34) with a cutoff frequency of 0.34 Hz and a digital low-pass filter (35) with a cutoff frequency of 7Hz.The input of the L digital low-pass filter (35) is as follows. Swift (36) controlled by the output of AND gate (33)
The level difference data Le-Re and C
When both e-3e are small and both judgment outputs are pressured from the level judgment device (32), the output of the digital low-pass filter (34) is not applied to the digital low-pass filter (35), otherwise the level difference data Le -Re and Ce-5e are each applied to a digital low pass filter (35).

Since the digital low-pass filters (31), (34), and (35) in the second bronch (12) are ultra-low-pass filters, they are 2D filters like the digital low-pass filter (23) mentioned above so as not to degrade the multiplication accuracy. It has become a type. Also, since the sampling frequency of this second block (12) is as low as 2.75 KHz, these digital low-pass filters (3I), (34), and (35
) can be kept to about 16 bits.

The polarity discriminator (28) includes a digital low-pass filter (28).
7) The polarity of each pressure ELR and ECS, that is, each output E
LR and EC8 determine whether it is positive or negative.As shown in FIG. 5, an absolute value calculator (37), a -1 multiplier (38), an adder (39), 1/2 multiplier (4
For example, when ELR is positive, the pressure of absolute value field a (3a) is ELR and L adder (39
) The pressure on one side is 2ELR, and the output on the other side is 0. Therefore, -ELR is multiplied by 8 to the output EL' of the multiplier (4o), and the output ER' of the other multiplier (40) becomes 0. Conversely, when ELR is negative, 0 is output to EL' and ELR is output to ER'. The same applies to EC8.

The antilogarithmic converter (29) uses a table such as a ROM that stores logarithmic input and output data similarly to the logarithmic converter (24).
, ER', EC', and ES' are inverse logarithmically transformed to create data EL EREClES for applying directionality emphasis.

The coefficient calculator (30) receives data EL, ER, and EC.

Based on the ES, eight coefficients are created to multiply the left channel digital data LIN and the right channel digital data RIH, and are configured as shown in FIG.

Constants LL, CL, CRRR Data EL, ER, EC
, ES by a predetermined constant using a multiplier (41), and adding the multiplication result and a predetermined constant using an adder (42), constants LR and RL are obtained by multiplying data EC and ES by a predetermined constant, respectively. The constants SL and SR are obtained by multiplying a predetermined constant by a multiplier (41) and adding the multiplication results by an adder (42).
It is obtained by multiplying R and EC by respective fixed constants in a multiplier (41), and adding the multiplication result and a predetermined constant in an adder (42).

The third block, like the first block, is a block that operates at the sampling frequency fs, and uses the coefficient values LL, OL, RL, and SL output from the second block to the left channel digital data L+s input every L sampling period. a multiplier (43) that multiplies the right channel digital data RIH by coefficient values LR, OR, RR, and SR, respectively; By adding, the digital data of each channel L゛,
An adder (45) that creates R and C'S, and a digital bypass filter (45) that inputs channel data C, removes the low frequency part, and outputs center channel data C0UA.
46) and the output data of the digital bypass filter (46) from the channel data C' to obtain the low frequency part of the center channel, and add this to the channel data L' and R' to obtain the left channel digital data L. A subtracter (47) and an adder (48) that output as 0 and right channel digital data Ro, J, a delay element (49) that delays channel data S°, and a delay element (4
9) and removes the high frequency portion to generate surround channel digital data S. It is composed of a low-pass filter (5o) that outputs Ua. Here, the digital bypass filter (46) has a cant-off frequency of 100H.
The cant-off frequency of the L digital low-pass filter (50) at z is 7KH2.

This third block contains coefficient values LL, CL, RL, SL.
and coefficient values LR, CR, RR, SR are 1 of the third block.
The third block is supplied once every six operations, and the third block performs processing using the same supplied data until the next data is supplied. Output processed by the third block. I.J.T., R.

ut, Goυ↑, S QLI7 is an output with directionality emphasis.By converting this into DA and reproducing it, an effective three-dimensional sound field can be reproduced.

In this way, the first and third blocks are operated at a sampling frequency f s = 44, 1 kHz, and the second block is operated at a sampling frequency of 1/16, 275 KHz.
By operating at Hz, the coefficient accuracy of the L low frequency digital low-pass filters (3]), (34), and (35) can be ensured.

That is, the three multiplication coefficients a, b of the low frequency digital filter
, C is a=ω. /(ωo+2 f 5) b=ω. /(ωo+ 2 f5) c=(ωo-2fsl/(ωo+ 2 f8)(A)O
= 2 f Btan(W f c/ f 5lls=
Sampling frequency, f8 = cuft-off frequency). Therefore, in a very low-pass filter,
The higher the sampling frequency, the lower f0/fB becomes
Because it is close to ω. becomes close to O.

Therefore, a#0, b丑0. The number of significant digits of the L coefficient becomes longer, such as c#-1. Therefore, if the sampling frequency f5 is lowered, the value of f C/ f8 becomes larger, L coefficient a,
The number of significant digits of b and c is short, improving coefficient accuracy.

Next, FIG. 7 shows an SP that is optimal for realizing the audio signal processing device with directional emphasis shown in FIG. This DSP has a pair of data buses (BUS 1)
(BUS2) (51+ and the data bus (BUS1)
) (BUS2) +51) and the digital processing circuit +52) +53) connected to the data bus (Bus 1)
) (BUS2) (511), the data input/output circuit (54), the interface circuit (55), the external memory interface circuit (56), the data exchange register (57), and the memory connected to the data bus (BUS2). A control register (58), a conditional branch control circuit (59),
This is a DSP system for audio signal processing that is connected to a data bus (BUS2) and is composed of a control circuit (60) that controls the operation of each of the circuits. This DSP system is integrated on a Wangchinbu semiconductor device. be.

Each data bus (51) is composed of 24 bits (8 pins x 3). The data input/output circuit (54) serially inputs 16 bits of left channel and right channel sampling data applied externally to the input terminal IN, and the right channel data is input to the data bus BUSI, and the right channel data is input to the data bus BUSI. It sends the data to the data bus BUS2, and receives the processed data sent to the data buses BUS1 and BUS2, and serially compares it from the L output terminal OUT.

The data processing circuit (52) is for data processing of the right channel, and the data processing circuit (53) is for processing data of the left channel, and they have exactly the same configuration. That is, data processing circuit (52) (531 is data RAM (61), constant RAM (62), constant ROM+63), address pointer f64) (65) (66) 1 multiplier (MU
LH67), ALU (68), accumulator (ACC) (69), temporary register (TMPI
~TMP8) (70). Data RAM (6
Reference numeral 11 denotes 24 which stores unprocessed data sent from the data input/output circuit (54) and data after arithmetic processing.
It has a capacity of 128 bits and is connected to the data bus (51) and the input of the multiplier (67). Constant RAM +
62) is a 16-biff) X2 that stores the coefficients of the digital filter sent out from the interface circuit (55).
It has a capacity of 56, a data bus (51), a multiplier (67
) and ALU (connected to the input of 681. Also, constant ROM +83) fixedly stores fixed multiplication coefficients of the digital filter, data tables for logarithmic conversion and anti-logarithmic conversion, etc. 24 bits x 256
This read-only memory is connected to the L data bus (5I) and the input of the multiplier (67).

The address pointer (64) is composed of 8 bits and specifies the address of the data RAM (61), and is controlled by the microcodes INCl and DECI output from the L control circuit (60). In addition, the address pointer (6
5) is 1 that specifies the address of constant RAM (62)
It is a 0-bit pointer and is controlled by the microcode INC2 output from the L control circuit (60). Furthermore, the address pointer (66) is an 8-bit pointer that specifies the address of the constant ROM (63), and is an 8-bit pointer that specifies the address of the constant ROM (63).
) is controlled by microcode DEC3.

The multiplier (67) performs 24-bit x 16-bit multiplication, the LA input is 24 bits, the input is 16 bits, and the multiplication result is determined after one cycle.

Further, input selection circuits MPXA and MPXB are provided for the input A and input B of the multiplier (b) 7), and the input selection circuit M
PXA is microcode A from the control circuit (60)
-BUS NIOl1l) Select the data bus (51) and load the data RAM using the microcode A-DRAM.
(Select 611 and apply it to A human power, input selection circuit MP
The XB is connected to the data bus (
51), select constant RAM (62) by microcode B-ORAM, and select microneed B-C
ROMk constant ROM (0 multiplication result selected by 631 and applied to B input is pressed by 32 pinto.

ALU (68) is a 32-pin arithmetic circuit that adds the 32-bit multiplication result input to one side and the 32-bit ACC (69) data input to the other side using the microcode ADD, and adds the result. The result is ACC(
69). Of the 32 bits of ACC (691), the upper 24 bits are connected to the data bus (51), and the lower 8 pins are connected to the lower 8 bits of the temporary register (70) by the auxiliary bus (71). Register (70) is a 32-bit register T
Consists of MPI, TMP2...TMP8, 3
It is a register that holds up to 8 pieces of 2-pin data, and the upper 24 bits of each L are connected to a data bus (51). The data bus (51) and the auxiliary bus (71) allow 3
2-bit data is transferred.

The control circuit (60) controls each section circuit according to a preprogrammed procedure, but it is also possible to control each section circuit of the data processing circuit f52) +53) simultaneously or independently. This control circuit (60
) has a built-in program ROM (or RAM), and by executing the program read from the program ROM, the L address pointer (64) (65) (6
8) Control lNCl, lNC2゜DECI, CLE
AR2, DEC3; A-Bus A-DRAM, B-BUS, B-C that controls input selection circuits MPXA and MPXB
RAM, B-CROM; A that controls AL] 681
DD, THR, MD; CHG that controls the data exchange register (57); 0 that controls the conditional branch control circuit (59)
VFR, 5IFR, CAFR, BOFR; MBDL, etc. that control the storage control register (58) are output.

The interface circuit f55) connects the DSP system and an external control device, such as a microcomputer (not shown).
It is used to send and receive data between.

The external memory interface circuit (56) is a circuit for specifying addresses and transmitting and receiving data to and from a memory externally connected to the DSP system.

The data exchange register (57) holds the data sent to the data bus BUS1, and the 24-pin R→L register (57a) outputs the data to the data bus BUS2, and the data exchange register (57) holds the data sent to the data bus BUS2. 24-bit signal output to data bus BUS 1 + R register (
57b), and when the exchange command is executed, the control circuit (
During the L1 instruction cycle, data retention and output are controlled by the control signal CHG output from the R-L register (57).
a) and L→R register (57bl) at the same time.

Therefore, the digital data of the right channel and the digital data of the left channel can be exchanged with each other, and signal operations such as multiplying the data of the opposite channel by a predetermined coefficient and adding or subtracting the two from their own digital data can be performed.

The conditional branch control circuit (59) outputs a signal that is output when the digital processing output of the ALU (681) of each digital processing circuit (52+(53)) reaches a predetermined state.

It selects based on data applied from data bus BUS2 and generates jump control signal JMP.

When the signal processing device shown in FIG. 1 is implemented using the DSP shown in FIG. 7, the digital processing circuits (52) and (53) of the DSP can each perform processing at the same time. That is, the digital bandpass filter (14) that filters the digital cheaters of the left channel and the right channel that are input after AD conversion is formed independently in each of the digital processing circuits (52) and (53), and the output results are is DsPO) f - evening exchange Li sister (57
) to each of the digital processing circuits (52) (53). Thereafter, basically, the left channel and right channel are processed by the digital processing circuit (52), and the center channel and surround channels are processed by the digital processing circuit (53).

Furthermore, in each of the digital processing circuits (52) (531), when realizing the various digital filters shown in FIGS.
Addition and subtraction are performed by A L U +68+, i.e., the digital data input to the filter is applied to the input A of the multiplier (67), and the filter coefficient is stored in the constant ROM.
It is read out from the data RAM (611) and applied to the input B to perform multiplication, and then the data from one sampling ago is read out from the data RAM (611) and multiplied by the filter coefficient from the constant ROM I63 in the multiplier (67). While repeating this multiplication, the multiplication results output from the multiplier (67) are A L U
By repeatedly adding (6B) and ACC (69), filter processing can be efficiently achieved.

Furthermore, the absolute value calculator (22) of the full-wave rectifier (1B) and the absolute value calculator (37) of the polarity discriminator (28) are AL]
This is realized by determining the most significant bit in step 68) and calculating the complement based on the result. In addition, the level determiner (32) and the AND gate (33) compare the output of the multiplier (67), which is the output result of the digital low-pass filter (31), with a predetermined value in the ALU I 681, and perform conditional branching based on the result. The JMP control signal is generated from the control circuit (59), and the jump destination program is configured to process the digital low-pass filter (34). The logarithmic converter (24) and the anti-logarithmic converter (29) store a logarithmic conversion table in the constant ROM (63) of one digital processing circuit, and store the logarithmic conversion table in the constant ROM (63) of the other digital processing circuit.
This is achieved by storing an anti-logarithm conversion table in (63) and accessing each other's constant ROM (63).

Alternatively, the constant conversion table and the anti-logarithm conversion table may be stored in a program ROM within the control circuit (60), and this ROM may be accessed.

By the way, the sampling frequency fB of the first and third blocks in FIG. 1 is 44.1 KH.

In order to operate in this way, every time digital data L1.4 and R of the left and right channels are input, the program for processing the first and third blocks must be executed until the next digital data is input. Complete it in time. on the other hand,
In order to operate the second block at 1/16 of the sampling frequency f3, the program that implements the second block is divided into 16 approximately equal parts, and each of them is divided into 16 parts at each sampling period. This is accomplished by doing this before or after executing the block program. that time,
The processing results must be saved in the data RAM (61) for use in the next sampling period.

In this way, when the DSP shown in FIG. 7 is used, the data processing circuits (52) and (53) can be controlled simultaneously with the same program, so the number of program steps can be shortened and the direction control shown in FIG. An audio signal processing device with emphasis can be realized very easily.

(G) Effects of the Invention As described above, according to the present invention, when configuring an audio signal processing device having direction control emphasis using a DSP, the AD
By dividing the blocks into blocks that operate at the sampling period of the converted audio signal and blocks that operate at a period N times the sampling period, high-precision calculations with a small number of bits for L low-frequency digital filter coefficients can be performed. I can do it.

Furthermore, by dividing the processing of a block that operates at N times the sampling period approximately equally into 1/N and distributing it over N sampling periods, the number of steps to be processed within L- sampling periods is reduced, resulting in increased throughput. improves.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram of the bandpass filter shown in FIG. 1, and FIG. 3 is a block diagram of the full-wave rectifier shown in FIG. 1. 4 is a block diagram of the level detector and digital low-pass filter shown in FIG. 1, FIG. 5 is a block diagram of the polarity discriminator shown in FIG. 1, and FIG. 6 is a block diagram of the polarity discriminator shown in FIG. 1. FIG. 7 is a block diagram of a DSP suitable for realizing the audio signal processing device shown in FIG. 1, and FIG. 8 is a block diagram showing a conventional example of the present invention. . (11) First block, (I2) Second block, (13) Third block, (14) Digital band pass filter, (15) Adder, (16)...
・Subtractor, (I7)... Bypass filter, (18
)... Full-wave rectifier, (24)... Logarithmic converter, (2
5)...Subtractor, (26)...Level detector, (2
7)... Digital low-pass filter, (28) - Polarity discriminator, (29)... Anti-logarithm converter, (30)...
Coefficient calculator, (43) (44)... Multiplier, (4
5) Adder, (46)...Digital bypass filter, (47)...Subtractor, (48)...Adder, (49)...Delay element, (50)...Digital low-pass filter.

Claims (4)

[Claims] (1) Directionality is achieved by detecting the level ratio of the left channel signal and right channel signal and the level ratio of the sum and difference of each channel signal, and amplifying or attenuating the level of each output channel based on the detection results. In an audio signal processing device that performs enhancement, left channel and right channel digital data input at every predetermined sampling period is input, and the processing of the digital data is performed using a block that completes each sampling period and a block corresponding to the sampling period. An audio signal processing device having directionality emphasis characterized in that the audio signal processing device is divided into blocks that are completed in N times the period. (2) Directionality is achieved by detecting the level ratio of the left channel signal and right channel signal and the level ratio of the sum and difference of each channel signal, and amplifying or attenuating the level of each output channel based on the detection results. In an audio signal processing device that performs emphasis, left channel and right channel digital data L and R are input at every predetermined sampling period.
Calculate L+R and LR from each digital data L,
A first block that calculates each rectified value of R, L+R, and LR, and each rectified value calculated in the first block is converted by a predetermined function, and L and L are calculated from the function conversion output. Difference in R and L+R
a second block that calculates the difference between a third block that calculates directionally emphasized multi-channel output data by multiplying the digital data L and R by the coefficients created in the second block; An audio signal processing device having directionality emphasis, characterized in that the block completes processing at each sampling period, and the second block completes processing at a period N times the sampling period. (3) dividing the processing of the second block into approximately 1/N;
2. The audio signal processing device with directionality emphasis according to claim 1, wherein the 1/N divided processing is performed during a sampling period in which the first and third blocks are processed. (4) Directional enhancement by detecting the level ratio of the left channel signal and right channel signal and the level ratio of the sum and difference of each channel signal, and attenuating the level of non-main output channels based on the detection results In an audio signal processing device that performs Addition/subtraction means for calculating, each digital data L, R, L+R, and
a first block comprising full-wave rectification means for calculating each absolute value of L-R; a logarithmic conversion means for logarithmically converting each absolute value calculated in the first block; and the logarithmic conversion. A level difference calculation means for calculating the difference between L and R and the difference between L+R and LR from the output, and each output of the level difference calculation means is integrated by a first digital low-pass filter to reach a predetermined level. a second digital low-pass filter whose time constant is switched and controlled according to the output of the level detection means and receives the output of the level difference calculation means; A polarity determining means for distributing outputs according to signs, an anti-logarithmic converting means for anti-logarithmically converting the output of the polarity discriminating means, and a coefficient creating means for creating a plurality of coefficients based on the output of the anti-logarithm converting means. and a second block, which multiplies the digital data L and R of the left channel and right channel input at each sampling period by the coefficient created in the second block, and outputs a plurality of channels with directionality emphasis. a third block that calculates data, the first and third blocks complete processing at each sampling period, and the second block performs processing at a period N times the sampling period. An audio signal processing device having directional enhancement characterized in that: