JPH0481030A - Frame synchronizing circuit - Google Patents

Abstract

PURPOSE:To shorten time for resynchronization by loading the value of a second frame counter to a first frame counter according to an out-of-synchronism signal and loading the value of the first frame counter to the second frame counter according to a synchronism establishing signal. CONSTITUTION:Even when non-coincidence is detected between a frame synchronizing pattern inputted in a synchronous state and a previously decided frame synchronizing pattern, a front protection counter 19 does not immediately judge an out-of-synchronism state but outputs the out-of-synchronism signal when a non-coincidence detection circuit exceeds the number of steps for protection. Even when coincidence between the both patterns is detected, a rear protection counter 21 does not immediately judge the synchronous state but outputs the synchronism establishing signal when a coincidence detection circuit exceeds the number of steps for protection. Accoridng to the out-of-synchronism signal from the front protection counter 19, the value of a second frame counter 33 is loaded to a first frame counter 4 and according to the synchronism establishing signal from the rear protection counter 21, the value of the first frame counter 4 is loaded to the second frame counter 33. Thus, time for resynchronization is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frame synchronization circuit for synchronizing frames by detecting frame synchronization patterns inserted at regular intervals in a serial input signal.

[Conventional technology]

Figure 4 shows a circuit diagram of a conventional 1-bit instant shift frame synchronization circuit based on the configuration shown in "Digital Communication Technology" by Kimio Tanaka, Tokai University Press.
FIG. 5 is a timing chart thereof. In the figure,
1 is input data input from an external processing device, etc.; 3
4 is a frame counter that counts frames and multi-frames; 5 is a frame signal that is output from the frame counter 4 and becomes active for each frame; 7 is input data 1 is a reference input clock signal, and 9 is a 1 counter clock signal controlled by a gate signal 29. 11 is a frame pattern detection signal that becomes active when the frame pattern detection unit 3 detects a frame synchronization pattern; 13 is a multi-frame signal that is output from the frame counter 4 and becomes active for each multi-frame; 15 is a multi-frame signal 13
becomes active and frame pattern detection signal 1
A match signal that becomes active when the phase matches with 1,
Reference numeral 17 denotes a mismatch signal that becomes active when the phases of the multi-frame signal 13 and the frame pattern detection signal 11 do not match. 19 is a forward protection counter that counts only the number of protection steps without setting the out-of-synchronization alarm signal 27 in response to one mismatch signal 17;
21 is synchronized with one coincidence signal 15; Yozur, rear protection counter that counts the number of protection stages without resetting the alarm signal 27, 23 is a mismatch signal 17 for the number of protection stages.
This is an alarm cent signal output from the forward protection counter 19 when the forward protection counter 19 is output. 25 is an alarm reset signal that is output from the rear protection counter 21 when the match signal 15 is output for the number of protection stages, and 27 is a synchronization signal that is activated by the alarm set signal 23 and deactivated by the alarm reset signal 25. A slip alarm signal 29 is an input port when the synchronization alarm signal 27 is active, that is, when the synchronization is lost and the mismatch signal 17 is active.

This is a gate signal that gates the signal 7.

Next, the operation will be explained. When no input data 1 is input, the frame counter 4 is in a free-running state, and the mismatch signal 17 is output for each multi-frame signal 13, the rear protection counter 21 continues to be reset, and the front protection counter 9 continues to count. The alarm signal 23 is output, and the out-of-synchronization alarm signal 27 becomes active, indicating an out-of-synchronization state. In this state, the gate signal 29 is output for each multi-frame, and the frame counter 4 changes its own phase by 1 for each multi-frame.
It is in a hunting state by shifting bits at a time.

If input data 1 containing a normal synchronization bit pattern continues to be input from this state, a hunting state will occur.
The phase of the frame counter 4 becomes equal to the phase of the input data 1. In this state, the phases of the frame pattern detection signal 11 and the multi-frame signal 13 are equal, and the mismatch signal 17 is not output, but the match signal 15 is output.

When the match signal 15 is output, the forward protection counter 19 is reset and the backward protection counter 21 is counted and amplified. Also, since the mismatch signal 17 is not output, the gate signal 2
9 is not activated, the frame counter 4 maintains the same phase. If the phase of the frame counter 4 remains unchanged and the frame synchronization pattern in the input data is normal, a coincidence signal 15 is output for each multi-frame. When the coincidence signal 11 is output for the number of protective films, the front protection counter 19 continues to be reset and the alarm reset signal 25 is output from the rear protection counter 21, and the out-of-synchronization alarm signal 27 becomes inactive and a synchronized state is established. . This state is always maintained if it is in a synchronized state and the frame synchronization pattern in input data 1 is normal. The above operation is shown in the section ``■'' in FIG.

Next, the process of losing synchronization will be explained. If input data 1 stops coming from a certain point or an abnormality occurs in the synchronization bit pattern in input data 1, when the next multi-frame signal 13 becomes active, the coincidence signal 15 will not be output and a mismatch signal 17 will be output. be done. frame counter 4
Since the out-of-synchronization alarm signal 27 is inactive, the gate signal 29 is not output. That is, this phase is maintained. If this state continues for several minutes with the protective film, a mismatch signal 17
is continuously output for each multi-frame and continues to reset the rear protection counter 21, the forward protection counter 19 counts up, outputs the alarm cent signal 23, and activates the out-of-synchronization alarm signal 27, resulting in an out-of-synchronization state. The timing of the above operation is shown in (■) in FIG. In the conventional frame synchronization circuit, hunting operation is first started at this point. For reference, FIG. 6 shows a timing chart at the time of a short-term failure in the two frame synchronization circuits shown in FIG. 4.

[Problem to be solved by the invention]

Conventional frame synchronization circuits are configured to hunt only when they are out of synchronization, so if the frame phase is out of sync due to a slip, etc., and it immediately returns to normal, it is necessary to wait a few minutes for the front protective film. The problem was that only crows could hunt.

This invention was made to solve the above-mentioned problems, and aims to provide a frame synchronization circuit that enables hunting while performing forward protection operations and shortens resynchronization time. .

[Means for Solving the Problems: The frame synchronization circuit according to the present invention includes a first frame counter 4 that performs hunting, which is an operation of transitioning from a frame out-of-frame state to a frame-synchronized state, only when the frame is out of synchronization; A second frame counter 33 starts hunting if the frame phase in the input data shifts even momentarily regardless of the timing, and detects a mismatch between the input frame synchronization pattern and a predetermined frame synchronization pattern when in the synchronized state. The forward protection counter 19 outputs a synchronization loss signal indicating an out-of-synchronization state when the number of mismatch detections exceeds the number of protection steps without immediately determining that the synchronization is out of synchronization. and a backward protection counter 21 that outputs a synchronization establishment signal indicating a synchronization state when the number of coincidence detections exceeds the number of protection stages without immediately determining a synchronization state, and the forward protection counter 1
The value of the second frame counter 33 is loaded into the first frame counter 4 by the out-of-synchronization signal from 9, and the value of the first frame counter 4 is loaded by the same Y, B establishment signal from the backward protection counter 21. The second frame counter 33 is configured to read the above-mentioned second frame counter 33.

[Effect]

The first frame counter 4 hunts only when frame synchronization is lost. The second frame counter 33 starts hunting when the frame phase in the input data shifts even momentarily, regardless of the synchronization state. Forward protection counter 19
Even if it detects a mismatch between the input frame synchronization pattern and a predetermined frame synchronization pattern when it is in a synchronized state, it does not immediately judge the state to be out of synchronization, but loses synchronization when the number of mismatch detections exceeds the number of protection stages. Outputs an out-of-synchronization signal indicating the status. Even if the backward protection counter 21 detects a match between the two, it does not immediately determine that it is in a synchronized state, but outputs a synchronization establishment signal indicating a synchronized state when the number of times of match detection exceeds the number of protection stages. The value of the second frame counter 33 is loaded into the first frame counter 4 by the out-of-synchronization signal from the forward protection counter 19. The value of the first frame counter 4 is loaded into the second frame counter 33 by the synchronization establishment signal from the backward protection counter 21.

〔Example〕

FIG. 1 is a circuit diagram of a frame synchronization circuit according to an embodiment of the present invention, and FIG. 2 is a timing chart thereof. In the figure, 1 is input data (input signal) input from an external processing device, etc., and 3 is a frame slam detection unit that detects a synchronization bit pattern. 4 is a first frame counter that counts frames (and multiframes) only when frame synchronization is lost. That is, the first frame counter 4 performs hunting, which is a transition operation from the frame out-of-frame state to the frame-synchronized state, only when the frame is out of synchronization. 5 is a frame signal (frame position pulse) that is output from the first frame counter 4 and becomes active for each frame; 7 is an input cross signal that serves as a reference for the input data l; 9 is a counter clock signal controlled by the gate signal 29 , 11 is a frame pattern detection signal that becomes active when the frame pattern detection section 3 detects a frame synchronization pattern. 13 is a multi-frame signal that is output from the frame counter 4 and becomes active for each multi-frame; 15 is a coincidence signal that becomes active when the phase of the multi-frame signal 13 becomes active and the frame pattern detection signal 11 match; 17 indicates when the multi-frame signal 13 becomes active and the frame pattern detection signal 11
This is a mismatch signal that becomes active when the phase does not match with the Reference numeral 19 denotes a forward protection counter that does not set the out-of-synchronization alarm signal 27 in response to one mismatch signal 17 and counts by the number of protection stages. In other words, even if the forward protection counter 19 detects a mismatch between the input frame synchronization pattern and a predetermined frame synchronization pattern while in the synchronized state, it does not immediately determine that the synchronization is out of synchronization, but only if the number of mismatch detections exceeds the protection limit. When the number of stages is exceeded, an out-of-synchronization signal indicating an out-of-synchronization state is output. Reference numeral 21 denotes a backward protection counter that does not reset the out-of-synchronization alarm signal 27 by one coincidence signal 15, but counts by the number of protection stages. That is, the backward protection counter 21 immediately detects the coincidence between the two; it does not determine that it is in a synchronous state, and when the number of coincidence detections exceeds the number of protection stages, it issues the same M establishment signal indicating a synchronous state. Output. Reference numeral 23 indicates an alarm cent signal (out-of-synchronization signal) outputted from the forward protection counter 21 when the number of mismatch signals 17 equal to the number of protection stages is output, and reference numeral 25 indicates a match signal 15 outputted equal to the number of protection stages.

When the rear protection counter 21 outputs an alarm center signal (same 'U establishment signal), 27 is activated by the alarm signal 23 and an alarm center signal 25 is output.
Out-of-synchronization alarm signal becomes inactive due to
Reference numeral 29 is a gel signal that gates the poem input clock signal 7 when the out-of-synchronization alarm signal 27 is active, that is, when the out-of-synchronization occurs and the mismatch signal 17 is active. 31 and 32 are plus-one circuits that add "1" to the values of the two frame counters 4 and 33 when the values of the two frame counters 4 and 33 are rotated to the other, respectively. This is a second frame counter that starts hunting when the frame phase shifts.

35 is a counter clock signal controlled by a mismatch signal 37; 37 is a mismatch signal indicating a mismatch between the phase of the second frame counter 33 and the phase of the frame pattern detection signal 11 detected from the input data 1; and 39 is a second mismatch signal. This is a multi-frame signal output from the frame counter 33 every multi-frame period.

Next, the operation of this embodiment will be explained with reference to FIGS. 1 and 2. When no input data 1 is input, the first frame counter 4 is in a free running state,
The mismatch signal 17 is output every multi-frame signal 13, the rear protection counter 21 continues to be reset, the front protection counter 19 counts up, and the alarm center signal 2 is output.
3 is output, and the out-of-synchronization alarm signal 27 becomes active, indicating an out-of-synchronization state. In this state, the gate signal 29 is output for each multi-frame, the first frame counter 4 shifts its phase by 1 bit for each multi-frame, and the second frame counter 33, which is in a hunting state, becomes in an alarm state. At this time, the own counter value is incremented by 1 in the plus 1 circuit 32 and loaded into the first frame counter 4, so at this time, the first frame counter 4 and the second frame counter 33 operate in exactly the same phase. are doing.

If input data 1 containing a normal synchronization bit pattern continues to be input from this state, the phase of the first frame counter 4, which is in the hunting state, will change to the input data l.
is equal to the phase of In this state, the phases of the frame pattern detection signal 11 and the multi-frame signal 13 are equal, and the mismatch signal 17 is not output, but the match signal I5 is output. Further, the multi-frame signal 39 is also in the same phase as the multi-frame signal 13, and the phases of the frame pattern detection signal 11 and the multi-frame signal 39 are also equal, so that the mismatch signal 37 is not output.

- When the match signal 15 is output, the forward protection counter 19 is reset and the backward protection counter 2I is counted up. Furthermore, since the mismatch signal 17 is not output, the gate signal 29 does not become active and the first frame counter 4 maintains its phase. Furthermore, since the mismatch signal 39 is not output, the second frame counter 33 also maintains the same phase. If the phase of the first frame counter 4 remains unchanged and the frame synchronization bump in the input data 1 is normal, a coincidence signal 15 is output for each multi-frame. When the coincidence signal 11 is output for the number of protection stages, the front protection counter 19 continues to be reset, the rear protection counter 21 outputs an alarm reset signal 25, and the out-of-synchronization alarm signal 27 becomes non-active, resulting in a synchronized state.

This state is always maintained if it is in a synchronized state and the frame synchronization pattern in input data 1 is normal.

The above operation is shown in the section ``■'' in FIG.

Next, the process of losing synchronization will be explained. If input data 1 stops coming from a certain point or an abnormality occurs in the synchronization bit pattern in input data 1, when the next multi-frame signal 13 becomes active, the coincidence signal 15 is not output and the mismatch signal 17 is output. Ru. The first frame counter 4 loses synchronization and the keto signal 29 is not outputted because the alarm signal 27 is inactive. In other words, this phase is maintained. Since the second frame counter 33 starts hunting regardless of the synchronization state, it has already started hunting in this state.

However, since input data 1 remains abnormal, no special operation is performed. If this state continues for several minutes of the protective film, the mismatch signal I7 is output continuously for each multi-frame, and the rear protection counter 21
continues to be reset, the forward protection counter 19 counts up, outputs the alarm set signal 23, and activates the out-of-synchronization alarm signal 27, resulting in an out-of-synchronization state.

At this time, the positive value of the second frame counter 33 is incremented by one in the plus-one circuit 32 and loaded into the first frame counter 4, so that the phases of the two counters 4 and 33 become equal. The timing of these operations is shown in the section ``■'' in FIG. As can be seen by comparing FIG. 5 and FIG. 2, in the above-mentioned state, the operation is similar to that of the conventional example. However, as shown in Fig. 3, when the input data l instantaneously shifts from the multi-frame phase to another phase like a slip, and operates as normal data at that phase, the frame counter 4 of the cylinder 1 performs a forward protection operation. Therefore, the phase of its own counter is not changed. However, since the second frame counter 33 is configured to hunt regardless of the synchronization state, the first frame counter 4 is already hunting during the forward protection operation and is approaching the correct multi-frame phase state. . If this state continues, the forward protection counter 19 continues to count up and the alarm set signal 23 is output. This alarm set signal 23 activates the out-of-synchronization alarm signal 27, resulting in a synchronization alarm state. At the same time, the value of the second frame counter 33 is incremented by 1 by the plus 1 circuit 32, and the value of the second frame counter 33 is incremented by 1 by the plus 1 circuit 32.
is loaded into the frame counter 4 of . This means that the first frame counter 4 receives information that hunting has already been performed during the forward protection operation. Since the synchronization is out of synchronization at this time, the first frame counter 4 continues hunting and establishes synchronization.

Although the above embodiment has been described using a frame synchronization circuit using a 1-bit immediate shift method, similar effects can be obtained using other frame synchronization methods such as a parallel detection method and a frame division inspection method. Furthermore, the synchronization of the two frame counters can also be performed by resetting them. It is conceivable that the plus 1 circuit may have a value of 0 or 1 or more depending on the loading method.

The above embodiments can be implemented without requiring large-scale hardware.

〔Effect of the invention〕

As described above, according to the present invention, the value of the second frame counter is inverted to the first frame counter by the synchronization loss signal from the forward protection counter, and the value of the second frame counter is inverted to the first frame counter by the synchronization establishment signal from the backward protection counter. Since the configuration is configured such that the value of is loaded into the second frame counter, hunting can be performed while performing forward protection operation using the forward protection counter.This reduces resynchronization time and creates a frame synchronization circuit with good operating characteristics. This has the effect of being able to provide the following.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a frame synchronization circuit according to an embodiment of the present invention, FIG. 2 is a timing chart showing the operation of the circuit in FIG. 1, and FIG. 4 is a circuit diagram of a conventional frame synchronization circuit. 5 is a timing chart illustrating the operation of the circuit in 4. FIG. 6 is a timing chart showing the operation of the circuit in 4. It is a timing chart showing the operation. 4... First frame counter, 19... Front protection counter, 21... Back protection counter, 33... Second frame counter. Agent Patent Attorney Jun Miyazono

Claims (1)

[Claims] In a frame synchronization circuit that detects frame synchronization patterns distributed at specific positions within a frame of input data and synchronizes frames, there is a transition operation from an out-of-frame state to a frame-synchronized state only when the frame is out of synchronization. A frame counter that performs certain hunting, a second frame counter that starts hunting if the frame phase in input data shifts even momentarily regardless of the synchronization state, and a predetermined frame synchronization pattern that is input when in the synchronization state. When a mismatch with the frame synchronization pattern is detected, a forward protection counter outputs an out-of-sync signal indicating an out-of-sync state when the number of mismatch detections exceeds the number of protection stages, and when a match between the above two is detected, a match is detected. and a backward protection counter that outputs a synchronization establishment signal indicating a synchronization state when the number of frames exceeds the number of protection stages, and the value of the second frame counter is changed to the first frame counter by the out-of-synchronization signal from the forward protection counter. A frame synchronization circuit characterized in that it is configured to load the value of the first frame counter into the second frame counter in response to a synchronization establishment signal from the backward protection counter.