JPH0481865B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and particularly to a semiconductor device having a substrate potential generation circuit lower than a ground potential.

(Prior Art) Conventionally, for example, in an integrated circuit device using an N-channel MOS transistor, in order to form a desired circuit on a semiconductor substrate and obtain desired characteristics, the potential of the semiconductor substrate is not set to the ground potential, but is grounded. It is often set to a lower potential than the potential. Setting the substrate potential to a lower potential than the ground potential has various advantages such as increasing the threshold voltage of the MOS transistor formed on this semiconductor substrate.
Moreover, the substrate potential is not applied externally, but is performed using a circuit formed on the semiconductor substrate.

FIG. 3 is a circuit diagram of a conventional substrate potential generation circuit.

By differentiating the waveform generated by the oscillation circuit 5 with respect to the capacitance 1, the opposite node A has a potential lower than the ground potential. This potential is supplied to the substrate through a MOS transistor 2 that functions as a diode.

(Problem to be solved by the invention) The above-mentioned problem is solved by forming an N-type impurity diffusion layer on a P-type semiconductor substrate.
If an N-channel MOS transistor is used in which the source and drain regions of the MOS transistor are formed, current also flows through the PN diode 4 formed by the P-type substrate and the N-type drain region.

However, especially when a P-type substrate with high resistance is used, the electrons given from this PN diode do not immediately reach the metal electrode on the back of the substrate, and some of them diffuse into the semiconductor substrate. It spreads and is absorbed into a nearby N-type impurity diffusion layer. This electron effect is observed as substrate leakage current,
Other circuits near the substrate potential generation circuit may malfunction due to the loss of the held charge. In particular, in random access memory devices, each memory
The cell holds a minute signal and is easily affected by leakage current due to electrons from the substrate potential generation circuit.

An object of the present invention is to provide a semiconductor device that prevents leakage current from a substrate potential generation circuit formed on the semiconductor device and does not cause malfunctions.

(Means for Solving the Problems) The configuration of the present invention includes an oscillation circuit, a capacitive element connected to one end of the output of the oscillation circuit, and first and second MOS transistors whose gates and sources are commonly connected. are connected in cascade, the source of the first MOS transistor is connected to the ground potential, and the source of the first MOS transistor is connected to the ground potential.
A substrate potential generation circuit including a circuit in which the drain of the transistor is connected to the substrate potential, and the other end of the capacitive element is connected to the connection point of the first and second MOS transistors is provided in the P-type semiconductor substrate, In the semiconductor device in which the substrate potential generation circuit outputs a potential lower than the ground potential, the P
An N-type well is provided in the type semiconductor substrate, and a P-type impurity diffusion layer is provided in the N-type well to serve as the source and drain of the first and second MOS transistors, and the drain of the second MOS transistor and the It is characterized in that it is connected to a P-type semiconductor substrate by wiring.

(Example) Next, an example of the present invention will be described using the drawings.

FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is a circuit diagram of a substrate potential generation circuit using the embodiment shown in FIG.

An N-type well 12 is formed in a P-type silicon substrate 11 having a specific resistance of 10 Ω-cm. Polycrystalline silicon is deposited through the insulating film 16a and patterned to have a capacitance of 1.
One electrode 14a and the gate electrode 14b of the MOS transistor are formed. P-type source/drain regions 13a and 13b are formed by ion-implanting boron or the like using the gate electrode 14b as a mask. Thereafter, it is covered with an insulating film 16b, a contact hole is made, and an Al wiring 15 is formed.

In this semiconductor device, the source/drain region 13a surrounded by the capacitor electrode 14a and the gate electrode 14b corresponds to the node A shown in FIGS. 2 and 3. In other words, it becomes an impurity diffusion layer with a potential lower than the ground potential.

The source/drain region 13a is an N-type well 12
Since it is surrounded by Therefore, no leakage current occurs. This low potential is rectified through a diode and connected to the substrate 11 through Al wirings 15, 15'. MOS transistor 22,
23 is a P-type channel enhancement type.

Note that a depletion type P-type channel transistor may be used for the capacitor 1.

(Effects of the Invention) As explained above, according to the present invention, it is possible to completely eliminate the leakage current generated from the substrate potential generation circuit, so that a semiconductor device with less malfunction and improved reliability can be achieved. can get.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of an embodiment of the present invention, FIG. 2 is a circuit diagram of a substrate potential generation circuit using the embodiment shown in FIG. 1, and FIG. 3 is a circuit diagram of a conventional substrate potential generation circuit. be. 1... Capacity, 2, 3... MOS transistor,
4...Diode, 5...Oscillation circuit, 11...P
type silicon substrate, 12...N type well, 13a,
13b...P-type source/drain region, 14a...
...Capacitor electrode, 14b...Gate electrode, 15,1
5'...Al electric wire, 16a, 16b...Insulating film, 2
2, 23...P channel enhancement type
MOS transistor, Vcc...power supply potential, Vsub...
...Substrate potential.

Claims (1)

[Claims] 1. An oscillation circuit, a capacitive element connected to one end of the output of this oscillation circuit, and first and second MOS transistors whose gates and sources are commonly connected are connected in cascade, and the source of the first MOS transistor is connected to a ground potential. and a circuit in which the drain of the second MOS transistor is connected to a substrate potential, and the other end of the capacitive element is connected to a connection point between the first and second MOS transistors. In a semiconductor device provided in a P-type semiconductor substrate, in which the substrate potential generation circuit outputs a potential lower than the ground potential, an N-type well is provided in the P-type semiconductor substrate, and in the N-type well. P-type impurity diffusion layers are provided to serve as sources and drains of the first and second MOS transistors, and
A semiconductor device characterized in that the drain of the MOS transistor and the P-type semiconductor substrate are connected by wiring.