JPH0482065B2 - - Google Patents
Info
- Publication number
- JPH0482065B2 JPH0482065B2 JP60121004A JP12100485A JPH0482065B2 JP H0482065 B2 JPH0482065 B2 JP H0482065B2 JP 60121004 A JP60121004 A JP 60121004A JP 12100485 A JP12100485 A JP 12100485A JP H0482065 B2 JPH0482065 B2 JP H0482065B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- region
- gate electrode
- source
- fixed potential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は高周波に対応する低入力容量のMOS
電界効果トランジスタ（以下、MOSFETとい
う）に関するものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention is a MOS with low input capacitance that supports high frequencies.
This relates to field effect transistors (hereinafter referred to as MOSFETs).
従来、低入力容量を実現させるために、
MOSFETの１セルは第２図に示すように裏面に
ドレイン電極９を有するN+半導体基板８上に形
成したN-半導体層１１にＰ型ベース層６とN+型
ソース領域５を設け、Ｐ型ベース層６上のゲート
電極２とN-半導体層１１上の電極３とを形成し、
酸化膜を介して全表面にソース電極１を設けてい
た。
Conventionally, in order to achieve low input capacitance,
As shown in FIG. 2, one MOSFET cell includes a P type base layer 6 and an N + type source region 5 provided on an N - semiconductor layer 11 formed on an N + semiconductor substrate 8 having a drain electrode 9 on the back surface. forming a gate electrode 2 on the mold base layer 6 and an electrode 3 on the N − semiconductor layer 11;
A source electrode 1 was provided on the entire surface with an oxide film interposed therebetween.
１つのセル内におけるゲート電極２の長さはた
かだか数μm程度であり、上述したMOSFETのゲ
ート電拠２および電極３は、１つの金属層にスリ
ツトを設けて３分割して形成しているが、このス
リツトを形成するには超微細加工技術を用いなけ
ればできないという欠点がある。
The length of the gate electrode 2 in one cell is approximately several μm at most, and the gate voltage base 2 and electrode 3 of the MOSFET described above are formed by providing a slit in one metal layer and dividing it into three parts. However, there is a drawback that this slit cannot be formed without using ultra-fine processing technology.
また、ソース・ドレイン間に高電圧を印加した
場合、等電位面が、第２図の破線１１のようにな
り、ゲート・ソース間に高電圧がかかる。この高
電圧のためゲート・ソース間に悪影響を及ぼし信
頼性が低下するという欠点もある。 Further, when a high voltage is applied between the source and the drain, the equipotential surface becomes like the broken line 11 in FIG. 2, and a high voltage is applied between the gate and the source. This high voltage also has the disadvantage of adversely affecting the gate-source gap and reducing reliability.
本発明のMOSFETは、一導電型の半導体領域
と、該半導体領域内に少くとも対向する部分を有
するように形成された他の導電型のベース領域
と、該ベース領域内に形成された一導電型のソー
ス領域と、前記ベース領域表面上に酸化膜にて絶
縁して形成したゲート電極と、該ゲート電極に一
部重畳して前記半導体領域上に酸化膜を介して形
成された固定電位電極と、前記ベース領域とソー
ス領域の一部に接続し、前記ゲート電極および前
記固定電位電極上に延在するように絶縁膜を介し
て設けたソース電極とを有し、前記半導体領域と
前記ソース電極との間には前記ゲート電極か前記
固定電位電極の少なくとも一方を介在したことを
特徴とするMOS電界効果トランジスタを得る。
The MOSFET of the present invention includes a semiconductor region of one conductivity type, a base region of another conductivity type formed in the semiconductor region so as to have at least opposing portions, and a base region of one conductivity type formed in the base region. a gate electrode formed on the surface of the base region insulated with an oxide film, and a fixed potential electrode partially overlapped with the gate electrode and formed on the semiconductor region via the oxide film. and a source electrode connected to the base region and a part of the source region and provided through an insulating film so as to extend over the gate electrode and the fixed potential electrode, and the source electrode is connected to the base region and a part of the source region, and is provided through an insulating film so as to extend over the gate electrode and the fixed potential electrode. A MOS field effect transistor is obtained, characterized in that at least one of the gate electrode and the fixed potential electrode is interposed between the gate electrode and the fixed potential electrode.
次に図面を参照して本発明により詳細に説明す
る。
Next, the present invention will be explained in detail with reference to the drawings.
第１図は本発明の一実施例であつて、１はソー
ス電極、２はゲート電極、３はゲート電極とは絶
縁された固定電位電極、４は酸化膜、５はN+ソ
ース領域、６はＰ型ベース領域、７はN-半導体
層、８はN+半導体基板、９はドレイン電極であ
る。特にゲート電極２と固定電位電極３とは一部
重なつており、N-半導体層７とソース電極１と
の間はゲート電極２か固定電位電極３かのいづれ
かが介在しているようになつている。かかる構造
はゲート電極２を形成後、酸化膜４をかぶせ、そ
の後固定電位電極３を形成することにより容易に
実現することができる。従つて超微細加工技術を
用いずに簡単に実現することができる。また、ソ
ース・ドレイン間に高電圧を印加した場合でも等
電位面は第１図の破線１０のようになり、ゲー
ト・ソース間に高電位が加わることがなく悪影響
を及ぼすことがない。 FIG. 1 shows an embodiment of the present invention, in which 1 is a source electrode, 2 is a gate electrode, 3 is a fixed potential electrode insulated from the gate electrode, 4 is an oxide film, 5 is an N + source region, and 6 is a fixed potential electrode insulated from the gate electrode. is a P-type base region, 7 is an N − semiconductor layer, 8 is an N + semiconductor substrate, and 9 is a drain electrode. In particular, the gate electrode 2 and the fixed potential electrode 3 partially overlap, and either the gate electrode 2 or the fixed potential electrode 3 is interposed between the N - semiconductor layer 7 and the source electrode 1. ing. Such a structure can be easily realized by forming the gate electrode 2, covering it with the oxide film 4, and then forming the fixed potential electrode 3. Therefore, it can be easily realized without using ultra-fine processing technology. Further, even when a high voltage is applied between the source and the drain, the equipotential surface becomes as indicated by the broken line 10 in FIG. 1, and no high potential is applied between the gate and the source, causing no adverse effects.
以上説明したように本発明は、ゲート電極の面
積を小さくすることにより、低入力容量の
MOSFETを超微細加工技術を用いず実現するこ
とができる効果がある。
As explained above, the present invention achieves low input capacitance by reducing the area of the gate electrode.
This has the advantage that MOSFETs can be realized without using ultra-fine processing technology.
第１図は本発明の一実施例による低入力容量
MOSFETの断面図である。第２図は従来の低入
力容量MOSFETの断面図である。
１……ソース電極、２……ゲート電極、３……
固定電位電極、４……酸化膜、５……N+ソース
領域、６……Ｐベース層、７……N-半導体層、
８……N+半導体基板層、９……ドレイン電極、
１０，１１……ソース・ドレイン間に高電圧を印
加した場合の等電位面。
Figure 1 shows a low input capacitance according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view of a MOSFET. FIG. 2 is a cross-sectional view of a conventional low input capacitance MOSFET. 1... Source electrode, 2... Gate electrode, 3...
Fixed potential electrode, 4... Oxide film, 5... N + source region, 6... P base layer, 7... N - semiconductor layer,
8...N + semiconductor substrate layer, 9... drain electrode,
10, 11...Equipotential surface when high voltage is applied between source and drain.
Claims (1)
少くとも対向する部分を有するように形成された
他の導電型のベース領域と、該ベース領域内に形
成された一導電型のソース領域と、前記ベース領
域表面上に酸化膜にて絶縁して形成したゲート電
極と、該ゲート電極に一部重畳して前記半導体領
域上に酸化膜を介して形成された固定電位電極
と、前記ベース領域とソース領域の一部に接続
し、前記ゲート電極および前記固定電位電極上に
延在するように絶縁膜を介して設けたソース電極
とを有し、前記半導体領域と前記ソース電極との
間には前記ゲート電極が前記固定電位電極の少な
くとも一方を介在したことを特徴とするMOS電
界効果トランジスタ。1. A semiconductor region of one conductivity type, a base region of another conductivity type formed to have at least opposing portions within the semiconductor region, and a source region of one conductivity type formed within the base region. , a gate electrode insulated and formed on the surface of the base region with an oxide film, a fixed potential electrode partially overlapped with the gate electrode and formed on the semiconductor region via the oxide film, and the base region. and a source electrode connected to a part of the source region and provided via an insulating film so as to extend over the gate electrode and the fixed potential electrode, and between the semiconductor region and the source electrode. 2. A MOS field effect transistor, wherein the gate electrode interposes at least one of the fixed potential electrodes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60121004A JPS61279176A (en) | 1985-06-04 | 1985-06-04 | Mos field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60121004A JPS61279176A (en) | 1985-06-04 | 1985-06-04 | Mos field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61279176A JPS61279176A (en) | 1986-12-09 |
| JPH0482065B2 true JPH0482065B2 (en) | 1992-12-25 |
Family
ID=14800399
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60121004A Granted JPS61279176A (en) | 1985-06-04 | 1985-06-04 | Mos field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61279176A (en) |
-
1985
- 1985-06-04 JP JP60121004A patent/JPS61279176A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61279176A (en) | 1986-12-09 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |