JPH0482229A - semiconductor equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a structure of a vertical bipolar transistor having a so-called walled emitter structure, in which at least a portion of an emitter region is in contact with an element isolation film. .

[Prior Art] A cross-sectional view of the structure of a conventional walled-emitter vertical NPN bipolar transistor is shown in FIG.

The vertical NPN bipolar transistor is formed on the surface of an N-type well 2 formed in a P-type silicon substrate 1.
Base region 3 made of P-type impurity; Emitter region 4 made of N-type impurity formed on the substrate surface within the base. It is constituted by an electrode lead-out portion 5 of the collector. The bipolar transistor has a so-called walled emitter structure in which the emitter region 4 is in contact with the element isolation film 6 for miniaturization.

At the end of the element isolation film, in order to prevent the lightly doped base region and emitter region from overlapping due to lateral diffusion, which would lower the punch-through breakdown voltage between the emitter and collector, the An impurity diffusion layer 8 formed at the same time as the channel stopper region 7 is formed in the emitter region 4 of the bipolar transistor.
It is arranged under the element isolation film 6 which is in contact with the element isolation film 6.

[Problems to be Solved by the Invention] However, the conventional walled emitter structure vertical NPN bipolar transistor as described above has the following disadvantages.

The channel stopper region is a highly concentrated impurity diffusion layer in order to prevent the formation of parasitic transistors. A high concentration is effective for improving the punch-through voltage between the emitter and collector, but it also reduces the reverse breakdown voltage of the emitter-base junction and the reverse breakdown voltage of the base-collector junction. It is disadvantageous in this respect. Further, the impurity diffuses in the lateral direction and increases the base concentration directly under the emitter, which lowers the current amplification factor of the bipolar transistor.

SUMMARY OF THE INVENTION The present invention aims to solve these problems, and its purpose is to form a vertical bipolar transistor on one surface of a semiconductor substrate, and to form an emitter region of the vertical bipolar transistor. In a semiconductor device in which at least a portion of the device is in contact with an element isolation film, the punch-through voltage between the emitter and the collector does not decrease, and the reverse breakdown voltage of the emitter and base junctions and the reverse breakdown voltage of the base and collector junctions do not decrease. It is an object of the present invention to provide a semiconductor device in which the withstand voltage does not decrease and the current amplification factor of a bipolar transistor does not decrease.

[Means for Solving the Problems] In the semiconductor device of the present invention, a vertical bipolar transistor is formed on one surface of a semiconductor substrate.

In the semiconductor device in which at least a portion of the emitter region of the vertical bipolar transistor is in contact with an element isolation film, an impurity layer of the same conductivity type as the base region is provided in a lower part of the front rudder element isolation film that is in contact with the emitter region. The impurity layer has a higher concentration than the base region and a lower concentration than the channel stopper region.

[Example] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a structural cross-sectional view of a vertical NPN bipolar transistor with walled emitter structure according to the present invention.

The vertical NPN bipolar transistor is formed on the surface of an N-type well 2 formed in a P-type silicon substrate 1.
Base region 3 made of P-type impurity; Emitter region 4 made of N-type impurity formed on the substrate surface within the base. It is constituted by an electrode lead-out portion 5 of the collector. A P-type impurity layer 9 having an impurity temperature higher than that of the base region 3 and lower than that of the channel stopper 7 is provided below the element isolation film 6 in contact with the emitter region 4 .

Next, a second embodiment of the method for manufacturing a semiconductor device of the present invention will be described.
This will be explained based on FIGS. (a) to (d).

First, as shown in FIG. 2(a), phosphorus ions are injected into the P-type silicon substrate 1 in the region where the NPN bipolar transistor is to be formed at a rate of 1×10 12 /cI with an energy of 120 KeV.
An N-type well 2 is formed by implanting 112 ions.

Next, a silicon nitride film 10 is formed on the entire surface of the substrate, and the portion where the element portion M% is to be formed is removed by etching using a resist pattern. Then, using the photoresist 11 and the silicon nitride film 10 as a mask, boron ions are irradiated into the element isolation region with an energy of 35 KeV.
x 10" 7cm2 to form a P-type impurity layer 7 which is a channel stopper. This state is shown in Fig. 2 (b).
).

Similarly, using the photoresist 11 and the silicon nitride film 10 as a mask, boron ions are irradiated with 1 x 10'' at an energy of 35 KeV in the region where the emitter of the bipolar transistor to be formed later contacts the device isolation film.
/am2 implantation to form a P-type impurity layer 9 for increasing the punch-through breakdown voltage between the emitter and collector of the bipolar transistor. This state is shown in FIG. 2(C).

Next, as shown in FIG. 2(d), an element isolation film 6 of about 1 .mu.m thick is formed by thermal oxidation in the area excluding the silicon nitride film 10, and then the silicon nitride film is removed.

Next, as shown in FIG. 2(e), the base region 3 and emitter region 4 of the NPN bipolar transistor are formed. Base region 3 contains boron ions at 30KeV 8×1
The emitter 4 is formed by implanting arsenic ions at 1×10 16 /cm 2 at 80 KeV.The depth of the formed base is about 0.3 μm, and the depth of the emitter is about 0.15 μm.

After that, through the normal transistor formation process,
By forming a vertical NPN bipolar transistor, the structure of the embodiment of the present invention shown in FIG. 1 can be obtained.

Although this embodiment has been described with reference to the case where the bipolar transistor is an NPN bipolar transistor, it can also be applied to a PNP bipolar transistor by replacing the impurity types.

[Effects of the Invention] As described above, according to the present invention, in a bipolar transistor with a so-called walled emitter structure, an impurity layer having a higher concentration than the base region is formed in the lower part of the element isolation film in contact with the emitter region. By arranging it, the bunch-through breakdown voltage between the emitter and collector does not decrease,
Because the impurity layer has a lower concentration than the channel stopper region, the reverse breakdown voltage of the emitter and base junctions and the reverse breakdown voltage of the base and collector junctions do not decrease, and the current amplification factor of the bipolar transistor This has the great effect of not reducing the

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the structure of a semiconductor device of the present invention. FIGS. 2(a) to 2(e) are diagrams showing an embodiment of the method for manufacturing a semiconductor device of the present invention. FIG. 3 is a cross-sectional view showing the structure of a conventional semiconductor device. 1... P-type silicon substrate 2... N-type well 3... Base region 4... Emitter region 5... Electrode extension part of collector region 6... Element isolation film 7... Channel stopper 8... Impurity layer with the same temperature as the channel stopper 9... Impurity layer with a lower concentration than the channel stopper 10... Silicon nitride film 11... Photoresist or higher Applicant Seiko Epson Corporation Agent Patent Attorney Suzuki Kisanbe (1 other person) Mitsuru 3 Tomoe

Claims (1)

[Claims] In a semiconductor device in which a vertical bipolar transistor is formed on one surface of a semiconductor substrate, and at least a portion of an emitter region of the vertical bipolar transistor is in contact with an element isolation film, the element isolation film is in contact with the emitter region. An impurity layer having the same conductivity type as the base region is disposed below the film, and the impurity layer has a higher concentration than the base region and a lower concentration than the channel stopper region. A semiconductor device characterized by: