JPH06196638A - Semiconductor device - Google Patents

Abstract

(57) [Summary] [Purpose] Since the injection efficiency of the emitter can be increased, h _FE can be earned while reducing the width of the base. [Structure] In a semiconductor device including a pnp transistor 22, an n-type epitaxial layer 4 is provided on a p-type silicon substrate 1. This n-type epitaxial layer 4
The pnp transistor 22 is provided therein. The emitter region 10 of the pnp transistor 22 is formed of at least two regions, a low concentration region and a high concentration region 31.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an n-type epitaxial layer and a pnp transistor provided on a substrate.

[0002]

2. Description of the Related Art Bipolar ICs have been known as semiconductor devices of this type. An npn transistor is usually mainly used as an element constituting the bipolar IC, and when it is advantageous to mix the two in terms of circuit configuration, the pnp transistor is used.
The transistor is used together. The pnp transistor includes a horizontal pnp transistor (or lateral pnp transistor) whose operation direction is parallel to the substrate surface, and a vertical transistor (or sub pnp transistor) whose operation direction is vertical to the substrate surface.

These npn transistors, lateral pnp
A bipolar IC using a transistor and a vertical pnp transistor at the same time has been conventionally manufactured by a method as shown in FIGS. That is, first, as shown in FIG. 8, p-type silicon substrate 1 to the n ⁺ -type buried layer 2,
3 is formed, and then an n-type silicon epitaxial layer 4 is formed on the p-type silicon substrate 1, and then a p ⁺ -type isolation diffusion region 5 reaching the p-type silicon substrate 1 is formed in the silicon epitaxial layer 4. Form.

Next, as shown in FIG. 9, in the silicon epitaxial layer 4, a p-type base region 7 for an npn transistor, a p-type emitter region 8 and a collector extraction region 9 for a vertical pnp transistor, and a lateral pnp are formed. P-type emitter region 10 and collector region 1 for a transistor
1 and 1, respectively.

Next, as shown in FIG. 10, in the silicon epitaxial layer 4, an n ⁺ type emitter region 12 and a collector extraction region 13 for an npn transistor and a vertical pnp are formed.
An n ⁺ type base take-out region 14 for a transistor and a base take-out region 15 for a lateral pnp transistor are formed respectively. After that, electrodes (not shown) are formed in the regions 7 to 15 to complete the bipolar IC.

In the bipolar IC shown in FIG. 10 manufactured in this manner, a collector region including an emitter region 12, a base region 7, and a silicon epitaxial layer 4 between the base region 7 and the buried layer 3. 16 and n
A pn transistor 17 is formed. A vertical pnp transistor 20 is formed by the emitter region 8, the base region 18 formed of the silicon epitaxial layer 4 below the emitter region 8, and the collector region 19 formed of the p-type silicon substrate 1 below the emitter region 8. ing. Further, an emitter region 10, a collector region 11,
A lateral pnp transistor 22 is constituted by the base region 21 formed of the silicon epitaxial layer 4 between the emitter region 10 and the collector region 11. The buried layer is not provided below the vertical pnp transistor 20 in order to obtain the direct current amplification factor h _FE .

The above-described bipolar IC shown in FIG. 10 has the following drawbacks. That is, in order to obtain a low-voltage, high-speed bipolar IC, it is necessary to reduce the thickness of the silicon epitaxial layer 4 to about 1 to 2 μm. _{Since FE} will decrease,
In order to prevent this, it is necessary to design the base width W small. However, if W is reduced to, for example, about 2 μm, there is a drawback that punch-through occurs between the collector and the emitter.

[0008]

SUMMARY OF THE INVENTION In consideration of the above problems, it is an object of the present invention to provide a semiconductor device in which the above-mentioned drawbacks of a conventional semiconductor device such as a bipolar IC are corrected.

[0009]

A semiconductor device according to the present invention is a semiconductor device comprising an n-type epitaxial layer provided on a substrate and a pnp transistor, wherein the pnp transistor is the n-type epitaxial layer. It is characterized in that it is provided in the layer and the emitter region thereof is formed by at least two regions of a low concentration region and a high concentration region.

[0010]

EXAMPLE A semiconductor device according to the present invention will be described below with a bipolar I
An embodiment applied to C will be described with reference to the drawings.
In FIGS. 1 to 4 below, the same parts as those in FIGS. 8 to 10 are designated by the same reference numerals, and the description thereof will be omitted as necessary.

First, a method of manufacturing the bipolar IC according to this embodiment will be described. As shown in FIG. 1, first, on the p-type silicon substrate 1, n such as arsenic (As) and antimony (Sb) is formed.
After the impurity is diffused in a high concentration to form a buried layer 2 and 3 of the n ⁺ -type, p-type silicon substrate 1 on the thickness of, for example, is 2μ
An n-type silicon epitaxial layer 4 having a specific resistance ρ of 1 Ωcm is formed. Then after forming the SiO ₂ film 24 on the surface of the silicon epitaxial layer 4, the SiO ₂
A is formed in the silicon epitaxial layer 4 through the film 24.
An n-type impurity such as s is selectively ion-implanted under a predetermined condition (injection impurity in the silicon epitaxial layer 4 is represented by ◯).

Next, as shown in FIG. 2, after a predetermined portion of the SiO ₂ film 24 is removed by etching to form openings 24a to 24d, p-type impurities such as boron (B) are introduced through these openings 24a to 24d. P diffused into the silicon epitaxial layer 4 and reaching the p-type silicon substrate 1
^{A +} type isolation diffusion region 5 is formed. This separation diffusion region 5
At the time of heat treatment for forming, the implanted impurities in the silicon epitaxial layer 4 are diffused in the depth direction and electrically activated. As a result, the impurity concentration in the silicon epitaxial layer 4 is higher than that of the silicon epitaxial layer 4, and the npn transistor 1 described later is also used.
Impurity concentration lower than that of the base region 7 of
For example, the n-type regions 26 to 28 of about 5 × 10 ¹⁶ cm ⁻³ are formed. After that, the SiO ₂ film 24 is removed by etching.

Next, as shown in FIG. 3, the n-type region 26 is formed.
A p-type collector region 11 and an emitter region 10 are provided therein, and a p-type emitter region 8 is provided in the n-type region 27.
And a p-type base region 7 is formed in the silicon epitaxial layer 4. After that, p is added to the base region 7.
^{A +} type graft base region 29 is formed, and p ⁺ type regions 30 and 31 are formed in the emitter regions 8 and 10, respectively.

Next, as shown in FIG. 4, n-type regions 26 to 2 are formed.
After forming the n ⁺ type base extraction regions 15 and 14 and the collector extraction region 13 respectively in 8 and forming the n ⁺ type emitter region 12 in the base region 7,
Electrodes (not shown) are formed in the regions 9, 11 to 15 and 29 to 31, respectively, to complete the intended bipolar IC.

The relation between the operating frequency f _T of the lateral pnp transistor 22 and the collector current Ic in the bipolar IC shown in FIG.
Is shown as a parameter in FIG. FIG. 6 shows the relationship between the direct current amplification factor h _{FE of the} lateral pnp transistor 22, the collector-emitter breakdown voltage V _CEO, and the base width W.

As is apparent from FIG. 6, W = 2 μm
In this case, V _CEO becomes 5 V or less and punch through occurs in the related art, whereas according to the present embodiment, h _FE
It is possible to increase V _CEO to about 10 V as compared with the conventional case without significantly lowering V. Therefore, as is clear from FIG. 5, it is possible to obtain f _T of a value of about 50 to 60 MHz.

Next, FIG. 7 shows the relationship between f _T and Ic of the vertical pnp transistor 20 in the bipolar IC according to the above embodiment. As is apparent from FIG. 7, when the vertical epitaxial pnp transistor 20 in the conventional bipolar IC also uses the silicon epitaxial layer 4 having a thickness (5 μm or more) at which punch-through does not occur, 20 MH
While only f _T of a value of about z can be obtained, according to the present embodiment, it is possible to obtain f _T of a value of about 100 MHz by using the silicon epitaxial layer 4 having a thickness of 2 μm. _CEO can be 15V or higher.

As described above, according to the above-described embodiment, even when the thickness of the silicon epitaxial layer 4 is extremely thin, for example, 2 μm, the lateral pnp transistor 22 is formed.
Also, since V _CEO of the vertical pnp transistor 20 can be made sufficiently high, an extremely high f _T can be obtained without causing punch through. The reason why punch through can be prevented in this way is as follows. That is, n-type regions 26 and 27 having an impurity concentration higher than that of the silicon epitaxial layer 4 are formed in the silicon epitaxial layer 4, and lateral pnp transistors 22 and vertical pnp transistors 20 are formed in these n-type regions 26 and 27, respectively. Therefore, the expansion of the depletion layer toward the base side at the collector-base junction can be made smaller as compared with the conventional one due to the higher impurity concentration.

Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made based on the technical idea of the present invention. For example, although the impurity concentration of the n-type regions 26 to 28 is set to 5 × 10 ¹⁶ cm ⁻³ in the above-mentioned embodiments, the impurity concentration can be set higher or lower than this as required. . However, in order to effectively prevent punch-through, etc., it is preferable to set the impurity concentration in the range of 1 × 10 ¹⁶ to 1 × 10 ¹⁷ cm ⁻³ .

[0020]

According to the semiconductor device of the present invention, in the n-type epitaxial layer provided on the semiconductor substrate or in the n-type semiconductor region having a high impurity concentration provided in the n-type epitaxial layer. In the provided pnp transistor, since the emitter of the pnp transistor is composed of the low concentration region which determines the base width and the high concentration region which makes h _FE earn, the injection efficiency of the emitter can be increased. H _FE can be earned by reducing the width of the base.

Further, the present invention is more effective when applied to a pnp transistor provided in an n-type semiconductor region having a high impurity concentration in the n-type epitaxial layer. The reason is that, in this case, the impurity concentration of the emitter region becomes smaller than that of the base region in the transistor. Therefore, by applying the present invention, the impurity concentration of the emitter region is increased to improve the injection efficiency. Because you can.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a first step in a diagram showing an example of a method of manufacturing a bipolar IC according to an embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing a step next to the step shown in FIG. 1 of the drawings showing an example of the method of manufacturing the bipolar IC according to the embodiment of the present invention in the order of steps.

FIG. 3 is a cross-sectional view showing the next step of the step shown in FIG. 2 among the drawings showing the example of the method of manufacturing the bipolar IC according to the embodiment of the present invention in the order of steps.

FIG. 4 is a cross-sectional view showing a step next to the step shown in FIG. 3 of the drawings showing the example of the method of manufacturing the bipolar IC according to the embodiment of the present invention in the order of steps.

FIG. 5 is a graph showing the relationship between the operating frequency f _T of the lateral pnp transistor and the collector current Ic with the base width W as a parameter.

FIG. 6 shows a direct current amplification factor h _{FE of a} lateral pnp transistor.
And a graph showing the relationship between the collector-emitter breakdown voltage V _CEO and the base width W.

FIG. 7 is a graph showing a relationship between an operating frequency f _T of a vertical pnp transistor and a collector current Ic.

FIG. 8 is a cross-sectional view showing a first step of the drawings showing the method of manufacturing the conventional bipolar IC in the order of steps.

FIG. 9 is a cross-sectional view showing a step next to the step shown in FIG. 8 of the drawings showing the method of manufacturing the conventional bipolar IC in the order of steps.

FIG. 10 is a cross-sectional view showing a step subsequent to the step shown in FIG. 9 among the drawings showing the method of manufacturing the conventional bipolar IC in the order of steps.

[Explanation of symbols]

 1 p-type silicon substrate 4 n-type epitaxial layer 5 isolation diffusion region 7 base region 8 emitter region 10 emitter region 11 collector region 12 emitter region 16 collector region 18 base region 19 collector region 20 vertical pnp transistor 21 base region 22 lateral pnp transistor 26 n-type region 27 n-type region 28 n-type region 30 high concentration region 31 high concentration region

Claims (3)

[Claims] 1. A semiconductor device comprising an n-type epitaxial layer provided on a substrate and a pnp transistor, wherein the pnp transistor is provided in the n-type epitaxial layer, and an emitter region thereof is a low concentration region. And a high-concentration region. At least two regions are formed. 2. The semiconductor device according to claim 1, wherein the pnp transistor is a lateral pnp transistor. 3. The semiconductor according to claim 1, wherein the pnp transistor is provided in an n-type semiconductor region having a high concentration of n-type impurity concentration provided in the n-type epitaxial layer. apparatus.