JPH0485879A - Gate array - Google Patents
Gate arrayInfo
- Publication number
- JPH0485879A JPH0485879A JP19883290A JP19883290A JPH0485879A JP H0485879 A JPH0485879 A JP H0485879A JP 19883290 A JP19883290 A JP 19883290A JP 19883290 A JP19883290 A JP 19883290A JP H0485879 A JPH0485879 A JP H0485879A
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- stage
- cells
- cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、入出力セル及び入出力パッドとセル配置領域
と配線領域とを二段で構成したゲートアレイに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a gate array having two stages of input/output cells, input/output pads, cell placement areas, and wiring areas.
［従来の技術］
従来のゲートアレイにおいては、第２図に示すように、
同一面上に入出力セル１１と入出力パッド１２、セル配
置領域１３と配線領域１４とが、それぞれ、チップ周囲
と中央部に配置されている。[Prior Art] In a conventional gate array, as shown in FIG.
Input/output cells 11, input/output pads 12, cell arrangement areas 13, and wiring areas 14 are arranged on the same surface at the periphery and center of the chip, respectively.
［発明が解決しようとする課題］
前述の従来技術では、１チツプに配置できる入出力セル
及び入出力パッドの数は、チップの周囲長とパッドピッ
チにより制限されていた。そのために、多くの入出力ビ
ンを必要とするものにおいては、セルの使用数が少ない
場合でも、チップの周囲長の長いもの、つまり、チップ
面積の高いものを使わざるを得す、セルの使用効率が著
しく悪いことがあった。そこで、本発明は従来のこのよ
うな問題を解決するため、入出力セル及び入出力パッド
とセル配置領域及び配線領域とを上段と下段に分けて、
上段においてチップ−面に入出力セルとパッドを配置し
、セルの使用効率を下げずに、多ビンの仕様を実現する
ことを目的とする。[Problems to be Solved by the Invention] In the prior art described above, the number of input/output cells and input/output pads that can be arranged on one chip is limited by the peripheral length of the chip and the pad pitch. Therefore, in products that require a large number of input/output bins, even if the number of cells used is small, it is necessary to use a chip with a long peripheral length, that is, a chip with a large chip area. There were times when the efficiency was extremely poor. Therefore, in order to solve these conventional problems, the present invention divides input/output cells, input/output pads, cell placement areas, and wiring areas into upper and lower stages.
The purpose is to arrange input/output cells and pads on the chip surface in the upper stage to realize multi-bin specifications without reducing cell usage efficiency.
［課題を解決するための手段］ 本発明のゲートアレイは、 半導体集積回路における、 ａ）上段の入出力セルと ｂ）上段の入出力パッドと Ｃ）下段のセル配置領域と ｄ）下段の配線領域と ｅ）上段と下段の間の絶縁膜 とからなる二段構成であることを特徴とする。[Means to solve the problem] The gate array of the present invention is In semiconductor integrated circuits, a) Upper input/output cell and b) Upper input/output pad and C) Lower cell placement area and d) Lower wiring area and e) Insulating film between the upper and lower stages It is characterized by a two-stage structure consisting of.
［実施例］
第１図は、本発明の実施例におけるゲートアレイの断面
図である。構成は、上段の入出力パッド１、入出力セル
２と、上段と下段を分ける絶縁膜３、下段のセル配置領
域４、配線領域５と、入出力セルと下段の配線とを接続
するホール６とからなる。上段の人出力セル２は、下段
の配線領域５の上に位置する。これにより、上段と下段
の接続はホール６によって行なう。使用しない入出力セ
ルは、絶縁膜３により下段には影響しない。第３図は、
本発明の上段の平面図であり、入出力パッド１と入出力
セル２がチップの全面に配置される。[Example] FIG. 1 is a cross-sectional view of a gate array in an example of the present invention. The structure includes an input/output pad 1 in the upper stage, an input/output cell 2, an insulating film 3 that separates the upper stage from the lower stage, a cell arrangement area 4 in the lower stage, a wiring region 5, and a hole 6 that connects the input/output cell and the wiring in the lower stage. It consists of The human output cell 2 in the upper stage is located above the wiring area 5 in the lower stage. Thereby, the connection between the upper stage and the lower stage is made through the hole 6. The input/output cells that are not used do not affect the lower stage due to the insulating film 3. Figure 3 shows
FIG. 2 is a plan view of the upper stage of the present invention, in which input/output pads 1 and input/output cells 2 are arranged over the entire surface of the chip.
第４図は、本発明の下段の平面図であり、セル配置領域
４と配線領域５で全面が構成されている。FIG. 4 is a plan view of the lower stage of the present invention, in which the entire surface is composed of the cell arrangement region 4 and the wiring region 5.
下段のセルの配置は、上段の入出力セルの配置を考慮し
て行えるので、入出力セルからの配線を短くしたい場合
には、上段の入出力セルの真下にセルを配置することが
できる。また、入出力セルが全面にあるので、電源セル
をチップに対して均等に配置することができるため、チ
ップ中心部への電源供給の安定化がはがれる。The arrangement of the cells in the lower row can be done taking into consideration the arrangement of the input/output cells in the upper row, so if it is desired to shorten the wiring from the input/output cells, the cells can be arranged directly below the input/output cells in the upper row. Furthermore, since the input/output cells are on the entire surface, the power cells can be arranged evenly on the chip, which makes it possible to stabilize the power supply to the center of the chip.
［発明の効果］
本発明は、ゲートアレイにおいて、入出力パッド及び入
出力セルと、セル配置領域及び配線領域とを二段で構成
したので、従来より多くの入出力ビンを使うことが可能
になった。また、従来と同じチップ面積のゲートアレイ
と比較すると、下段から入出力セルとパッドの部分が不
要となるので、内部セルの集積度が高まる。更に、電源
ビンを任意に配置することにより、チップ全体に対して
安定した電源供給が行える。入出力ビンからの配線を短
くしたい場合には、上段と下段のセルの配置を同じ位置
にすることができる。[Effects of the Invention] In the gate array of the present invention, the input/output pads, input/output cells, cell placement area, and wiring area are configured in two stages, so it is possible to use more input/output bins than before. became. Additionally, compared to conventional gate arrays with the same chip area, the input/output cells and pads from the bottom are no longer required, increasing the degree of integration of internal cells. Furthermore, by arbitrarily arranging the power supply bins, a stable power supply can be provided to the entire chip. If you want to shorten the wiring from the input/output bin, you can arrange the upper and lower cells at the same position.
第１図は、第３図第４図のＡ−Ａを示す主要断面図。 第２図は従来のゲートアレイの平面図。 第３図は実施例における上段の平面図。 第４図は実施例における下段の平面図。 １・・・入出力パッド ２・・・入出力セル ３・・・絶縁膜 ４・・・セル配置領域 ５・・・配線領域 ６・・・ホール 躬／１０ １１・・・入出力パッド １２・・・入出力セル １３・・・セル配置領域 １４・・・配線領域 以上 出願人 セイコーエプソン株式会社 代理人 弁理士 鈴木喜三部（他１名）稟２Ｃ FIG. 1 is a main sectional view taken along line A-A in FIGS. 3 and 4. FIG. FIG. 2 is a plan view of a conventional gate array. FIG. 3 is a plan view of the upper stage in the embodiment. FIG. 4 is a plan view of the lower stage in the embodiment. 1...I/O pad 2...Input/output cell 3...Insulating film 4... Cell placement area 5...Wiring area 6...Hall 謬／10 11...I/O pad 12...Input/output cell 13... Cell placement area 14...Wiring area that's all Applicant: Seiko Epson Corporation Agent: Patent attorney Kisanbe Suzuki (and 1 other person) Ren 2C
Claims (1)
ことを特徴とするゲートアレイ。[Claims] In a semiconductor integrated circuit, a) an input/output cell in an upper stage, b) an input/output pad in an upper stage, c) a cell arrangement area in a lower stage, d) a wiring area in a lower stage, and e) a region between the upper stage and the lower stage. A gate array characterized by having a two-stage configuration consisting of an insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19883290A JPH0485879A (en) | 1990-07-26 | 1990-07-26 | Gate array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19883290A JPH0485879A (en) | 1990-07-26 | 1990-07-26 | Gate array |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0485879A true JPH0485879A (en) | 1992-03-18 |
Family
ID=16397662
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19883290A Pending JPH0485879A (en) | 1990-07-26 | 1990-07-26 | Gate array |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0485879A (en) |
-
1990
- 1990-07-26 JP JP19883290A patent/JPH0485879A/en active Pending
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