JPH0485923U - - Google Patents
Info
- Publication number
- JPH0485923U JPH0485923U JP12698290U JP12698290U JPH0485923U JP H0485923 U JPH0485923 U JP H0485923U JP 12698290 U JP12698290 U JP 12698290U JP 12698290 U JP12698290 U JP 12698290U JP H0485923 U JPH0485923 U JP H0485923U
- Authority
- JP
- Japan
- Prior art keywords
- flop
- circuit
- flip
- data
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Pulse Circuits (AREA)
Description
第１図はこの考案の実施例を示すブロツク図、
第２図は従来のデータ同期処理回路を示すブロツ
ク図、第３図はクロツクによるデータのリタイミ
ングを示すタイムチヤート、第４図は従来のデー
タ同期処理回路の他のものを示すブロツク図であ
る。
Figure 1 is a block diagram showing an embodiment of this invention.
Fig. 2 is a block diagram showing a conventional data synchronization processing circuit, Fig. 3 is a time chart showing data retiming using a clock, and Fig. 4 is a block diagram showing another conventional data synchronization processing circuit. .
Claims (1)
ツプに取込み、その前段フリツプフロツプの出力
を機能回路で処理し、その機能回路の出力データ
を、上記クロツクを遅延回路で遅延したクロツク
により後段Ｄ形フリツプフロツプに取込んで出力
するデータ同期処理回路において、 上記遅延回路は半導体集積回路内に構成された
内部遅延回路と、その半導体集積回路の外部に設
けられた外部遅延回路との直列接続からなり、 上記前段Ｄ形フリツプフロツプ、上記機能回路
及び上記後段Ｄ形フリツプフロツプは上記半導体
集積回路内に構成され、 上記前段Ｄ形フリツプフロツプのクロツク入力
時点から、上記データが上記後段Ｄ形フリツプフ
ロツプに達するまでの遅延時間と、上記内部遅延
回路の遅延時間とがほゞ等しく選定されている、
ことを特徴とするデータ同期処理回路。[Claims for Utility Model Registration] Input data is taken into a D-type flip-flop at the front stage using a clock, the output of the flip-flop at the front stage is processed by a functional circuit, and the output data from the functional circuit is processed using a clock obtained by delaying the above-mentioned clock using a delay circuit. In a data synchronization processing circuit that takes in and outputs data to a subsequent D-type flip-flop, the delay circuit is a series connection of an internal delay circuit configured within a semiconductor integrated circuit and an external delay circuit provided outside the semiconductor integrated circuit. The front D-type flip-flop, the functional circuit, and the rear D-type flip-flop are configured in the semiconductor integrated circuit, from the time when the clock is input to the front-stage D flip-flop until the data reaches the rear-stage D flip-flop. and the delay time of the internal delay circuit are selected to be approximately equal to each other,
A data synchronization processing circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12698290U JPH0485923U (en) | 1990-11-29 | 1990-11-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12698290U JPH0485923U (en) | 1990-11-29 | 1990-11-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0485923U true JPH0485923U (en) | 1992-07-27 |
Family
ID=31874506
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12698290U Pending JPH0485923U (en) | 1990-11-29 | 1990-11-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0485923U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0226451A (en) * | 1988-07-15 | 1990-01-29 | Nec Corp | Primary group t point interface device |
-
1990
- 1990-11-29 JP JP12698290U patent/JPH0485923U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0226451A (en) * | 1988-07-15 | 1990-01-29 | Nec Corp | Primary group t point interface device |
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