JPH0487643U - - Google Patents

Info

Publication number
JPH0487643U
JPH0487643U JP1990130707U JP13070790U JPH0487643U JP H0487643 U JPH0487643 U JP H0487643U JP 1990130707 U JP1990130707 U JP 1990130707U JP 13070790 U JP13070790 U JP 13070790U JP H0487643 U JPH0487643 U JP H0487643U
Authority
JP
Japan
Prior art keywords
semiconductor chip
substrate
semiconductor device
semiconductor
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990130707U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990130707U priority Critical patent/JPH0487643U/ja
Publication of JPH0487643U publication Critical patent/JPH0487643U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/681—Shapes or dispositions thereof comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第１図ａは本考案の一実施例による半導体チツ
プの実装部の平面図、第１図ｂは第１図ａのＢ−
Ｂ′線断面図、第２図ａ乃至ｄは本考案の一実施
例による半導体チツプ実装時の充填樹脂の注入過
程図、第３図ａは本考案の他の実施例による半導
体チツプの実装部の平面図、第３図ｂは第３図ａ
のＣ−Ｃ′線断面図、第４図ａは従来例による半
導体チツプの実装部の平面図、第４図ｂは第４図
ａのＡ−Ａ′線断面図、第５図ａ乃至ｃは従来例
による半導体チツプ実装時の充填樹脂の注入過程
図、第６図ａ乃至ｃは従来例による半導体チツプ
実装時の樹脂充填の問題点を説明するための図で
ある。 １……半導体チツプ、２……基板、４……バン
プ、５……充填樹脂、１０，１１……貫通孔。

Claims (1)

  1. 【実用新案登録請求の範囲】 半導体チツプをバンプを介して基板に接続する
    とともに、前記半導体チツプと前記基板間を樹脂
    充填してなる半導体装置において、 前記基板の前記半導体チツプ実装領域の少なく
    とも一部に貫通孔を形成してなることを特徴とす
    る半導体装置。
JP1990130707U 1990-11-30 1990-11-30 Pending JPH0487643U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990130707U JPH0487643U (ja) 1990-11-30 1990-11-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990130707U JPH0487643U (ja) 1990-11-30 1990-11-30

Publications (1)

Publication Number Publication Date
JPH0487643U true JPH0487643U (ja) 1992-07-30

Family

ID=31878024

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990130707U Pending JPH0487643U (ja) 1990-11-30 1990-11-30

Country Status (1)

Country Link
JP (1) JPH0487643U (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09214071A (ja) * 1996-01-31 1997-08-15 Hitachi Ltd 家庭用電気機器の制御基板
KR100545881B1 (ko) * 1998-03-24 2006-01-25 세이코 엡슨 가부시키가이샤 반도체 칩의 실장 구조체, 액정장치 및 전자기기

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09214071A (ja) * 1996-01-31 1997-08-15 Hitachi Ltd 家庭用電気機器の制御基板
KR100545881B1 (ko) * 1998-03-24 2006-01-25 세이코 엡슨 가부시키가이샤 반도체 칩의 실장 구조체, 액정장치 및 전자기기

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