JPH0499059A - Delay circuit for gate array - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a delay circuit for a semiconductor integrated circuit for a gate array.

[Conventional technology]

Conventional delay circuits in gate arrays create delay times by connecting multiple inverter circuits in series.

In addition, the technology disclosed is the patent application published in 1986-49.
As shown in 816, there was a plurality of inverter circuits connected in series via a circuit that caused a voltage drop.

[Problem to be solved by the invention 5] In the case of a gate array, the conventional circuit system in which a plurality of inverter circuits are connected in series has a fixed capacity of one inverter circuit and is designed for high speed. In order to obtain a constant delay time, a very large number of inverter circuits were required.Also, as in the patent application published in 1981-59816, when the output goes through several elements that cause a voltage drop, There were five problems: the signal could not reach the power supply, so the next stage gate could not be completely turned on and off.Therefore, the present invention aims to solve the above problems (with a relatively small number of elements and , an object of the present invention is to provide a gate array delay circuit that can completely control the gates of the next stage.

[Means to solve the problem]

The delay circuit for a gate array of the present invention is α) a semiconductor integrated circuit for a gate array having a first power source and a second power source, and also having a first conductivity type MOSFET and a second conductivity type MOSFET. , b) First stage C! C) A group of multiple CMOS inverter circuits in which the output of a MOS inverter circuit is connected in series to the input of a CMOS inverter circuit in the next stage, and C) a source electrode is connected to a first power supply terminal, and a gate electrode and a drain a first conductivity type whose electrodes are connected to each other;
d) a second MOSFET of a second conductivity type having a source electrode connected to a second power supply terminal and a gate electrode and a drain electrode connected to each other;
g) a signal potential correction circuit, and f) one power source of the plurality of CMOS inverter circuit groups is supplied from the drain electrode of the first MOSFET, and the other power source is supplied from the drain electrode of the 20M08FET. g) The first input signal of the plurality of CMOS inverter circuit groups and the output signal of the final stage are input to the signal potential correction circuit.

[Effect]

According to the above configuration of the present invention, after causing a voltage drop by the first MOS FET and the second MOSFET,
Since power is supplied to the CMOS inverter circuit group, a large delay time can be obtained with a small number of elements, and the signal potential correction circuit makes the output signal a signal that swings between power supply voltages.

〔Example〕

FIG. 1 is a circuit diagram of a first embodiment of the present invention. In Figure 1, 101, 103, 105.1/07 HaP type M
O3F'ET, i02,104°106.108
is an N-type MQSNET. P-type MosFET101m
The source electrodes of 103, 105, 107 are connected in common, and the source electrodes of N-type MO8FETIQ2, 104, 106, 10
8 source electrodes are commonly connected. P-type MO
The gate electrode and drain electrode of S FET101 and N-type MOSFET102 are connected to each other, and C
It constitutes a MOS inverter circuit. Also MOSFE
T103 and 104, MOSFET105 and 106, MO
The SFETs 107 and 108 similarly constitute an inverter circuit. The drain electrodes, which are the outputs of the previous stage, of the four inverter circuits described above are connected to the gate electrodes, which are the inputs of the next stage. However, MOSFE
The gate electrode of the first inverter circuit consisting of T101 and T102 is connected to the input signal terminal 14, and MOSFET1
The drain electrode of the last inverter circuit consisting of 07 and 108 is connected to the output signal terminal 15. P-type MOS
The source electrode of FETI 1 is +V, which is the positive power supply terminal.
DD, and the gate electrode and drain electrode are connected in common, and the P-type MOSFETs 101, 105, 1
It is connected to the source electrodes of 05 and 107. N-type MO
The source electrode of 5FET12 is the negative power supply terminal -V
SS, the gate electrode and the drain electrode are connected in common, and the N-type MOSFETs 102, 104.1
It is connected to the source electrodes of 06 and 108. Therefore, a voltage drop approximately equal to the respective threshold voltages occurs in the P-type MOSFET 11 and the N-type Mo5FET 12, and the inverter circuit group consisting of the MOSFETs 101 to 108 operates at a voltage lower than that between the molecules VDD and -VSS. A signal inputted from the input signal terminal 14 is outputted from the output signal terminal 15 through an inverter circuit group consisting of MOSFETs I01 to 108. At this time, there is a voltage drop due to MOSFETs 11 and 12, and since the inverter circuit group operates at a low voltage, a large delay time can be obtained relative to the number of stages of inverter circuits.

The circuit surrounded by the broken line 16 constitutes a signal potential correction circuit. 131 is a N A'N D circuit, 132 is a NOR circuit, 136 is a P-type MO5FET, and 164 is an N-type M
It is O8FET. P type MOSFET155 and N type M
The source electrodes of OSFET 154 are +VD, D, and
-VSS, and their drain electrodes are connected to each other and to the output signal terminal 15. Also P type M
A NAND circuit 151. NOR circuit 1
An input signal terminal 14 is connected to each of the 32 first human-powered gates, and an output signal terminal 15 is connected to each of the second human-powered gates.

Now, as mentioned above, the signal input from the input signal terminal 14 is connected to the P-type MOSFET 07 and the N-type MOSFET 108.
It is output from the final stage inverter circuit consisting of M
There is a voltage drop due to OSFETs 11 and 12, and the signal cannot swing all the way to between the power supply potentials, so if it is sent as a signal to the next stage circuit, it will not be a control signal that can be completely turned on or off. This causes short-circuit current between transistors, resulting in an incomplete signal for a CMOS circuit.Therefore, MOSFET10
The output signal of the inverter circuit consisting of 7 and 108 is NAN
D circuit 131, P type MOS FET 163, and NO
By outputting from the output signal terminal 15 via the R circuit 132 and the N-type MOSFET 134, it becomes a signal between the +VDD and -VSS power supplies. Also P type MO, 5FET153 and N
Common drain electrode of type MOSFET154 and P type MOSFET154
A NAND circuit 15 is created by connecting the common drain electrodes of the FET 107 and the N-type MOSFET 108 and feeding them back.
This prevents short-circuit current from flowing in the 1 and NOR circuits. Furthermore, by inputting the input signal terminal 14 to the first gates of the NAND circuit 131 and the NOR circuit 132, the MO8FE'I'155, 154 and the MOSFET
ET107.1 [18 conflicts are prevented from occurring.

The above circuit realizes a delay circuit that operates at a low voltage, has a large delay time, and obtains a normal control signal output signal that swings between power supply voltages.

FIG. 2 is a circuit diagram of a second embodiment of the invention.

In Figure 2, P-type MO8FET201.203.20
The inverter circuit group in FIG. 1 is made up of MOSFETs 5 and N-type MOSFETs 202, 204, and 206. The inverter circuit group in FIG. This is an example of an odd number of inverter circuits. Therefore, the input signal terminal 24 and the output signal terminal 25 have an inverted relationship. Also P
Type MOSFET 21 and N type MOSFET 22 are respectively P type MOSFET 1 and N type MOSFET 1 in Fig. 2.
It corresponds to 2 and plays the same role.

The circuit surrounded by the broken line 23 constitutes a signal potential correction circuit. Compared to the signal potential correction circuit 16 of FIG. 1, the signal potential correction circuit 23 of FIG. 2 has an additional inverter circuit 265. The circuit example shown in FIG. 2 operates in substantially the same way as the circuit example shown in FIG. As mentioned above, in the circuit shown in FIG. 1, the input signal terminal 14 and the output signal terminal 15 are in the same phase, and in the circuit shown in FIG. 2, the input signal terminal 24 and the output signal terminal 25 are in the opposite phase. It becomes.

Although specific circuit examples have been given above in FIGS. 1 and 2, these are only examples, and the number of inverter circuit groups may be any number.

Also, the voltage drop circuit configured by connecting the gate electrode and drain electrode of the MOSFET should not be used on both types of source sides (but it may be used only on one side. Also, connect multiple stages in series instead of just one stage to further increase the voltage drop). You can do it.

In addition, as shown in FIG. 1 and FIG. 2, there are other circuit examples of the signal potential correction circuit.

〔Effect of the invention〕

As described above, according to the present invention, since the inverter circuit is operated by lowering the voltage, there is an effect that the number of inverter circuits is reduced.

Furthermore, since the signal potential correction circuit extracts the output signal as a signal that has been completely switched between power supplies, it has the effect of completely turning on and off the gates of the next stage and not causing leakage current or the like.

Furthermore, since the above circuit can be constructed from a group of transistors having the same shape, it has the advantage that it can be used even in gate array devices whose design is relatively old.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the invention, and FIG. 2 is a circuit diagram showing a second embodiment of the invention. 11, 2. 1 zI 5°...P type M 12, 2. 1 34°...N type M 15 , 2 14 , 2 15 , 2 161 . 1.101,103,105.107 201. 205,20 5.255 ・・・・・・O
S ′E ′E T 2.1'02,104,106.108202.204
,206,254...5FFiT6......Signal potential correction circuit 4
......Input signal terminal 5...
...... Output signal terminal 261...
・・・・・・NAND circuit 152.252・・・・・・
・・NOR circuit 235・・・・・・・・・・・・・・・
...Applicant for inverter circuits and above Seiko Epson Corporation

Claims (1)

[Claims] (1) a) It has a first power source and a second power source, and also has a first conductivity type insulated gate field effect transistor (hereinafter MO).
SFET) and a second conductivity type MOSFET, b) the output of the previous stage complementary insulated gate field effect inverter circuit (hereinafter referred to as CMOS inverter circuit) is transferred to the next stage CMOS a plurality of CMOS inverter circuits connected in series to the input of the inverter circuit; c) a first conductivity type in which the source electrode is connected to the first power supply terminal and the gate electrode and the drain electrode are connected to each other; d) a second MOSFET of a second conductivity type whose source electrode is connected to a second power supply terminal and whose gate electrode and drain electrode are connected to each other; and e) a signal potential correction circuit. , f) one power source of the plurality of CMOS inverter circuit groups is supplied from the drain electrode of the first MOSFET, and the other power source is supplied from the drain electrode of the second MOSFET, g) the signal potential correction A delay circuit for a gate array, characterized in that the first input signal and the output signal of the final stage of the plurality of CMOS inverter circuit groups are input to the circuit.