JPH0520216A - Memory device with bus monitoring mechanism - Google Patents

Abstract

PURPOSE:To provide a memory device with a bus monitoring mechanism which is not affected by the number of slots and does not require the change in its constitution at the time of monitoring a bus. CONSTITUTION:A monitoring control part 17 detects the generation of an access to be monitored on a system bus SB. At the time of generating the access, an address selector 13 interrupts an address signal on an address bus AB and outputs a write address generated from an address generating part 16 to a memory array 11. A write selector 14 selectively supplies any one of the address signal on the AB, control information on a control bus CB and data on a data bus DB to the memory array 11 to write the address signal, control information and data in respective areas specified by respective write addresses.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device with a bus monitoring mechanism having a bus monitoring mechanism for detecting a fault on a system bus.

[0002]

2. Description of the Related Art As a component of a computer, a central processing unit, a memory device composed of RAM and ROM, and an input / output control device composed of a keyboard, a display, a magnetic storage device and the like can be mentioned. The respective devices are connected by a system bus composed of a control bus, an address bus, and a data bus, and various types of information are transmitted and received between the respective components. In general, some or all of the devices are connected to the system bus in a removable structure. This is carried out in order to easily deal with the replacement of the failed device and the change of the component. A structure on the system bus that can be freely attached and detached will be referred to as a slot here.

FIG. 2 shows a block diagram of a general computer. As shown in the figure, control bus CB, address bus A
B, a system bus SB composed of a data bus DB, a central processing unit 1, a memory unit 2, an input / output control unit 3
Are connected, and the bus monitoring device 5 is further connected via the slot 4. The central processing unit 1 performs various arithmetic processing based on a predetermined program. The memory device 2 is composed of a program and data referred to by the central processing unit 1, and a ROM and a RAM for storing the calculation result of the central processing unit. Input / output control device 3
Is composed of a keyboard, a display, a magnetic storage device, and the like.

When a failure occurs in each device connected to the system bus SB, the bus monitoring device 5 has a purpose of analyzing information on the system bus SB, specifically, access, for the purpose of analyzing the part that causes the failure. Address (address signal),
Access attribute (control information), access data (data)
Etc. are collected (bus monitoring). In the computer having the above-described configuration, the bus monitoring device 5 normally does not operate and operates only when necessary to monitor the bus.

That is, a device which is not essential for the operation of the computer is connected to the system bus SB. If there is only one slot on the system bus SB, that is, only slot 4, and you want to connect, for example, a SCSI standard input / output device to the system bus SB, prepare an interface for expanding the slot 4 into a plurality of slots. A method of connecting two devices to the interface, or connecting a SCSI standard input / output device or the like to the slot 4 and changing the device connected to the slot 4 to the bus monitoring device 5 only when a failure occurs. Was taken.

[0006]

In carrying out the above-described two methods, first, when a plurality of devices are connected to the slot 4, a special interface must be prepared. Further, when the bus monitoring device 5 is connected only when a failure occurs, the configuration of the computer at the time of the failure and the configuration of the computer at the time of bus monitoring change, which causes a problem that accurate bus monitoring cannot be performed. The present invention was made with attention to the above points,
It is an object of the present invention to provide a memory device with a bus monitoring mechanism that is not affected by the number of slots and does not need to change the configuration when monitoring the bus.

[0007]

SUMMARY OF THE INVENTION A memory device with a bus monitoring mechanism according to the present invention includes a system bus having an address bus, a control bus, and a data bus, a memory array connected to the system bus, and the system. A monitoring control unit that detects the occurrence of access to be monitored on the bus, an address generation unit that outputs a write address of the memory array when the access that is to be monitored occurs, and the monitoring control unit is configured to detect the monitoring target. When the occurrence of the access is detected, the address signal transmitted on the address bus is blocked, and the address selector for supplying the write address output from the address generator to the memory array and the address selector are transmitted on the address bus. Selects an address signal, control information transmitted on the control bus, and data transmitted on the data bus The supply to the memory array, in which a write selector for writing control by the writing address.

[0008]

In this device, the monitor control unit detects the occurrence of access to be monitored on the system bus. When this access occurs, the address selector blocks the address signal on the address bus and outputs the write address output from the address generator to the memory array. Then, the write selector selectively supplies the address signal on the address bus, the control information on the control bus, and the data on the data bus to the memory array, and the address signal, control information, and Write the data.

[0009]

1 is a block diagram of a memory device according to the present invention. The memory device 10 shown in the figure corresponds to the memory device 2 shown in FIG. Memory device 1
0 memory array 11 has a memory controller 12,
The address selector 13, the write selector 14, and the output buffer 15 are connected. The memory array 11 is RA
A storage area including a storage chip such as M or EEPROM, and a monitoring result storage area 11a for storing a monitoring result when bus monitoring is performed are provided in addition to an area for storing data and the like associated with normal processing. ing.

The memory controller 12 generates an enable signal for setting the read and write states of the memory array 11 and RAS and CAS signals. The address selector 13 is composed of a gate circuit that selects whether the address output to the memory array 11 is received from the address generator 16 or the address bus AB. The write selector 14 is composed of a gate circuit that selects whether the data to be written in the memory array 11 is received from the data bus DB or the combined bus MB in which the control bus CB and the address bus AB are combined.

The output buffer 15 comprises a register for temporarily storing the data read from the memory array 11. Control bus CB and address bus AB
A monitor controller 17 is connected to the. The monitoring control unit 17 stores the access attribute and the address signal in order to specify the access of the system bus SB to be monitored, and compares the access attribute and the address signal with the values of the control bus CB and the address bus AB. When it is determined that it is a target, the control signals CS1 to CS3 are controlled at a predetermined timing, the inputs of the address selector 13 and the write selector 14 are switched, and the address generator 16 is incremented.

The address selector 13 has a control signal CS1.
Is set to be valid, the input is switched from the address bus AB to the address generator 16. Address generator 16
Performs the increment of the stored write address when the control signal CS2 is set to be valid and invalid (when it is row active, at the time of falling and at the time of rising). The write selector 14 has a control signal C
When S3 is set to valid, the input is switched from the data bus DB to the composite bus MB.

When the system bus SB is set in a state to be monitored by the monitor control unit 17, the contents of the composite bus MB, that is, the address, in the area of the memory array 11 corresponding to the write address output from the address generation unit 16. Signals and access attributes are written. After that, by further incrementing the address generator 16 and switching the input of the write selector 14, the data on the data bus DB is written in the monitoring result storage area 11a.

FIG. 3 shows a conceptual diagram of the monitoring result according to the present invention. As shown in the figure, the monitoring result storage area 11a is composed of a plurality of items having a 32-bit width, which are indicated by the addresses A0 to An. Each time the monitoring control unit 17 recognizes an access to be monitored, the monitoring result is stored in two items in the monitoring result storage area 11a. That is,
The contents (address signal and access attribute) of the composite bus MB are stored in the first item, and the contents (data) of the data bus DB are stored in the next item.

When the storage in the final item of the monitoring result storage area 11a, that is, the item indicated by the address An is completed, the address generator 16 sets the content to the address A0 again and repeats the increment.

The operation of the memory device with a bus monitoring function according to the present invention will be described with reference to FIG. In the case where the monitoring control unit 17 implements bus monitoring, the central processing unit 1 controls the monitoring control unit 17 in advance to set the access attribute and address signal to be monitored, and activates the monitoring control unit 17. In addition, usually, the control signals CS1 to C
S3 is all disabled and address selector 1
3 receives the input of the address bus AB, and the write selector 1
The memory array 1 receives the input of the data bus DB.
Output to 1.

FIG. 4 is a flowchart according to the present invention. First, the monitoring controller 17 reads the access attribute transmitted on the control bus CB and the address signal transmitted on the address bus AB at a predetermined timing, compares them with the preset access attribute and address signal, and monitors them. It is determined whether a target access has occurred (step S1). When the result of step S1 is YES, that is, when the access to be monitored occurs, the monitoring controller 17 sets the control signal CS1 to be valid, and switches the input acceptance of the address selector 13 to the address generator 16 (step 2).

Further, the supervisory controller 17 controls the control signal CS2.
Is set to be valid, and the input acceptance of the write selector 14 is switched to the composite bus MB (step S3). Here, when the memory array 11 is set to the writable state under the control of the memory controller 12, the content of the composite bus MB is set in the area indicated by the address generation unit 16, for example, the address A0 on the monitoring result storage area 11a. It is written (step S4).

After that, the supervisory controller 17 controls the control signal CS.
2 is enabled and the content of the address generator 16 is incremented (step S5), the control signal CS3 is disabled, and the input acceptance of the write selector 14 is switched to the data bus DB (step S6). In this state,
When the memory array 11 is set to the writable state again under the control of the memory controller 12, the data on the data bus DB is written in the item of the address A1 (step S7).

The monitoring control unit 17 has a monitoring result storage area 11
When the writing of the contents of the data bus DB to a is completed, the control signal CS1 is set to invalid and the input acceptance of the address selector 13 is switched to the address bus AB (step S
8) Further, after the control signal CS2 is invalidated and the address generator 16 is incremented (step S
9) The process returns to step S1 and waits for an access to be newly monitored. In this way, the memory device 10 is used for bus monitoring of the system bus SB when a failure occurs, and is used as a normal storage device when normal.

The present invention is not limited to the above embodiments.
In the embodiment, the memory device 2 is a RAM or an EEPROM.
Although the description has been made by taking as an example the case of being configured by the above, a storage medium such as a magnetic storage device may be used. Also, the monitoring control unit 17
Does not necessarily have to monitor both the access attribute and the address signal when determining the access to be monitored.
Only one of them may be used.

[0022]

As described above, the memory device with the bus monitoring function of the present invention does not need to prepare a slot for connecting to the system bus for the bus monitoring device for specially performing the bus monitoring. Therefore, it is possible to avoid the situation where the configuration at the time of effective use of the slot and the bus monitoring is different from that at the time of failure occurrence.

[Brief description of drawings]

FIG. 1 is a block diagram of a memory device according to the present invention.

FIG. 2 is a configuration diagram of a general computer.

FIG. 3 is a conceptual diagram of a monitoring result according to the present invention.

FIG. 4 is a flowchart according to the present invention.

[Explanation of symbols]

 11 memory array 13 address selector 14 write selector 16 address generator 17 monitoring controller

Claims (1)

1. A system bus including an address bus, a control bus, and a data bus, a memory array connected to the system bus, and an access to be monitored on the system bus. A monitoring control unit that detects the occurrence, an address generation unit that outputs the write address of the memory array when the access to be monitored occurs, and the monitoring control unit detects the occurrence of the access to be monitored, An address selector that blocks an address signal transmitted on the address bus and supplies a write address output from an address generator to the memory array; an address signal transmitted on the address bus; and a control bus on the control bus. The control information to be transmitted and the data to be transmitted on the data bus are selectively supplied to the memory array. A memory device with a bus monitoring mechanism, comprising: a write selector that performs write control based on a write address.