JPH05218092A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To enhance the breakdown strength, and at the same time, to reduce the capacitance between gate and source by making it difficult to allow the field concentration on the gate electrode. CONSTITUTION:An insulating film 4 and a metallic film 5 are formed on a GaAs substrate in that order. After the metallic film 5 and the insulating film 4 are anisotropically etched with a resist 6 as a mask, an operating layer 3 is etched to form a recess. Then, a resist 7 made of cyclopentanone and 2-(2- methoxy ethoxy) ethanol as the main components is coated in order to deposit a gate metal 8 while leaving resists 7a and 7b in the recess immediately below the insulating film 4 by the irradiation of ultraviolet rays and development.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a field effect transistor, and more particularly to a method for forming a gate electrode of a field effect transistor having a recess structure using a compound semiconductor.

[0002]

2. Description of the Related Art A conventional planar Schottky gate field effect transistor (MESFET) will be described with reference to FIG.

First, a non-doped GaAs buffer layer 2 and a thin N-type GaAs operating layer 3 are epitaxially grown on a semi-insulating GaAs substrate 1. Non-doped G here
The N-type GaAs operating layer 3 may be formed by omitting the epitaxial growth of the aAs buffer layer 2 and the N-type GaAs operating layer 3 and directly ion-implanting Si into the semi-insulating GaAs substrate 1.

Next, after forming the source electrode 9 and the drain electrode 10 in ohmic contact with the N-type GaAs operating layer 3, the gate electrode 8 in Schottky contact is formed to complete the element portion.

In this MESFET, the source electrode 9
Since the resistance of the N-type GaAs operating layer 3 (hereinafter referred to as source resistance) between the gate electrode 10 and the gate electrode 10 is large, it is known that high frequency characteristics and high speed operation are limited.

In order to improve this characteristic, it is necessary to increase the carrier concentration of the operating layer or to thicken the operating layer, but in any case, there is a problem that the pinch-off voltage becomes excessive. Increasing the carrier concentration causes a problem of lowering the gate breakdown voltage.

Recessed MESFET that solves this problem
This will be described with reference to FIGS.

First, as shown in FIG. 5A, a non-doped GaAs buffer layer 2 and a thick N-type GaAs operating layer 3 are epitaxially grown on a semi-insulating GaAs substrate 1. Here, the non-doped GaAs buffer layer 2 may be omitted, and Si may be directly ion-implanted into the semi-insulating GaAs substrate 1 to form the thick N-type GaAs operating layer 3.

Next, as shown in FIG. 5B, an insulating film 4 made of SiO ₂ or SiN _x is deposited by a CVD method, and a gate opening is formed by anisotropic dry etching using the resist 6 as a mask. In particular, since a gate electrode having a submicron gate length requires high accuracy within 1/10 μm, wet etching is not performed in this step.

Next, as shown in FIG. 5C, the N-type GaAs operating layer 3 is etched using a mixed solution of sulfuric acid and hydrogen peroxide to form a recess. Next, the source electrode 9, the drain electrode 10 and the gate electrode 8 are formed to complete the element portion.

[0011]

DISCLOSURE OF THE INVENTION Conventional recess type MES
In the FET, when the gate metal is deposited or sputtered in the recess by vapor deposition or sputtering as shown in FIG. 5C, the gate length L _g cannot be controlled accurately.

Further, since the gate metal wraps around the recess region, the gate-source capacitance C _gs between the side surface of the gate electrode 8 and the N-type GaAs operating layer 3 increases, and the high frequency characteristics deteriorate.

Further, N-type GaA is used with the insulating film 4 as a mask.
Since the s-operation layer 3 is wet-etched, the insulating film 4 becomes an "overhang", where the gate metal becomes extremely thin or broken, resulting in an extremely high gate resistance. Therefore, there are problems such as characteristic deterioration and yield reduction.

[0014]

A method of manufacturing a field effect transistor according to the present invention comprises a step of sequentially depositing an insulating film and a metal film on one main surface of a semiconductor substrate, and the metal film using a first resist as a mask. And a step of anisotropically dry etching the insulating film and then etching the surface of the semiconductor substrate with the insulating film as a mask to form a recess, and cyclopentane and 2- (2-methoxyethoxy) ethanol as main components. A step of applying a second resist and then developing it by irradiating with ultraviolet rays, and a step of depositing a gate metal on the entire surface and then etching the gate metal using a third resist covering a portion immediately above the recess as a mask. And a step of removing the insulating film and the second resist to form a gate electrode.

[0015]

EXAMPLE FIG. 1A shows a first example of the present invention.
This will be described with reference to (d).

First, as shown in FIG. 1A, a non-doped GaAs buffer layer 2 is formed on a semi-insulating GaAs substrate 1.
And thickness 0.15-0.3 μm, carrier concentration 2-3
An N-type GaAs operating layer 3 of × 10 ¹⁷ cm ^-3 is epitaxially grown. Next, after performing element isolation (not shown), Si having a thickness of 0.3 to 0.7 μm formed by the CVD method.
An insulating film 4 made of an O ₂ film is deposited, and a metal film 5 made of WSi _x having a thickness of 0.1 to 0.3 μm is deposited thereon by a sputtering method.

Next, after applying the first resist 6, g
Pattern using a line or i-line stepper. First
As the resist 6 of, for example, TSMR manufactured by Tokyo Ohka Kogyo
-8900 or PFI-15 manufactured by Sumitomo Chemical is used.

Next, the metal film 5 is anisotropically etched by reactive ion etching using a gas such as SF ₆ or CHF ₃ . Next, the insulating film 4 is anisotropically etched by reactive ion etching using a gas such as CF ₄ or SF ₆ .

Next, as shown in FIG. 1B, after removing the first resist 6, the N-type GaAs operating layer 3 is wet-etched with a mixed solution of sulfuric acid and hydrogen peroxide to form a recess. ..

Next, cyclopentanone and 2- (2-
Deep based on (methoxyethoxy) ethanol
25 after applying the second resist 7 having UV sensitivity
Bake in an oven at 0 ° C. for 45 minutes. By this baking, the second resist 7 completely enters the gap in the recess, and the photosensitive characteristics and the adhesion are stabilized. As the second resist, for example, SAL110 manufactured by Shipley Co., Ltd.
To use.

Next, a deep UV ultraviolet ray hν is applied on the entire surface.
(Wavelength λ = 240 to 300 nm) is irradiated. Since no external mask is used here, the irradiation conditions are, for example, using Deep UV exposure apparatus PLA-520 manufactured by Canon Inc., and irradiating ultraviolet rays having a wavelength of 250 nm with 1.5 to 2.0 J / cm ² .

At this time, the metal film 5 formed on the insulating film 4 serves as a mask, and the second resists 7a and 7b that enter under the eaves of the insulating film 4 are not exposed to light.

Next, as shown in FIG. 1 (c), the second resist 7 exposed by a developing solution dedicated to the second resist 7 is dissolved, so that the second resist 7 is exposed only in the recess just below the eaves. The second resists 7a and 7b are left. For example, it is developed for 60 seconds by SAL101 developer manufactured by Shipley.

Next, as shown in FIG. 1 (d), after depositing the gate metal 8 by vapor deposition or sputtering, the excess gate metal is etched using a third resist (not shown) as a mask, and then a hydrofluoric acid-based material is used. The insulating film 4 is etched with the above solution.

In this embodiment, heat resistant and chemical resistant WSi _X is used as the gate metal.

To further reduce the gate resistance, WSi _x
On top of this, a low resistance metal such as TiN-Pt-Au is formed. Here, TiN-Pt is used because WSi _x and Au are used.
This is for preventing the above-mentioned reaction from occurring and for improving the adhesiveness.

Finally, using a Microposit 1165 remover manufactured by Shipley, for example, the second resist 7a,
The gate electrode 8 is completed by dissolving and removing 7b.

The cutoff frequency f _T, which is one of the important characteristics of the MESFET, is expressed by the following equation from the source-gate capacitance C _gs and the transconductance g _m .

F _T = g _m / 2πC _gs (1) The dependence of the cutoff frequency f _{T on} the recess-gate distance X is shown in FIG.
Shown in. As the distance X from the source-side recess end to the gate electrode end increases, C _gs decreases and f _T improves. When X is further increased, g _m decreases and f _T
Is going down.

In the present embodiment, it was possible to improve f _T by about 1.3 times compared with the conventional structure by setting X = 0.3 μm. The impurity concentration of the N-type operating layer 3 is set to 2.5 × 10 ¹⁷ c
m ⁻³ , thickness 0.2 μm, gate length L _g 0.5 μm
m and the gate width was 1 μm.

If a positive resist containing an ordinary novolac resin as a main component is used as the second resist 7,
The following problems arise. Since it is liable to be thermally altered and cannot be baked at 150 ° C. or higher, it cannot be sufficiently inserted under the eaves of the insulating film. Since the heat resistance is low, the resist is deformed or deteriorated when the gate metal is vapor-deposited or sputtered and when the gate electrode is dry-etched. As a result, the gate electrode is deformed and resist removal becomes difficult.

Next, a second embodiment of the present invention will be described with reference to FIGS. 2 (a) and 2 (b).

First, as in the first embodiment, a non-doped GaAs buffer layer 2 on a semi-insulating GaAs substrate 1,
The N-type GaAs operating layer 3 is epitaxially grown. Next, after isolation between elements (not shown), an insulating film 4 is deposited, and the insulating film 4 is etched by using the first resist 6 as a mask. Next, after removing the first resist, N
The type GaAs layer 3 is wet-etched to form a recess. Next, after applying the second resist 7, 250
Bake at ℃.

[0034] Next, as shown in FIG. 2 (a), by etching the second resist 7 by anisotropic etching using O ₂ gas, the eaves directly below the side face of the insulating film 4 of insulating film 4 The second resists 7c and 7d are left.

Next, as shown in FIG. 2B, after the gate metal 8 is deposited by vapor deposition or sputtering, the excess gate metal is etched using the third resist (not shown) as a mask. Next, the insulating film 4 is etched with a hydrofluoric acid-based solution to dissolve and remove the second resists 7c and 7d.

In this embodiment, the resist 7 is formed on the side surface of the insulating film 4.
Since c and 7d remain, the gate length can be shortened. Since the gate electrode position in the recess is closer to the center,
Further, there is an advantage that the breakdown voltage is improved.

Also, unlike the first embodiment, there is an advantage that the metal film on the insulating film 4 is not necessary and the deep UV light is not irradiated, so that the process can be shortened.

The present invention is based on the GaAs MESFE described above.
Besides T, it can be applied to a field effect transistor using a GaAs / GaAlAs heterojunction two-dimensional electron gas and a field effect transistor using a compound semiconductor such as InP.

[0039]

The recess is filled with a heat resistant resist having a sensitivity to Deep UV. Deep UV light is vertically irradiated with the metal film formed on the insulating film as a mask, and after development, a gate metal is deposited.

As a result, since the gate electrode can be formed in the recess in a self-aligned manner, the gate length can be controlled with high accuracy. Further, since the gate metal is not deposited on both ends of the recess, the source-gate capacitance can be reduced, the electric field concentration is alleviated, and the gate reverse breakdown voltage is improved. Further, since there is no eaves between the insulating film and the recess, there is an effect that the gate metal is not disconnected.

As described above, in the recess structure having the small source-gate resistance, the source-gate capacitance is small, the gate reverse breakdown voltage is high, the controllability of the gate length is good, and the MESFET without the step disconnection is realized. it can.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of the present invention in process order.

FIG. 2 is a cross-sectional view showing a second embodiment of the present invention in process order.

FIG. 3 is a graph showing the dependence of the cutoff frequency f _{T on} the recess-gate distance X.

FIG. 4 is a sectional view showing a conventional planar type field effect transistor.

FIG. 5 is a cross-sectional view showing a method for manufacturing a conventional recess type field effect transistor.

[Explanation of symbols]

1 semi-insulating GaAs substrate 2 non-doped GaAs buffer layer 3 N-type GaAs operating layer 4 insulating film 5 metal film 6 first resist 7, 7a, 7b, 7c, 7d second resist 8 gate electrode 9 source electrode 10 drain electrode L _g Gate length hν Wavelength 240 to 300 nm ultraviolet ray X Recess-gate distance

Claims (2)

[Claims] 1. A step of sequentially depositing an insulating film and a metal film on one main surface of a semiconductor substrate, and anisotropic etching of the metal film and the insulating film using the first resist as a mask, and then the insulating film. And forming a recess by etching the surface of the semiconductor substrate using the mask as a mask, and applying a second resist containing cyclopentane and 2- (2-methoxyethoxy) ethanol as a main component, and then irradiating with ultraviolet rays to develop the resist. And a step of depositing a gate metal on the entire surface and then etching the gate metal using a third resist covering a region immediately above the recess as a mask.
And a step of removing the insulating film and the second resist to form a gate electrode. 2. A step of sequentially depositing an insulating film and a metal film on one main surface of a semiconductor substrate, and anisotropic dry etching of the metal film and the insulating film using the first resist as a mask, and then the insulating film. Using the mask as a mask to form a recess by etching the surface of the semiconductor substrate, and applying a second resist containing cyclopentane and 2- (2-methoxyethoxy) ethanol as a main component, followed by anisotropic dry etching. Exposing the surface of the semiconductor substrate in the recess region, and etching the gate metal using a third resist as a mask after depositing the gate metal on the entire surface and then covering the area immediately above the recess.
And a step of removing the insulating film and the second resist to form a gate electrode.