JPH07335667A - Method for manufacturing semiconductor device - Google Patents

Abstract

PURPOSE:To perform the high accuracy and the high yield without generating an alignment deviation by simultaneously forming electrode patterns of a source, a drain and a gate. CONSTITUTION:After first resist patterns 10 for forming gate, source and drain electrodes 6, 3, 4 are simultaneously formed on a semiconductor active layer 2, second resist patterns 11 corresponding to the electrodes 3, 4 are formed on the patterns 10. Then, metal for the electrodes 3, 4 is vapor-deposited, and the electrodes 3, 4 are formed by a lifting-off method. Thereafter, a third resist pattern 12 corresponding to the upper shape of the T-shaped gate electrode 6 is formed on the pattern 10, metal for the gate electrode is vapor-deposited to form the gate 6 by the lifting-off method. For example, the resist 10 is insoluble in solvent to be used for the lifting-off method and not mixed with the resists 11, 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a T-type gate electrode.

[0002]

2. Description of the Related Art The structure of a conventional semiconductor device having a T-shaped gate electrode, for example, a MESFET (field effect transistor) using a compound semiconductor GaAs, and its manufacturing method will be described. FIG. 3 is a sectional view of a GaAs MESFET having a T-shaped gate electrode having a gate length Lg. As shown in the figure, in a GaAs MESFET, an n-GaAs layer 2 which is an active layer or an operating layer is formed on a semi-insulating GaAs substrate 1, and a source electrode 3 and a drain electrode 4 are formed on the n-GaAs layer 2. The T-type gate electrode 6 is provided on the recess 5 formed on a part of the surface of the n-GaAs layer 2 between the two.

In this GaAs MESFET, the n-GaAs under the T-type gate electrode 6 is controlled by the voltage applied to the T-type gate electrode 6.
A depletion layer spreads in the layer 2 and its thickness is changed to control the current flowing from the drain electrode 4 to the source electrode 3. The smaller the gate length Lg of the T-type gate electrode 6 is, the more excellent the low noise characteristic is in the high frequency region such as millimeter wave, and the higher efficiency and higher output can be achieved. Therefore, the gate length Lg of 0.2 μm or less is required. Is coming. Further, the source-drain distance (drain-gate distance Ldg + source-gate distance Lsg) must be 3 μm or less.
Furthermore, in order to reduce the source resistance Rs, an offset gate structure in which the source-gate distance Lsg is smaller than the drain-gate distance Ldg is also required.

4A to 4D are sectional views showing a method of manufacturing a conventional GaAs MESFET having the T-type gate electrode 6 shown in FIG. A conventional manufacturing method will be described with reference to FIG.

First, as shown in FIG. 4A, the semi-insulating property
An n-GaAs layer 2 which is an active layer or an operating layer is formed on the GaAa substrate 1 by an epitaxial growth method or the like.

Next, as shown in FIG. 4B, a photoresist is applied on the nGaAs layer 2 and a resist pattern 7 for forming a source electrode and a drain electrode is formed by an optical exposure method. At the same time, an alignment mark for the next process is also formed.

Next, as shown in FIG. 4 (c), AuGe / Ni / Au or the like is vapor-deposited using the resist pattern 7 as a mask, the source electrode 3 and the drain electrode 4 are formed by the lift-off method, and the GaAs layer is further formed. An alloy reaction is caused by an alloy method in order to form an ohmic contact with 2.

Next, as shown in FIG. 4 (d), an electron beam resist 8 having a relatively low sensitivity is applied as a lower layer, and an electron beam resist 9 having a relatively high sensitivity is applied thereon to form two layers. Form a resist structure.

Next, as shown in FIG. 4 (e), alignment is performed by the alignment mark formed in the previous step,
A resist pattern for a T-type gate electrode having a source-gate spacing Lsg of 1 μm, a drain-gate spacing Ldg of 1 μm, and a lower pattern dimension of 0.2 μm is formed by using an electron beam exposure method.

Next, as shown in FIG. 4F, the exposed portion of the n-GaAs layer 2 is etched using the resist 8 as a mask to form a recess 5.

Finally, after depositing Pt / Au, which is a metal for the gate electrode, on the entire surface, a lift-off method is used to form the structure shown in FIG.
As shown in, a GaAs MESFET having a T-shaped gate electrode 6 having a gate length Lg of 0.2 μm is formed.

[0012]

In the conventional method of manufacturing a semiconductor device, when the gate electrode is formed, the alignment mark formed at the same time as the resist pattern formation for forming the source and drain electrodes is used as described above. Misalignment occurs due to edge roughness (rattle) of metal generated by alloying when forming the source and drain electrodes. Since this misalignment occurs about 0.15 μm, the source-gate spacing Lsg and the drain-gate spacing Ldg cannot be formed as designed. Therefore, there is a problem that the manufacturing yield of the semiconductor device is significantly reduced.

Further, as a means for improving the performance of a semiconductor device, it is known that the source-gate distance Lsg is made smaller than the drain-gate distance Ldg in order to reduce the source resistance Rs. Since the method causes misalignment as described above, it is difficult to form the pattern of the T-shaped gate electrode as designed if the source-gate spacing Lsg is 0.4 μm or less because the resist film thickness changes greatly. There was also a problem.

The present invention has been made to solve the above problems, and by forming the source, drain, and gate electrode patterns at the same time, it is possible to achieve high precision and high accuracy without causing misalignment. An object of the present invention is to obtain a method for manufacturing a semiconductor device that can achieve a yield.

[0015]

A method of manufacturing a semiconductor device according to the present invention comprises a step of simultaneously forming a first resist pattern for forming gate, source and drain electrodes on an active layer, and a first resist pattern. A step of forming a second resist pattern corresponding to the source and drain electrodes, a step of depositing a metal for the source and drain electrodes and forming a source and a drain electrode by a lift-off method, a T-shaped gate on the first resist pattern The method includes a step of forming a third resist pattern corresponding to the shape of the electrode upper portion, a step of depositing a metal for a gate electrode and forming a T-type gate electrode by a lift-off method.

Further, in the method for manufacturing a semiconductor device according to the present invention, as the first resist, a resist which is insoluble in the solvent used in the lift-off method and which does not mix with the second and third resists is used. Is.

Further, in the method of manufacturing a semiconductor device according to the present invention, a step of simultaneously forming a first pattern made of an inorganic insulating film for forming gate, source and drain electrodes on the active layer, and the first pattern is formed. A step of forming a second resist pattern corresponding to the source and drain electrodes, a step of depositing a metal for the source and drain electrodes and forming the source and drain electrodes by a lift-off method, and a step of forming a T-type gate electrode on the first pattern. The method includes a step of forming a third resist pattern corresponding to the upper shape and a step of depositing a metal for a gate electrode and forming a T-type gate electrode by a lift-off method.

Further, the method for manufacturing a semiconductor device according to the present invention uses an image reversal type resist for forming the second and third resist patterns.

[0019]

In the method of manufacturing a semiconductor device according to the present invention, since the resist patterns for forming the gate, source and drain electrodes are formed at the same time and the above electrodes are formed in a self-aligned manner, the gate electrode and the source and drain electrodes are formed. Misalignment with the electrodes can be eliminated.

Since the first resist is insoluble in the solvent used for lift-off and does not mix with the second and third resists, the gate electrode and the source / drain electrode should be formed with high accuracy. You can

Further, since the first pattern for forming the gate, source and drain electrodes is formed of the inorganic insulating film, there is no room for the first pattern to mix with the resists of the second and third resist patterns. Instead, the gate electrode and the source / drain electrodes can be formed with high precision.

Further, since the image reversal resist is used as the resist corresponding to the upper shape of the T-shaped gate electrode, the overhang shape can be easily formed.

[0023]

【Example】

Example 1. A first embodiment of the present invention will be described with reference to FIG. 1A to 1D are cross-sectional views showing a method of manufacturing a semiconductor device of the present invention in the order of steps.

First, as shown in FIG. 1A, the semi-insulating property
The active layer 2 is formed on the GaAs substrate 1 by the epitaxial growth method. On top of this, a first resist 10 that does not dissolve in a solvent such as acetone in the subsequent lift-off process and does not mix with the image reversal resist used in the subsequent process, such as an electron beam, deep ultraviolet rays (DeepUV), or X-rays, is formed. A positive resist PMGI (polydimethylglutarimide) having a sensitivity of 0.2 μm is applied. After that, the pattern of the gate, source and drain electrodes is exposed by the electron beam 20, for example. The first resist 10 is not limited to the positive resist, and a negative resist may be used as long as it does not cause mixing with the image reversal resist used in the subsequent process.

Next, as shown in FIG. 1B, organic alkali development is performed to form a first resist pattern 10 for forming gate, source and drain electrodes.

Next, as shown in FIG. 1 (c), an image reversal resist (for example, AZ5214 manufactured by Hoechst Co., Ltd.) capable of obtaining an overhang shape is applied on the upper surface by 1 μm, and an optical exposure,
For example, i-line (365 nm) stepper exposure is performed to form a second resist pattern 11 corresponding to the source and drain electrodes.

Next, as shown in FIG. 1D, the source,
Ohmic metal for drain electrode, eg AuGe / Ni / Au, is deposited and lifted off with an organic solvent such as acetone,
The source electrode 3 and the drain electrode 4 are formed. In addition,
The first resist pattern 10 remains undissolved.

Next, as shown in FIG. 1 (e), an image reversal resist is applied again to a thickness of 1 μm, and optical exposure is performed to perform T
A third resist pattern 12 corresponding to the upper pattern of the mold gate electrode is formed.

Next, as shown in FIG. 1 (f), tartaric acid,
The exposed portion of the active layer 2 is etched with a phosphoric acid-based etching solution to form a recess 5.

Finally, as shown in FIG. 1G, a gate electrode 6 is formed by a lift-off method after depositing, for example, WSi as a gate electrode metal, and then a first resist pattern 10 is formed by O ₂ plasma ashing. Is removed, and FIG.
A semiconductor device having the structure shown in is obtained.

Example 2. In the method of Example 1, the source and drain electrodes are first formed, and then the gate electrode is formed. However, the order is reversed, the gate electrode is formed first, and then the source and drain electrodes are formed. However, the same semiconductor device can be obtained.

Example 3. 2A to 2D are sectional views showing a third embodiment of the present invention in the order of steps. First, as shown in FIG. 2A, the active layer 2 is formed by CVD (Chemical Vapor Deposition).
An inorganic insulating film 13, such as SiO ₂ , SiO ₂ or SiN, is formed to a thickness of 0.2 μm, and a resist 14 having excellent dry etching resistance, such as a novolac-based positive resist for EB exposure, is formed to a thickness of 0.5 μm. The electron beam 20 is used to expose a pattern corresponding to the gate, source and drain electrodes.

Next, as shown in FIG. 2B, organic alkali development is performed to form a pattern on the resist 14 corresponding to the gate, source and drain electrodes.

Next, as shown in FIG.
The insulating film 13 is etched by the reactive ion etching method using the pattern 14 as a mask to form a first pattern 15 made of an inorganic insulating film for forming gate, source and drain electrodes.

After that, by performing the same processes as those shown in FIG. 1C and subsequent drawings according to the first embodiment, the T-type gate electrode can be formed in a self-aligned manner. The first pattern 15 made of an inorganic insulating film may be left as it is, but if the increase in parasitic capacitance poses a problem, it is removed by hydrofluoric acid in the final step.

Example 4. Example 3 described above. First, the source and drain electrodes are formed, and then the gate electrode is formed. However, if the order is reversed, the gate electrode is formed first, and then the source and drain electrodes are formed. A semiconductor device can be obtained.

[0037]

Since the present invention is constructed as described above, it has the following effects.

Since the first resist pattern for forming the gate, source and drain electrodes is formed at the same time and the above respective electrodes are formed in a self-aligning manner, there is room for misalignment between the gate electrode and the source and drain electrodes. It is possible to form each of the above electrodes with high accuracy.

The resist used for forming the first resist pattern is insoluble in the solvent used for lift-off in the subsequent step, and does not mix with the resist used for forming the second and third resist patterns. The electrodes and the source / drain electrodes can be formed with higher accuracy.

Furthermore, since the first pattern for forming the gate, source and drain electrodes is formed of the inorganic insulating film, there is no room for the first pattern to mix with the resists of the second and third resist patterns. Instead, the gate electrode and the source / drain electrodes can be formed in a self-aligned manner with higher precision.

Further, since the image inversion resist is used as the resist of the third resist pattern corresponding to the upper shape of the T-shaped gate electrode, the overhang shape can be easily formed, and the shape of the T-shaped gate electrode can be formed with high accuracy. Can be formed.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention in the order of steps.

FIG. 2 is a sectional view showing another embodiment of the present invention in the order of steps.

FIG. 3 is a cross-sectional view of a semiconductor device having a T-type gate electrode.

FIG. 4 is a cross-sectional view showing a method of manufacturing a semiconductor device having a conventional T-type gate electrode in the order of steps.

[Explanation of symbols]

 1 semiconductor substrate 2 active layer 3 source electrode 4 drain electrode 6 gate electrode 10 first resist 11 second resist 12 third resist 13 inorganic insulating film 15 first pattern

Claims (4)

[Claims] 1. A step of simultaneously forming a first resist pattern for forming gate, source and drain electrodes on a semiconductor active layer, and a second resist corresponding to the source and drain electrodes on the first resist pattern. A step of forming a pattern, a step of depositing a metal for a source / drain electrode and forming a source / drain electrode by a lift-off method, and a third resist pattern corresponding to the upper shape of the T-shaped gate electrode on the first resist pattern. A method of manufacturing a semiconductor device, which includes a step of forming a gate electrode metal and a step of forming a T-type gate electrode by a lift-off method. 2. The semiconductor device according to claim 1, wherein the first resist is a resist which is insoluble in a solvent used for lift-off and which does not mix with the second and third resists. Production method. 3. A step of simultaneously forming a first pattern made of an inorganic insulating film for forming gate, source and drain electrodes on a semiconductor active layer, and a source and a drain on the first pattern made of the inorganic insulating film. A step of forming a second resist pattern corresponding to the electrodes, a step of depositing a metal for the source and drain electrodes and forming source and drain electrodes by a lift-off method, a T-shaped gate on the first pattern made of the inorganic insulating film A method of manufacturing a semiconductor device, comprising: a step of forming a third resist pattern corresponding to the upper shape of an electrode; and a step of depositing a metal for a gate electrode and forming a T-type gate electrode by a lift-off method. 4. The method of manufacturing a semiconductor device according to claim 1, wherein an image reversal type resist is used for forming the second and third resist patterns.