JPH0528105A - Data transfer method - Google Patents

Abstract

(57) [Abstract] [Purpose] Regarding a data transfer method in a line processing device that accommodates a plurality of communication lines and transfers transmission / reception data of each communication line to a common storage device, The purpose is to realize reliable and efficient data transfer. According to each input / output device 2, a buffer memory 200 for temporarily storing data transmitted / received by the input / output device to / from the communication line 1, and data transfer between the buffer memory and the input / output device are independent of each other. And a first data transfer unit 300 for executing the data transfer between the respective buffer memories and the common storage device 100, which is common to each input / output device, independently of each first data transfer unit. The second data transfer means 400 is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data in a line processing device which accommodates a plurality of communication lines and transfers data transmitted and received by each communication line to and from a storage device commonly provided in each communication line. Regarding transfer method.

[0002]

2. Description of the Related Art FIG. 3 is a diagram showing an example of a conventional line processing device. In FIG. 3, the line processing device includes a plurality of input / output devices (IO) 2, a main storage device (MM) 3 shared by the input / output devices (IO) 2, and a central processing unit (C).
PU) 4 and direct memory access controller (D
MC) 5 and a processor bus 6 for connecting between the respective devices
It consists of and.

Each input / output device (IO) 2 accommodates a communication line 1 and transmits / receives data to / from each accommodated communication line 1. The main memory device (MM) 3 stores data transmitted and received to and from the communication line 1 accommodated in each input / output device (IO) 2.

The central processing unit (CPU) 4 extracts data from the main storage device (MM) 3 via the processor bus 6 and also the main storage device (M) via the processor bus 6.
M) Store data in 3.

Further, the direct memory access control device (DMC) 5 receives data received by the input / output device (IO) 2 from the communication line 1 via the processor bus 6 under the control of the central processing unit (CPU) 4. The main memory (M
M) 3 is transferred / stored in the I / O device (IO) 2 and transmitted from the main memory device (MM) 3 by the input / output device (IO) 2 to the communication line 1.
O) Transfer to 2.

The central processing unit (CPU) 4 and the direct memory access control unit (DMC) 5 transfer data to and from the main memory unit (MM) 3 via a processor bus 6 provided in common. Since it does, it is impossible to perform multiple data transfers at the same time.

Therefore, the central processing unit (CPU) 4 is executing data transfer with the main storage device (MM) 3, or the direct memory access control device (DMC) 5 is optional with the main storage device (MM) 3. During execution of data transfer with the input / output device (IO) 2, the data arriving from any other communication line 1 is discarded without being stored in the main memory device (MM) 3, resulting in a so-called overrun state. Further, while the central processing unit (CPU) 4 or the direct memory access control unit (DMC) 5 is executing the data transfer as described above, the data to be transmitted to any other communication line 1 is the main storage device (M
M) is not extracted from 3 and becomes a so-called underrun state.

[0008]

As is apparent from the above description, in the conventional line processing device, the data to be transmitted / received to / from a plurality of communication lines are directly memory-accessed in common to each communication line 1. Controller (DM
Since C) 5 is transferred via the processor bus 6 provided in common, an overrun state of received data from each communication line 1 and an underrun state of transmitted data to each communication line 1 occur. There was a problem that reliable and efficient data transfer could not be executed.

The present invention is reliable for a plurality of communication lines,
It is also intended to realize efficient data transfer.

[0010]

FIG. 1 is a diagram showing the principle of the present invention. In FIG. 1, 1 is a plurality of communication lines accommodated in the line processing device, 2 is a plurality of input / output devices that accommodate each communication line 1 and send / receive data to / from the accommodated communication line 1, and 100 is each communication It is a common storage device which is provided in common to the line 1 and stores the data transmitted / received to / from each communication line 1 in common.

Reference numeral 200 is a buffer memory provided corresponding to each input / output device 2 according to the present invention. 300 is
The first data transfer means is provided corresponding to each input / output device 2 according to the present invention.

Reference numeral 400 is a second data transfer means commonly provided to each input / output device 2 according to the present invention.

[0013]

The buffer memory 200 temporarily stores the data transmitted / received by the input / output device 2 to / from the communication line 1.

The first data transfer means 300 executes data transfer between the buffer memory 200 and the input / output device 2 independently of each other. The second data transfer means 400 executes data transfer between each buffer memory 200 and the common storage device 100 independently of each first data transfer means 300.

Therefore, the data arriving from each communication line can be stored in the corresponding buffer memory independently of the other communication lines, and the data to be transmitted to each communication line is
Since it can be extracted from the buffer memory that corresponds to other communication lines independently, the overrun state of the received data and the underrun state of the transmitted data do not occur, and reliable and highly efficient data transfer to the communication line is realized. It will be possible.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a diagram showing a line processing device according to an embodiment of the present invention. The same reference numerals denote the same objects throughout the drawings.

In FIG. 2, a main storage device (MM) 3 is shown as the common storage device 100 in FIG. 1, and a buffer memory (BM) 7 is provided as the buffer memory 200 in FIG. 1 for each input / output device (IO) 2. 1, a direct memory access control device (DMC) 8 is provided corresponding to each input / output device (IO) 2 as the first data transfer means 300 in FIG. The central processing unit (CPU) 4 as the data transfer means 400 and the gate buffer (GB) 10 provided corresponding to each input / output device (IO) 2 play their roles.

Each buffer memory (BM) 7, direct memory access controller (DMC) 8 and gate buffer (GB) 10 are connected via an input / output bus 9, and each input / output bus 9 is connected to a gate. It is connected to the processor bus 6 via a buffer (GB) 10.

The central processing unit (CPU) 4 extracts each required data from the main memory device (MM) 3 or accumulates the required data in the main memory device (MM) 3, for example, each gate buffer. The (GB) 10 is set in the shut-off state to separate each input / output bus 9 from the processor bus 6.

In this state, each input / output device (IO) 2
Upon receiving the data arriving from each of the accommodated communication lines 1, each of them activates the corresponding direct memory access control device (DMC) 8 and requests the transfer / storage of the received data.

The activated direct memory access control device (DMC) 8 transfers / stores the data received by the input / output device (IO) 2 into the corresponding buffer memory (BM) 7 via the input / output bus 9. To do.

Each input / output bus 9 is the processor bus 6
Since it is independent of the other input / output bus 9, the direct memory access control device (DMC) 8 transfers data independently of the central processing unit (CPU) 4 and other direct memory access control device (DMC) 8. Can be executed.

When the received data is accumulated in the buffer memory (BM) 7, the direct memory access control device (D
The MC) 8 requests the central processing unit (CPU) 4 to transfer the received data accumulated in the buffer memory (BM) 7 to the main storage device (MM) 3.

The central processing unit (CPU) 4 having received the data transfer request, the gate buffer (GB) corresponding to the direct memory access control unit (DMC) 8 of the request source.
After setting 10 to the conductive state, the buffer memory (BM)
The received data accumulated in 7 is extracted and passed through the input / output bus 9, the gate buffer (GB) 10 set to the conductive state, and the processor bus 6 to the main memory device (MM) 3
After storing the data in the main memory device (MM) 3 and storing it in the main memory device (MM) 3, the gate buffer (GB) 10 is set to the cutoff state again.

In the meantime, the gate buffer (GB) 10 other than the gate buffer (GB) 10 corresponding to the direct memory access control device (DMC) 8 which is the source of the data transfer request.
The other direct memory access control devices (DMCs) 8 are connected to the corresponding input / output device (IO) 2 and buffer memory (BM) 7 because they are continuously set to the cutoff state.
Data can be transferred between and via the dedicated input / output bus 9.

Further, when it becomes necessary for each input / output device (IO) 2 to transmit data to the communication line 1 accommodated therein,
The corresponding direct memory access controller (DMC) 8 is activated to request extraction / transfer of transmission data.

The activated direct memory access control device (DMC) 8 receives the buffer memory (B) when transmission data is stored in the buffer memory (BM) 7.
M) extracts transmission data from M and transfers it to the input / output device (IO) 2 via the input / output bus 9.

When no transmission data is stored in the buffer memory (BM) 7, the direct memory access control device (DMC) 8 has the central processing unit (CPU) 4
Is requested to transfer the transmission data accumulated in the main memory (MM) 3.

The central processing unit (CPU) 4 which has received the data transfer request, the gate buffer (GB) corresponding to the direct memory access control unit (DMC) 8 of the request source.
After setting 10 to the conductive state, the transmission data accumulated in the main memory device (MM) 3 is extracted and passed through the processor bus 6, the gate buffer (GB) 10 and the input / output bus 9 which are set to the conductive state. Buffer memory (BM) 7
After being transferred to the buffer memory (BM) 7 and accumulated in the buffer memory (BM) 7,
The gate buffer (GB) 10 is set to the cutoff state again.

In the meantime, the gate buffer (GB) 10 other than the gate buffer (GB) 10 corresponding to the direct memory access control device (DMC) 8 which is the source of the data transfer request.
The other direct memory access control devices (DMCs) 8 are connected to the corresponding input / output device (IO) 2 and buffer memory (BM) 7 because they are continuously set to the cutoff state.
Data can be transferred between and via the dedicated input / output bus 9.

Direct memory access control device (DM
The C) 8 transfers the transmission data stored in the buffer memory (BM) 7 to the input / output device (IO) 2 as described above. As is clear from the above description, according to this embodiment,
Communication line 1 corresponding to each input / output device (IO) 2
Data sent to and received from the direct memory access control device (DMC) provided correspondingly.
8 dedicated input / output bus 9
Independent of the transfer of transmission / reception data to / from another communication line 1 or the data transfer between the central processing unit (CPU) 4 and the main storage device (MM) 3 with the buffer memory (BM) 7 via the Therefore, the overrun of the reception data from the communication line 1 or the underrun of the transmission data to the communication line 1 is prevented.

It is to be noted that FIG. 2 is merely an embodiment of the present invention, and for example, the first data transfer means 300 and the second data transfer means 400 are the direct memory access controller (DMC) 8 and Central processing unit (CP
The present invention is not limited to U) 4 and the like, and many other modifications can be considered, but in any case, the effect of the present invention does not change. It goes without saying that the line processing device which is the subject of the present invention is not limited to the one shown in the figure.

[0033]

As described above, according to the present invention, in the line processing device, the data arriving from each communication line can be stored in the buffer memory independently corresponding to the other communication lines and can be transmitted to each communication line. Since the data to be extracted can be extracted from the buffer memory that corresponds to other communication lines independently, the overrun state of the received data and the underrun state of the transmitted data do not occur, and the communication line is reliable and highly efficient. Data transfer can be realized.

[Brief description of drawings]

FIG. 1 is a diagram showing the principle of the present invention.

FIG. 2 is a diagram showing a line processing device according to an embodiment of the present invention.

FIG. 3 is a diagram showing an example of a conventional line processing device.

[Explanation of symbols]

 1 Communication Line 2 Input / Output Device (IO) 3 Main Memory Device (MM) 4 Central Processing Unit (CPU) 5, 8 Direct Memory Access Control Device (DMC) 6 Processor Bus 7,200 Buffer Memory (BM) 9 Input / Output Bus 10 Gate Buffer (GB) 100 Common Storage Device 300 First Data Transfer Means 400 Second Data Transfer Means

Claims (1)

Claims: 1. A plurality of input / output devices (2), each accommodating a communication line (1), transmitting and receiving data to and from the communication line (1), and each communication line (1). ), A common storage device (10) for commonly storing the data transmitted and received.
0) and a buffer memory for temporarily accumulating data to be transmitted / received to / from the communication line (1) by the input / output device (2) corresponding to each of the input / output devices (2). (200), the buffer memory (200), and the input / output device (2)
A first data transfer means (300) for independently performing data transfer between the buffer memory (200) and the common storage device (200) is provided commonly to the input / output devices (2). A data transfer method, characterized in that a second data transfer means (400) is provided for performing data transfer with the first data transfer means (300) independently of each other.