JPH0535661A - SCSI controller IC - Google Patents

Abstract

(57) [Summary] [Purpose] If the processing of the first command of two commands issued consecutively ends normally, the normal end report to the CPU is omitted. [Structure] A command FIFO (6, 7) stores two commands issued continuously by the CPU. The sequencer (8) processes the first command, stores the normal end code in the status register (16), and outputs the normal end interrupt setting signal (20). At this time, since the command display bit (14) indicating that there is a command to be processed remains set, the normal end interrupt setting signal is suppressed by the AND gate (19) and the interrupt signal (13) is No output. On the other hand, at the end of the processing of the second command, since the command display bit (14) is reset, the interrupt signal (13) is output to the CPU. [Effect] When the processing of the first command of the two commands issued consecutively ends normally, the interrupt signal for notifying the CPU of the end of command execution can be suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to SCSI (Small Computer Sys) in an information processing system.
SC used to control the tem Interface)
The present invention relates to the SI controller IC.

[0002]

2. Description of the Related Art Conventionally, SCSI has been widely used as an interface between devices in a small-scale information processing system.

The SCSI is an SCS composed of a control bus consisting of nine control lines and a data bus consisting of nine data lines.
It is a parallel interface for transmitting and receiving data using the I bus. Also, up to eight devices can be connected to the SCSI bus.

It is S to control the SCSI data transmission between the devices connected to the SCSI bus.
It is a CSI controller.

Such a SCSI controller is
It is often supplied as an IC such as SI.

[0006] Here, the conventional SCSI controller LS
The configuration of I is shown in FIG.

In the figure, 1 is an internal bus on the CPU side, 2 is an SCS
The I-side internal bus, 3 is a CPU connection bus connected to the CPU, and 4 is a SCSI bus.

Reference numeral 5 temporarily stores transfer data, and C
A data FIFO (First in First Out) memory that adjusts the data transfer rate between the PU bus and the SCSI bus.

Reference numerals 6 and 7 denote SCSs set by the CPU.
Command FIFO for storing up to two I control commands
Is. Further, among them, 6 is a first-stage FIFO for storing a command currently being executed, and 7 is a second-stage FIFO for storing a command in a command execution waiting state.

Reference numeral 8 is a sequencer for controlling the SCSI bus in accordance with the command stored in the command FIFO 6.

Further, 9 and 10 are status FIFOs for storing up to two command execution results of the sequencer 8. Also, 9 of them is the first-stage FIFO,
Reference numeral 10 is a second stage FIFO.

Numerals 11 and 12 are status FIFOs, respectively.
The interrupt bits included in O9 and O10 are shown.

Reference numeral 13 is an interrupt signal to the CPU.

Hereinafter, this conventional SCSI controller L
The operation of SI will be described.

FIG. 6 shows a conventional SCSI controller LS.
3 shows the operation timing of I.

As shown in the figure, the command 1 is written in the first stage 6 of the command FIFO by the CPU. Then, the next command 2 from the CPU is the command FIFO
It is written in the second row 7.

The sequencer 8 processes the command 1 written in the first stage 6 of the command FIFO. When the processing is completed, the command 1 is added to the first stage 9 of the status FIFO.
Stores the end status of command FIFO 2nd stage 7
The command 2 stored in the command FIFO is loaded into the first stage 6 of the command FIFO. Then, the processing of the command 2 written in the first stage 6 of the command FIFO is started.

On the other hand, when the sequencer 8 stores the end status 1 of the command 1 in the first stage 9 of the status FIFO, the interrupt signal 13 is output to the CPU.

When the sequencer 8 finishes processing the command 2, it stores the end status of the command 2 in the second stage 10 of the status FIFO.

Upon receiving the interrupt signal 13, the CPU receives the status FI in order to know the execution result of the issued command 1.
When the command 1 end status stored in the first FO 9 is read, the command 2 end status stored in the second status FIFO 10 is changed to the status FI.
It is loaded in the first stage 9 of the FO.

When the command 2 end status is loaded in the first stage 9 of the status FIFO, the interrupt signal 13 to the CPU is output again.

The CPU receiving the second interrupt signal 13 reads the command 2 end status stored in the first stage 9 of the status FIFO in order to know the execution result of the issued command 2.

When command 1 ends abnormally, sequencer 8 issues an abnormal end interrupt to the CPU when command 1 ends abnormally, and command 2 is automatically cleared.

Table 1 shows an example of commands issued by the CPU to the SCSI controller LSI. In the table, the middle column is the command, and the right column is the operation specified by the command.

[0025]

[Table 1]

Next, taking a sequence in which the initiator issues a read command to the target and receives data from the target, the SCSI controller LSI is exemplified.
The operation will be described when it is applied as a SCSI adapter of the initiator.

As shown in FIG. 4, in this sequence, the phases transit to a bus free phase, an arbitration phase, a selection phase, a message out phase, a command phase, a message in phase, and a bus free phase.

As shown in the figure, the CPU firstly outputs the data F
Write transmission data such as read command data to be transmitted to the target in the IFO5, and Select With shown in Table 1
The ATN Sequence command and the Transfer Information command are issued to the SCSI controller LSI.

Then, the sequencer 8 of the SCSI controller LSI executes the Select With ATN Sequence command, controls the SCSI bus, and executes the arbitration phase, the selection phase, the message out phase, and the command phase.

Command phase ends, ACK / 40
When negating 1 signal, the sequencer 8
A code indicating normal termination is output to the IFO first stage 9, "1" is set in the interrupt bit 11, and the interrupt signal 13 is set to C.
Output to PU. Next, the sequencer 8 of the conventional example executes the Transfer Information command 200, receives 1 byte in the message in phase, and receives ACK /
With the signal asserted, a code indicating normal termination is output to the second stage 10 of the status FIFO, and interrupt bit 1
Set "1" to 2.

When the CPU reads the normal end status of the Select With ATN Sequence command, the status FI
The normal status of the Transfer Information command stored in the FO second stage 10 is the status FIFO first stage 9
Loaded in. Also, the interrupt bit 12 is loaded into the interrupt bit 11 and the interrupt signal 13 is sent to the CPU.
Output again.

Next, when the CPU reads the normal status of the Transfer Information command, the status FI
The values of the first FO 9 and the interrupt bit 11 are cleared and the interrupt signal 13 is negated.

Next, the CPU reads the input data stored in the data FIFO received in the message in phase, and ACK / 401 in the message in phase.
A Message Accepted command for clearing and a Transfer Information command 200 for receiving the next 1 byte. Sequencer 8 uses Message Accept
Execute ed command, negate ACK / 401, RE
When Q / 402 is asserted by the target, a code indicating normal termination is output to the first stage 9 of the status FIFO, "1" is set in the interrupt bit 11, and the interrupt signal 13 is output to the CPU.

Next, the sequencer 8 transfers Transfer Inform.
ation command is executed and 1 in the message in phase
In the state where the byte is received and the ACK / signal 401 is asserted, a code indicating a normal end is output to the second stage 10 of the status FIFO, and "1" is set in the interrupt bit 12.

When the CPU reads the normal end status of the Message Accepted command, the normal status of the Transfer Information command stored in the second stage 10 of the status FIFO is loaded in the first stage 9 of the status FIFO. The value of interrupt bit 12 is interrupt bit 1
1 and re-output the interrupt signal 13 to the CPU.

Next, when the CPU reads the normal status of the Transfer Information command, the status FIFO
The values of the O1 stage 9 and the interrupt bit 11 are cleared and the interrupt signal 13 is negated. The CPU further issues a Message Accepted command to clear the ACK / signal 401 of the message in phase.

The sequencer 8 executes the Message Accepted command, negates ACK /, and when BSY / is negated by the target, the status FIFO first stage 9
A code indicating normal termination is output to, the interrupt bit 11 is set to "1", and the interrupt signal 13 is output to the CPU.

When the CPU reads the normal end status of the Message Accepted command and confirms the normal end, the values of the status FIFO first stage 9 and the interrupt bit 11 are cleared and the interrupt signal 13 is negated.

As described above, the SCSI controller LSI
The SCSI control sequence is generally specified by the CPU by a combination of versatile commands. If a command is provided for each SCSI operation sequence,
Since the number of command types becomes enormous, the operation sequence is specified by a combination of a small number of versatile commands.

Each command in the above-mentioned table is also used in combination with another command to realize a plurality of different SCSI control sequences.

As described above, in the case of using the conventional SCSI controller, the CPU receives the read command in order to realize the sequence for receiving the data and receiving the data from the target. Five interrupt processes must be executed corresponding to the five interrupts.

[0042]

As described above, the conventional S
According to the CSI controller, in order to specify the SCSI control sequence by the combination of commands, the execution completion status of the command is reported to the CPU by an interrupt in response to each command. Therefore, in the SCSI protocol processing of the CPU, there is a problem that the overhead due to the interrupt processing is large.

On the other hand, if the SCSI control sequence is to be specified by one command, the number of command types increases and the sequencer for processing this becomes complicated.

Therefore, according to the present invention, it is possible to reduce the overhead in the SCSI protocol processing of the CPU due to the report of the execution completion status of the command from the SCSI controller without increasing the number of command types. The purpose is to provide a SCSI controller IC.

[0045]

[Means for Solving the Problems] To achieve the above object,
The present invention is a SCSI controller IC for executing a plurality of commands given from the outside and sequentially controlling a SCSI bus, and a command storing means capable of storing two or more given commands, and the command storing means. Command processing means for sequentially executing the commands in the order in which the commands are stored in the means, execution result reporting means for externally reporting the execution completion state of the command when the command processing means has finished executing the command, and the command processing means Determination means for determining whether or not the executed command is the last command stored in the command storage means, and the command executed by the command processing means by the determination means is not the last command stored in the command storage means If it is determined that the execution end status of the command executed by the command processing means is Providing La IC - when was normally finished, SCSI controller, characterized in that it comprises a reporting inhibiting means for inhibiting reporting to outside of the execution completion status of the command as the command processing means executes.

[0046]

According to the SCSI controller IC of the present invention, the report prohibiting means determines that the determining means determines that the command executed by the command processing means is not the last command stored in the command storing means. If there is, and the execution end state of the command executed by the command processing means is normal end, the execution end state of the command executed by the command processing means is suppressed from being reported to the outside.

That is, when the execution of the command is completed normally, the command other than the command given last among the two or more commands stored in the command storage means is not reported as normal completion, Only the command given last is reported as a normal end. On the other hand, when the execution of the command ends abnormally, the abnormal end is always reported.

[0048]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The SCSI controller LS according to the present invention is described below.
A practical example of I will be described.

First, FIG. 3 shows the configuration of an information processing system adopting SCSI.

In the figure, 310, 320, 330, 340,
Reference numerals 350, 360, 370 and 380 are devices such as computers, disk drives and printers, and 390 is a SCSI bus. In addition, 311, 321, 331, 341, 351, 361 in each device,
Reference numerals 371 and 381 are SCSI controller LSIs according to this embodiment.

Computer devices 310 and 32
0 and 330 operate as an initiator on SCSI,
Other devices 340, 350, 360, 370, 3
80 operates as a target on SCSI. Each SCS
The I controller LSI controls the SCSI bus to enable data transmission using the SCSI bus of each device.

Next, the SCSI controller according to the present embodiment will be described.
The configuration of the LaLSI is shown in FIG.

In the figure, 1 is an internal bus on the CPU side, 2 is an SCS
I side internal bus, 3 is CPU bus, 4 is SCSI bus, 5
Is a data FIFO, 6 is a first stage of the command FIFO, 7 is a second stage of the command FIFO, 8 is a sequencer, and 13 is an interrupt signal.

Reference numeral 14 is a command presence display bit indicating whether or not a command exists in the second stage of the command FIFO, and reference numeral 15 indicates that the end of the first command is a normal end, and at the end, the second command is the command FIFO. If present, it is an intermediate interrupt prohibition bit that prohibits the output of an interrupt due to the end of the command.

Reference numeral 16 is a status register for holding the end state of the command executed by the sequencer 8. The status register 16 operates as a separate status register when the intermediate interrupt prohibition bit 15 is set, but when the intermediate interrupt prohibition bit 15 is not set, the SCSI according to the prior art described above is used.
Status FIFO of controller LSI (see FIG. 5)
As the first stage 9, it works as a part of the status FIFO together with the second stage 10 (not shown).

Reference numeral 17 is an interrupt bit for holding an interrupt, 1
Reference numeral 8 is a NAND gate, 19 is an AND gate, 20 is a normal end interrupt set signal, and 21 is an abnormal end interrupt set signal.

Next, the SCSI controller according to the present embodiment will be described.
The operation of the LaLSI will be described.

If the intermediate interrupt prohibition bit 15 is not set, the SCSI controller LS according to the present embodiment.
I operates in the same manner as the above-mentioned conventional SCSI controller LSI. At this time, the status register 1
As described above, 6 is the status FIFO first stage 9 of the SCSI controller LSI (see FIG. 5) according to the prior art, and the status FIFO second stage 10 (not shown).
Also works as part of the Status FIFO.

When the intermediate interrupt prohibition bit 15 is set, the operation is performed at the operation timing shown in FIG.

That is, as shown in the figure, command 1
Is written in the first stage 6 of the command FIFO by the CPU. Then, the next command 2 from the CPU is written in the second stage 7 of the command FIFO. When the command is written in the second stage 7 of the command FIFO, the command presence indicating bit 14 is set.

The sequencer 8 processes the command 1 written in the first stage 6 of the command FIFO. When the processing is completed, the end status of the command 1 is stored in the status register 16 and the normal end interrupt set signal 20
To issue. At this time, even if the end status of the command 1 is stored in the status register 16, the normal end interrupt signal 20 is suppressed and the interrupt bit 17 is not set by the command presence display bit 14 and the intermediate interrupt prohibition bit 15. .

Next, the sequencer 8 outputs the command FIFO.
The command 2 stored in the second row 7 is replaced by the command FIF
Load to the 1st stage of O6. And the command FIFO1
The processing of the command 2 written in the stage 6 is started. When the command FIFO second stage 7 becomes empty, the command presence display bit 14 is cleared.

After finishing the processing of the command 2, the sequencer 8 stores the normal end status of the command 2 in the status register 16 and issues the normal end interrupt set signal 20.

When the command 2 processing is completed and the command 2 completion status is loaded to the status register 16, the command presence display bit 14 is cleared, so the normal completion interrupt set signal 20 is Not inhibited, therefore the interrupt bit 17 is set and the interrupt signal 13 to the CPU is output.

The CPU receiving the interrupt signal 13 reads out the command 2 end status stored in the first stage 9 of the status register in order to know the execution result of the issued command 2.

If the command ends abnormally,
When the command ends abnormally, the sequencer 8 issues an abnormal end interrupt to the CPU and automatically clears the command. Since the setting 21 of the interrupt bit at abnormal end is not suppressed by the command presence display bit 14 and the intermediate interrupt prohibition bit 15, the interrupt signal 13 is output even when the command 1 ends abnormally. Therefore, the CPU can perform abnormal processing.

The conventional SCS is described below in the section of the prior art.
The initiator used in the operation of the I controller LSI is the initiator which issues a read command to the target and receives data from the target.
The operation of the SCSI controller LSI applied as the SCSI adapter of the computer will be described.

As described above, in this sequence, the phases are bass free phase, arbitration phase, selection phase, message out phase, command phase, message phase. -, The bus-free phase, and the signals on the SCSI bus transit as shown in FIG.

Also in this embodiment, the commands shown in Table 1 in the above-mentioned prior art are used.

In order to realize the sequence shown in FIG. 4, the CPU performs the operation indicated by 410 in FIG.

That is, first, the CPU determines the intermediate interrupt inhibit bit 1 of the SCSI controller LSI (see FIG. 1).
5 is set, the read command data to be transmitted by the message out phase and the command phase are written in the data FIFO 5, and the Select With ATN Sequence command and Transfer Information command are issued.

On the other hand, in the SCSI controller LSI, the Select With ATN Sequence command issued by the CPU is stored in the first stage 6 of the command FIFO, and the Transfer I
The nformation command is stored in the second stage 7 of the command FIFO. When the command is stored in the second stage 7 of the command FIFO, 1 is set in the command presence display bit 14.

The sequencer 8 executes the Select With ATN Sequence command stored in the first stage 6 of the command FIFO and controls the SCSI bus to arbitration phase, selection phase, message out phase.
Execute the command phase.

The sequencer 8 negates the ACK / signal 401 upon completion of the command phase and selects With
Terminates processing of the ATN Sequence command. Then, a code indicating normal termination is output to the status register 16,
The normal termination interrupt set signal 20 is output as a pulse.

Here, since the intermediate interrupt prohibition bit 15 is set in advance by the CPU, both the command presence display bit 14 and the intermediate interrupt prohibition bit 15 are 1. Therefore, the output of the NAND gate 18 is
The output of AND gate 19 does not become active.

Therefore, the interrupt bit 17 is not set to "1" and the interrupt signal 13 is not output.

Next, the Transfer Information command stored in the second stage 7 of the command FIFO is loaded into the first stage 6 of the command FIFO.

Since there are no commands in the second stage 7 of the command FIFO, the command presence display bit 14 is cleared to "0". Therefore, the output of the NAND gate 18 becomes "1".

The sequencer 8 is loaded in the first stage 6 of the FIFO.
When the transferred Transfer Information command is executed and one byte of data is received by the message inphase, this data is stored in the data FIFO 5, and the ACK / signal 4
The processing of the Transfer Information command is terminated with 01 being asserted. Then, a code indicating a normal end is output to the status register 16 and a normal end interrupt set signal is pulsed.

At this time, as described above, the NAND gate is
Since the output of the gate 18 is 1, the AND gate 19
Is 1, the interrupt bit 17 is set to "1", and the interrupt signal 13 is output.

The CPU which has received the interrupt by the interrupt signal 13 reads the value of the status register 16 and confirms the normal end. When the CPU reads the value of the status register 16, the value of the interrupt bit 17 is cleared and the interrupt signal 13 is negated.

The CPU then reads the value of the data FIFO 5 and issues a Message Accepted command in order to clear the ACK / of the message inphase. Also, in order to receive 1 byte of the next data, Tr
Issue the ansfer Information command.

On the other hand, in the SCSI controller LSI, the Message Accepted command issued by the CPU is stored in the first stage 6 of the command FIFO, and the Transfer Informati
The on command is stored in the second stage 7 of the command FIFO.
When the command is stored in the second stage 7 of the command FIFO, 1 is set in the command presence display bit 14.

The sequencer 8 executes the Message Accepted command stored in the first stage 6 of the command FIFO and executes AC.
When K / 401 is negated and REQ / 402 is asserted by the target, a code indicating normal termination is output to the status register 16 and a normal termination interrupt set signal 20 is output as a pulse. .

At this time, the intermediate interrupt prohibition bit 15 is set, and Transfer I is set in the second stage of the command FIFO.
Since the nformation command is stored, the interrupt signal 13 is not output.

On the other hand, the Transfer Information command stored in the second stage 7 of the command FIFO is the command F
It is loaded to the first stage 6 of the IFO.

Since there are no commands in the second stage 7 of the command FIFO, the command presence display bit 14 is cleared to "0". Therefore, the output of the NAND gate 18 becomes "1".

In the same way as the processing of the Transfer Information command, the sequencer 8 uses the FIFO first stage 6
When the Transfer Information command loaded into the memory is executed and one byte of data is received by the message inphase, this data is stored in the data FIFO 5 and ACK is sent.
/ Transfer Information with signal 401 asserted
Terminates command processing. Then, a code indicating a normal end is output to the status register 16 and a normal end interrupt set signal is pulsed.

At this time, as described above, the NAND gate is
Since the output of the gate 18 is 1, the AND gate 19
Is 1, the interrupt bit 17 is set to "1", and the interrupt signal 13 is output.

The CPU which has received the interrupt by the interrupt signal 13 reads the value of the status register 16 and confirms that it is normally completed. When the CPU reads the value of the status register 16, the value of the interrupt bit 17 is cleared and the interrupt signal 13 is negated.

Then, the CPU reads out the value of the data FIFO 5 received by the message inphase.

Further, the CPU issues a Message Accepted command to clear ACK / of the message inphase.

On the other hand, in the SCSI controller LSI, the Message Accepted command issued by the CPU is stored in the first stage 6 of the command FIFO.

The sequencer 8 executes the Message Accepted command stored in the first stage 6 of the command FIFO and executes AC.
When K / 401 is negated and BSY / 403 is negated by the target, the code indicating normal termination is output and the normal termination interrupt set signal 20 is output in pulses.

At this time, since the command is not stored in the second stage of the command FIFO, the output of the NAND gate 18 is 1, so that the output of the AND gate 19 is 1 and the interrupt bit 17 has "1". ｀ is set, and the interrupt signal 13 is output.

Upon receipt of this interrupt, the CPU receives Message Ac
Read the normal end status of the cepted command and confirm the normal end. When the normal termination status is read out,
The status register and interrupt bit 17 values are cleared and interrupt signal 13 is negated.

If the command ends abnormally,
When the command 1 ends abnormally, the sequencer 8 generates an interrupt set signal 21 at the time of abnormal end, sets an interrupt bit, generates an interrupt to the CPU, and outputs the command FIF.
The command of the second stage 7 is automatically cleared. Abnormal end interrupt set signal 21 is command existence indication bit 14
Since it is not suppressed by the intermediate interrupt prohibition bit 15, the interrupt signal 13 is output even if the command ends abnormally. Therefore, the CPU can perform the abnormal processing for all the issued commands.

The above is the SCSI controller LSI according to the present embodiment. This is a sequence operation in which the initiator issues a read command to the target and receives data from the target. And, as explained above,
According to this embodiment, the CPU realizes this sequence only by performing interrupt processing three times. This is less than the CPU interrupt processing frequency of 5 required in the above-described conventional technique. Further, in this embodiment, the same command as the above-mentioned conventional technique is used as the command.

As described above, according to this embodiment, the CPU
If the processing of the first command of the two commands issued in succession is completed normally, the report of normal completion is omitted and the information of the normal completion of the processing of the first command is 2
It is included in the completion report of the processing of the second command. For this reason, the number of interrupt processings of the CPU is reduced, and the overhead of the CPU due to the interrupt from the SCSI controller can be reduced. On the other hand, if the command processing ends abnormally, even if it is the first command processing,
By reporting this, the CPU can be processed abnormally.

This is because when the CPU continuously issues a plurality of commands as in the above-mentioned sequence,
Due to the normal termination of the processing of the first command, the CPU
It is assumed that there are few cases where processing that should be performed occurs.

On the other hand, according to the present embodiment, since the intermediate interrupt prohibition bit designating the omission of the report of the normal end of the first command can be set from the outside, the normal processing of the first command can be performed. If there is a process to be performed by the CPU due to the end, it is possible to perform the normal end report of the process of the first command without omitting it.

In the present embodiment, the SCSI controller LSI has set the number of commands that can be continuously received at two to two, but the number of commands that can be continuously received at once is three or more. You may In this case, the number of stages of the command FIFO that stores the command issued by the CPU is increased according to the number of commands that can be accepted, and the commands other than the last command accepted are
The command received at the beginning in the description of the embodiment is processed in the same manner, and the command received at the end is processed in the same way as the processing of the command received second in the description of the embodiment. Good.

Further, this embodiment is based on the SCSI controller L.
Although the SI has been described, other peripheral I that executes the process based on the command issued by the CPU and reports the process result
The same applies to C as well.

[0104]

As described above, according to the present invention, it is possible to increase the number of command types without increasing the number of command types, which is caused by the report of the command execution end state from the SCSI controller in the CPU's SCSI protocol processing. It is possible to provide a SCSI controller IC capable of reducing the bar head.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a SCSI controller according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the SCSI controller according to the embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of an information processing system according to an embodiment of the present invention.

FIG. 4 is a timing chart showing the relationship between an example of the sequence of the SCSI bus and the processing of the CPU.

FIG. 5 is a block diagram showing a configuration of a SCSI controller according to a conventional technique.

FIG. 6 is a timing chart showing the operation of the SCSI controller according to the prior art.

[Explanation of symbols]

1 CPU side internal bus 2 SCSI side internal bus 3 CPU connection bus, 4 SCSI bus 5 data FIFO 6 First-stage command FIFO 7 Second stage command FIFO 8 sequencer 9 First-stage status FIFO 10 Second stage status FIFO 11 interrupt bits 12 interrupt bits 13 Interrupt signal 14 Command existence display bit 15 Intermediate interrupt disable bit 16 Status Register 17 interrupt bits 18 NAND gate 19 AND Gate 20 Normal end interrupt set signal 21 Abnormal end interrupt set signal

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Kunio Watanabe             292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Ceremony Hitachi Microelectronics             Device Development Laboratory (72) Inventor Koji Shida             Gunma Prefecture Takasaki City Nishi-Yokote-cho 111 Address Co., Ltd.             Within Hitachi Semiconductor Design Development Center

Claims (8)

[Claims] 1. A SCSI controller IC for executing a plurality of commands given from the outside and sequentially controlling a SCSI bus, the command storage means being capable of storing two or more given commands, and the command. Command processing means for sequentially executing the commands in the order in which the commands are stored in the storage means;
Determining means for determining whether or not the command executed by the command processing means is the command last stored in the command storing means, and the command executed by the command processing means by the judging means is finally stored in the command storing means. If it is determined that the command is not a stored command, and
And a report prohibiting unit that suppresses an external report of the execution end state of the command executed by the command processing unit when the execution end state of the command executed by the command processing unit is normal end. SCSI
Controller IC. 2. The SCSI controller IC according to claim 1.
The command storage means is a FIFO memory capable of storing a plurality of commands, and the determination means is configured to execute the FI at the end of command execution by the command processing means.
By determining whether or not there is an unexecuted command in the FO memory, it is determined whether or not the command executed by the command processing means is the last command stored in the command storage means. A SCSI controller IC that does. 3. The SCSI controller IC according to claim 1.
A SCSI control means for controlling whether or not to suppress the report of the execution completion state of the command by the report prohibiting means to the outside based on an external setting. -La IC. 4. The SCSI control IC according to claim 3.
An externally settable report suppression register for storing designation of whether or not to suppress the report of the execution end state of the command by the report prohibiting means is provided, and the report suppression control means Controls the suppression of the external report of the command execution end state by the report prohibiting means based on the setting contents of the report suppression register.
CSI controller IC. 5. The SCSI controller IC according to claim 1.
The execution result reporting means includes a status register for storing the execution end state of the command, and stores the execution end state of the command in the status register to output an interrupt signal to the outside. Thereby, the execution end state of the command is reported to the outside, and the report prohibiting means reports the execution end state of the command of the execution result reporting means to the outside by suppressing the output of the interrupt signal to the outside. A SCSI controller IC characterized by suppressing the above. 6. A peripheral IC for executing a command given by a CPU, the command storing means capable of storing two or more commands given by the CPU, and the command storing means sequentially storing the commands in order. Command processing means for executing a command, execution result reporting means for externally reporting the execution completion state of the command when the command processing means has finished executing the command, and the command executed by the command processing means is the command storage means at the end. Determining means for determining whether or not the command is stored in the command storing means, and the determining means determines that the command executed by the command processing means is not the last command stored in the command storing means, and If the execution end status of the command executed by the command processing means is normal end, the command A peripheral IC, comprising: a report prohibiting unit that suppresses the external report of the execution end state of the command executed by the command processing unit. 7. The peripheral IC according to claim 6, wherein a report for controlling whether or not to suppress the report of the execution end state of the command by the report prohibiting means to the outside based on the setting from the outside. A peripheral IC, characterized by having a deterrent control means. 8. The S according to claim 1, which controls a SCSI bus.
And a CPU for issuing a command to the SCSI controller IC and utilizing the control of the SCSI bus by the SCSI controller IC to perform data transmission using the SCSI bus. Information processing system.