JPH054090U - Snooze alarm clock - Google Patents

Abstract

(57) [Summary] [Purpose] The effect of the wake-up alarm is increased by advancing the display time according to the snooze operation during the alarm alarm. [Structure] An alarm clock with snooze is provided with a constant pulse output circuit that advances the display time by a certain time by operating the snooze switch at the time of alarm warning. Display the time advanced. Alternatively, the display time is set as the last alarm occurrence time.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a snooze alarm clock, and more particularly to a timepiece display that can change the time display according to the operation of a snooze switch when an alarm occurs.

[0002]

[Prior Art]

 In the conventional alarm clock with snooze, an alarm is generated at a set time, and after a certain period of time has elapsed by the snooze switch operation, the alarm is generated again to warn the wake-up time. However, after the temporary stop operation, he fell asleep again and was late for the appointed time. In order to prevent such a situation, alarm clocks have been provided in which the alarm volume is sequentially increased according to the number of snooze operations or the alarm generation time.

[0003]

[Problems to be solved by the device]

 However, all of the above-mentioned conventional methods are audible alarms, and there are times when there is enough time to wake up, or when you set your wake-up alarm so that you wake up earlier than usual, you may fall asleep. It was The invention of the present application focuses on such a point, and an object thereof is to prevent a person from oversleeping by visually giving a warning by changing the time display to wait for an alarm again by snooze operation.

[0004]

[Means for Solving the Problems]

 In order to achieve the above object, the present invention counts the reference signal and displays the time, generates an alarm at the set time, and after the operation of the snooze switch for instructing the alarm suspension, the alarm is reactivated after a certain period of time. The alarm clock with snooze that is generated is characterized in that it is provided with a constant pulse number output circuit that advances the display time by a predetermined time according to the operation of the snooze switch when an alarm occurs.

[0005]

[Action]

 When an alarm sounds at the set time and the snooze switch is operated, the alarm sound is stopped and a step pulse for a certain period of time is input to the timekeeping section. When the snooze pause period elapses and an alarm is generated again to check the time, the time display will be a display time that is a certain time ahead of the actual time, and if the snooze switch is operated again, the display time will be a further time ahead. Then, the time is displayed twice as many times as the snooze switch has been operated, and is displayed. By permanently stopping the sound with the alarm set switch, the display time is displayed according to the true current time and the time stored in the timekeeping.

[0006]

【Example】

 FIG. 1 shows an embodiment of a digital timepiece according to the present invention, in which reference numeral 20 is a clock circuit, a reference signal generating circuit comprising an oscillator 2 and a frequency divider 4, and a clock signal for counting the reference signal. It comprises a counter 6, an OR gate 8, a presettable counter 10, a decoder 12, and a display unit 14.

An alarm circuit 50 includes a coincidence circuit 22, an alarm memory 24 for storing an alarm set time, an inverter 26, a one-shot circuit 28, two AND gates 30 and 32, and two OR gates 34. , 36, a flip-flop (hereinafter referred to as F F) 38, and a sounding circuit 40.

A snooze circuit 60 is composed of two AND gates 62 and 64, two one-shot circuits 66 and 68, and a counter 70. A constant pulse number output circuit 80 is composed of two FFs 72 and 73, an AND gate 74, an inverter 76, and a counter 78.

In the operation of the snooze alarm clock having the above-mentioned configuration, when the time of the clock counter 6 and the alarm memory 24 match when the alarm set switch 82 is in the ON state, the one-shot signal from the matching circuit causes the AND gate 30 and the OR gate. It is input to the C input terminal of the FF 38 via 36. In synchronization with this rising, the Q output becomes H level, and the sounding circuit 40 issues an alarm. At this time, the clock counter 6 and the preset counter 10 indicate the same time.

When the snooze switch 84 is pushed one time after an alarm is generated, the counter 70 operates via the AND gate 62 and the one-shot circuit 68, and the FF 38 is reset to stop the sound generation. On the other hand, the counter 70 operates the sounding circuit again via the one-shot circuit 66 after a fixed time, and sets the Q output of the FF 72 to H level so that the pulse passing through the AND gate 74 is kept until the counter 78 counts a fixed number of pulses. By being sent to the preset counter 10, the display time is advanced by a fixed time.

After that, when the snooze switch is operated, the above-mentioned operation is repeated, and the display time is advanced by a fixed time that is twice the number of times the snooze switch is operated. When the alarm sound is stopped by turning off the alarm set switch 82 while the alarm sound is being generated again, the preset counter 10 is switched to the current time display by presetting the current time of the clock counter 6. The constant pulse number output circuit may be operated by operating the snooze switch, and may be operated when the snooze switch is operated a certain number of times or more.

FIG. 2 shows a second embodiment, which is an example used for an analog timepiece. When the standard is turned on while the alarm switch 82 is in the on state, the Q output of the FF 118 is set to the H level through the AND gate 108 and the OR gate 114, and the sounding circuit 120 produces an alarm sound. At this time, the counter 132 is reset and is in a state of counting the number of operations of the snooze switch.

After that, the alarm sound is stopped by operating the snooze switch 84, and the counter 128 starts operating. Further, the counter 132 is incremented. When the snooze switch is operated a predetermined number of times, the counter 132 counts up and the AND gate 134 is opened. By the subsequent operation of the snooze switch, a fixed number of pulses are sent to the pointer counter 86 and the drive circuit 88, and the advanced time is displayed.

When the alarm set switch 82 is turned off, the inversion Q of the FF 148 that directs a direction via the AND gate 146 which is opened by the FF 144 that stores the time correction by the output from the AND gate 134 is set to L. The FFs 170 and 172 are reset by the H level signal of the Q output by setting the level to invert and the FFs 170 and 172 are further reset, and the stepping pulse is output through the OR gate 152, the FFs 162 and 164. Correct the reverse rotation.

When the time counting counter and the pointer counter 86 match, the output of the matching circuit 100 becomes H level. As a result, the Q output of the FF 170 becomes the H level and the pulse output is stopped via the OR gate 150. However, the second constant pulse number output circuit including the FFs 174 and 176, the AND gate 178, the inverter 180, and the counter 182 provides a fixed number of pulses. After the stepping, the carry signal of the counter 82 restores the normal rotation, and the AND gate outputs the normal rotation high-speed correction signal.

After that, when the time counter and the pointer counter match, the Q output of the FF 172 becomes H level, and normal hand movement is resumed. The second constant pulse output circuit may be used as a delay circuit so that the high speed correction pulse is not stopped by the Q output of the FF 170. In addition, the current time display may be provided separately without using the alarm set switch, or by operating the snooze switch when the alarm set switch is off.

Although the display time is advanced in proportion to the number of snooze operations in each of the first and second embodiments, the final alarm time is displayed by the first snooze switch operation and waiting for stop (for example, 20 minutes). Later). During this period, the snooze operation can be performed every predetermined time, and the display time is the last alarm time, and the operation is stopped. By repeating the snooze operation several times, when the current time and the display time match, the alarm sound is made different from the normal alarm and the current time display is started at the display time.

In the above operation, the AND gates 134 and 130 and the counter 132 in FIG. 2 are deleted, and instead the output of the AND gate 124 is connected to the S input of the FF with RS and the output of the one-shot circuit 104 is connected to the R input. If an AND gate that blocks the normal drive signal is provided in front of the OR gate 98 when the Q output of the FF 144 is H, and the alarm set switch is on between the matching circuit 100 and the FF 170 and the Q output of the FF 144 is H. When a coincidence signal occurs, the signal is inverted and input to the AND gate 124 to invalidate the snooze switch and input to the sounding circuit and the OR gate 114 as a signal to increase the volume, and further reset the FF144 and FF148. Return to normal hand movement, and the alarm switch is off and the Q output of FF144 is high. It is possible to provide a gate circuit so that when a coincidence signal occurs, it is input to the C input terminal of the FF 170 to correct the current time display.

[0019]

[Effect of the device]

 As described above, according to the present invention, the display time is advanced in response to the operation of the snooze switch, so that the wake-up alarm can be further strengthened.

[Brief description of drawings]

FIG. 1 shows an embodiment according to the present invention.

FIG. 2 is an embodiment of an analog timepiece according to the invention.

[Explanation of symbols]

 20 Clock circuit 50 Alarm circuit 60 Snooze circuit 80 Constant pulse number output circuit

Claims (1)

[Claims for utility model registration] [Claim 1] The reference signal is counted to display the time, an alarm is generated at the set time, and the alarm is re-issued after a certain time has elapsed after the snooze switch for instructing the alarm suspension is operated. In the snooze alarm clock, the snooze alarm clock is provided with a constant pulse number output circuit that advances the display time by a predetermined time according to the operation of the snooze switch when an alarm occurs.