JPH0562786B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In a system in which a plurality of I/O devices are controlled by a microcomputer, there is provided a means for setting a unique address for hardware in addition to an address decoding circuit for a normal I/O address space. By providing means for dynamically selecting the unique address using software, a large number of I/O devices can be connected to the same address in the I/O address space.

[Industrial application field]

The present invention relates to an I/O address decoding method for decoding addresses assigned to I/O devices in microcomputer systems used, for example, in terminal devices for financial institutions.

[Conventional technology]

FIG. 4 shows an example of the conventional method.

Many optional I/O (input/output) devices can be connected to recent terminal devices for financial institutions, and these I/O devices are controlled by the microcomputer built into the terminal device. It is becoming more and more like this.

Each I/O device has a unique address in the I/O address space, and as shown in Figure 4, the address output by the microcomputer is
It is decoded by the address decoder 30 of each device and used as an I/O chip select signal.

[Problem that the invention seeks to solve]

There is no problem when the number of I/O devices connected to the system, such as terminal devices, is small, but as the number of I/O devices connected increases, the I/O address space becomes insufficient, so the address area A problem has arisen in that the I/O devices that can be connected are limited due to the lack of I/O devices. The address space can be expanded by increasing the number of bits of the address signal in the address bus, but expansion of the address bus is difficult because it involves major modification of the hardware.

The present invention aims to solve the above-mentioned problems and provides a means for substantially increasing the I/O allocation space by adding a simple circuit to the address decoding section of each I/O device. .

[Means for solving problems]

FIG. 1 shows a principle block diagram of the I/O address decoding method of the present invention.

In FIG. 1, 10 is a fixed address decoding circuit that decodes the upper bits of the address allocated to the I/O address space, and 11 is the same I/O address decoding circuit.
Each I/O allocated to a range of O address space
A software register in which a value for selecting a device group is dynamically set; 12 is a hardware-specific address in which a different setting value is set for each I/O device group allocated to the same I/O address space range; A setting section 13 is a comparator 14 that compares the contents of the software register 11 and the setting value of the hardware specific address setting section 12.
is an AND circuit that takes the AND of the output of the fixed address decoding circuit 10 and the output of the comparator 13;
15 represents an address bus, and 16 represents a data bus.

Fixed address decoding circuit 10
This circuit decodes a predetermined number of upper bits of the address of the I/O device allocated to the O address space, and outputs "1" when the addresses match.

In the case of the present invention, there are multiple I/O addresses within the range of the I/O address space represented by the upper bits of the address.
In order to redundantly allocate O device groups, a hardware-specific address setting section 12 using, for example, a dip switch is provided. A value for distinguishing groups of I/O devices assigned to the duplicate addresses is set in the hardware specific address setting section 12 when the I/O devices are installed.

When selecting an I/O device to be used by the software that operates the microcomputer, it selects the I/O device group via the data bus 16 before sending out the address in the I/O address space. The allocation number, that is, the value held by the hardware specific address setting unit 12 is written into the software register 11. When the value held by the hardware specific address setting section 12 is set in the software register 11, the output of the comparator 13 becomes "1".

Thereafter, when the I/O device is accessed via the address bus 15 as in the conventional case, the decoding result by the fixed address decoding circuit 10 and the output of the comparator 13 are both "1", so the AND circuit 14 The output of is "1". By using this as an I/O group select signal that selects an I/O device group, desired I/O
You will be able to access the device.

[Effect]

FIG. 2 is a diagram for explaining the operation of the present invention.

For example, consider an I/O address space from address 1000 (hexadecimal) to address 10FF. I/O device A
For the groups 1, A2, . . . , the setting value of the hardware specific address setting section 12 shown in FIG. 1 is set to "00" in advance. I/O devices B1, B2,...
For the group, the setting value of the hardware specific address setting section 12 is set to "01". Furthermore, for the other groups of I/O devices C1, C2, . . . , the setting value of the hardware specific address setting section 12 is set to "02". In addition, I/O of the same group
Devices (A1, A2,...), (B1, B2,...), (C
It is assumed that the addresses (1, C2, . . . ) do not overlap within the group.

If “00” is written to software register 11 by software, 10FF will be written from address 1000.
I/O devices A1 and A
Groups 2, . . . will be selected. Furthermore, if "01" is written in the software register 11, the group of I/O devices B1, B2, . . . is selected. Similarly, by "02", I/O device C
Groups 1, C2, . . . are selected.

As described above, since addresses from 1000 to 10FF can be multiplexed and used, the space to which I/O addresses can be allocated can be expanded without expanding the address bus.

〔Example〕

FIG. 3 shows an embodiment of the invention.

In FIG. 3, 10A and 10B are upper address decoders, which correspond to the fixed address decoding circuit 10 shown in FIG. 11
A and 11B are software registers 11 shown in FIG. Also, 13A, 13B and 14
A and 14B correspond to the comparator 13 and the AND circuit 14 shown in FIG. 1, respectively.

20A and 20B are I/O address decoding circuits provided for each I/O device or each group of I/O devices. Address decoders 21A and 21B decode addresses assigned to software registers 11A and 11B. Reference numerals 22A and 22B are deep switches, which correspond to the hardware specific address setting section 12 shown in FIG.

23A, 24A and 23B, 24B are lower address decoders that decode lower bits of the address bus 15, respectively.

The dip switch 22A is set, for example, to always output a value of "00" when connecting an I/O device having the I/O address decoding circuit 20A. On the other hand, "01" is set in the deep switch 22B.

Software register 11A and software register 11B have the same address.
That is, address decoder 21A and address decoder 21B decode the same address.

A microcomputer (not shown) connects the software register 11 via the address bus 15.
Specify the addresses of A and 11B and connect the data bus 16.
Writing “00” through comparator 13
The output of A becomes "1". Also, if you specify that address and write “01”, comparator 1
The output of 3A becomes “0” and comparator 13B
The output of is switched to "1".

Upper address decoders 10A and 10B each decode the upper 8 bits of address bus 15 in the same way, but since the outputs of comparators 13A and 13B are different, the outputs of AND circuits 14A and 14B will never both become "1". .

When the output of the AND circuit 14A becomes "1", the lower address decoders 23A and 24A decode, for example, the lower 8 bits of the address bus 15, and identify the internal I/O addresses, respectively.

When the output of the AND circuit 14B becomes "1", the lower address decoders 23B and 24B input the I/
Each internal I/O address belonging to the O address decoding circuit 20B is identified.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to allocate a plurality of different I/O devices to the same I/O address space by adding a simple circuit. This can solve the problem of limited connectivity.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram of the present invention, FIG. 2 is an explanatory diagram of the operation of the present invention, and FIG. 3 is an embodiment of the present invention.
FIG. 4 shows an example of the conventional method. In the figure, 10 is a fixed address decoding circuit, 11
is a software register, 12 is a hardware specific address setting section, 13 is a comparator, 14
15 represents an AND circuit, 15 represents an address bus, and 16 represents a data bus.

Claims (1)

[Claims] 1. In a system in which a plurality of I/O devices are controlled by a microcomputer, hardware in which different setting values are set for each group of I/O devices allocated to the same I/O address space range. Unique address setting means 12
And, the above I/O is performed by the above microcomputer.
A software register 11 in which values corresponding to different setting values for each device group are dynamically set via a data bus, and a setting value held by the hardware-specific address setting means 12 and the software register. 1
Comparator 13 that compares with the value set to 1
and a fixed address decoding circuit 10 that decodes addresses allocated to the range of the I/O address space, and based on the comparison result by the comparator 13 and the decoding result by the fixed address decoding circuit 10, the I/O device An I/O device address decoding method comprising: means 14 for outputting a signal for selecting one of the I/O device addresses.