JPS6324343A - I/o address decoding system - Google Patents

Abstract

PURPOSE:To connect many I/O devices to the same address in an I/O address space by providing a means for setting an intrinsic address of a hardware, and a means for selecting dynamically its intrinsic address by a software. CONSTITUTION:An intrinsic address decoding circuit 10 decodes an address of an I/O device which has been allocated to the prescribed I/O address space. In order to overlap and allocate plural I/O devices to its same I/O address spaces, a hardware intrinsic address setting part 12 is provided. To the setting part 12, a value for discriminating the I/O device which has been allocated to its overlapped address is set at the time of installing the I/O device. In case of selecting the I/O device to be used, the value held by the setting part 12 is written in a software use register 11 through a data bus 16 before sending out an address in its I/O address space. Thereafter, an access is executed to its I/O device, and by an output of an AND circuit 14, an access can be executed to a desired I/O device.

Description

[Detailed Description of the Invention] [Summary] In a system in which a plurality of I10 devices are controlled by a microcomputer, in addition to an address decoding circuit for a normal I10 address space, a means for setting a unique address of hardware and software, By providing a means to dynamically select the unique address, I1
0 address space, many I1
0 devices can be connected.

[Industrial application field]

The present invention relates to an I10 address decoding method for decoding an address assigned to an I/O device in a microcomputer system used in a terminal device, etc. for financial institutions, for example.

[Conventional technology]

FIG. 4 shows an example of the conventional method.

Recently, many optional I/O (input/output) devices can be connected to terminal devices for financial institutions.
These I10 devices are designed to be serviced by a microcomputer incorporated in the terminal device.

Each I10 device has a unique address in the I10 address space, and as shown in FIG. 4, the address output by the microcomputer is decoded by the address decoder 30 of each I10 device and used as a signal such as I10 chip select.

[Problem that the invention seeks to solve]

There is no problem when the number of I10 devices connected to the system such as terminal devices is small, but as the number of I/O devices increases, the I/O address space becomes insufficient.
A problem has arisen in that the I/O devices that can be connected are limited due to a lack of address space. The address space can be expanded by increasing the number of bits of the address signal in the address bus, but expansion of the address bus is difficult because it involves major modification of the hardware.

The present invention aims to solve the above problems, and provides a simple circuit for each I1.
By adding to the address decoding part of the 0 device, the I/O allocation is essentially intended to provide a means of increasing space.

[Means for solving problems]

FIG. 1 shows a principle block diagram of the I10 address decoding method of the present invention.

In FIG. 1, 10 is a fixed address decoding circuit that decodes addresses allocated to the I10 address space, and 11 is a value that is dynamically set to select each I/O device allocated to the same I/○ address space. A software register, 12 a hardware-specific address setting section in which a different setting value is set for each I10 device allocated to the same I10 address space, 13 a setting for the contents of the software register 11 and the hardware-specific address setting section 12 A comparator that compares the value.

Reference numeral 14 represents an AND circuit that performs a logical product of the output of the fixed address decode circuit 10 and the output of the comparator 13, 15 represents an address bus, and 16 represents a data bus.

The fixed address decoding circuit 10 is a circuit that decodes the address of the I10 device allocated to a predetermined I/O address space, and outputs "1" when the address fails once. It may be considered that this corresponds to the conventional address decoder 30 shown in FIG.

In the case of the present invention, in that same I10 address space.

To redundantly allocate multiple ■/○ devices.

For example, a hardware-specific address setting section 12 using a dip switch or the like is provided. A value for distinguishing between I10 devices assigned to the duplicated address is sent to the hardware specific address setting unit 12 when the I/O device is installed.

When selecting the I10 device to be used by the software that operates the microcomputer, select the I10 device to be used.
Before sending out an address in the address space, the I10 device's allocation number, ie, the value held by the hardware-specific address setting section 12, is written into the software register 11 via the data bus 16. When the value held by the hardware specific address setting unit 12 is set in the software register 11, the comparator 1
The output of 3 becomes "1".

Thereafter, via the address bus 15 as in the conventional case.

When the I10 device is accessed, both the decoding result by the fixed address decoding circuit 10 and the output of the comparator 13 are "1".

The output of the AND circuit 14 becomes "1". By using this as an I/O chip select signal, etc.

This allows access to the desired I10 device.

[Effect]

FIG. 2 is a diagram for explaining the present invention in detail.

For example, consider the I10 address space from address 1000 (hexadecimal) to loFF address. I10 device AI, A
2. . . , set the setting value of the hardware-specific address setting section 12 shown in FIG.
shall be. I10 device Bl.

B2. . . , the setting value of the hardware specific address setting section 12 is set to "01".

In addition, for other groups of I10 devices C1, C2, ..., the setting value of the hardware specific address setting section 12 is set to 02''.
l, A2. ), (Bl, B2゜...),
It is assumed that each address (C1, C2, . . . ) does not overlap within the group.

The software register “
If you write "00", the group of I/O devices AI, A2, etc. will be selected for the addresses from address 1000 to loFF address. Also, write "01" to the software register 11. For example, I10 device B
l, B2. The group of... is selected. Similarly, “0”
2'' selects the group of I10 devices CI, C2, .

As described above, since addresses from 1000 to loFF can be multiplexed and used, the space to which I10 addresses can be allocated can be substantially expanded without expanding the address bus.

〔Example〕

FIG. 3 shows an embodiment of the invention.

In FIG. 3, IOA and IOB are upper address decoders, which are the fixed address decoding circuit 1 shown in FIG.
It corresponds to 0. 11A.

11B is a software register 11 shown in FIG. 13A, 13B and 14A, 14B are the comparator 13 and the AND circuit 14 shown in FIG. 1, respectively.
corresponds to

20A and 20B are I10 address decoding circuits provided for each I10 device or for each group of I10 devices. 21A and 21B are software registers II
This is an address decoder that decodes the address assigned to A and IIB. 22A and 22B are dip switches.

This corresponds to the hardware-specific address setting section 12 shown in FIG.

23A, 24A and 23B, 24B are lower address decoders that decode lower bits of the address bus 15, respectively.

The dip switch 22A is set to always output a value of 1, for example, "00" when an I10 device having the I10 address decoding circuit 20A is connected. On the other hand, "01" is set in the dip inch 22B.

Software register IIA and software register 11B have the same address.

That is, address decoder 21A, address decoder 21
B decodes the same address.

A microcomputer (not shown) has an address bus 1
5 specifies the address of the software registers 11A and IIB and writes "00" via the data bus 16, the output to the comparator 13 becomes "11". ”, the output of the comparator 13A becomes “0” and the output of the comparator 13B switches to “1”.

The upper address decoders IOA and IOB each decode the upper 8 bits of the address bus 15 in the same way.
Since the outputs of the comparators 13A and 13B are different, the outputs of the AND circuits 14A and 14B will never both become "1".

When the output of the AND circuit 14A becomes "1".

The lower address decoders 23A and 24A decode, for example, the lower 8 bits of the address bus 15.

Identify each internal I10 address.

The lower address decoders 23B and 24B are the AND circuit 1
When the output of 4B becomes "1", each internal I10 address belonging to the I10 address decoding circuit 20B is identified.

〔Effect of the invention〕

As explained above, according to the present invention, a plurality of different I10 devices can be allocated to the same I10 address space by adding a simple circuit, so device connections are restricted due to lack of address area. It is possible to solve the problem of

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is an explanatory diagram of the operation of the present invention, and FIG. 3 is an embodiment of the present invention. FIG. 4 shows an example of the conventional method. In the figure, 10 is a fixed address decoding circuit, 11 is a software register, 12 is a hardware specific address setting section, 13 is a comparator, 14 is an AND circuit, 15 is an address bus, and 16 is a data bus. Patent Applicant Fujitsu Ltd. Sub-Agent Patent Attorney Yoshiyoshi Ogasawara 1 Address (2 addresses) 2 ni Miyabi 6th month Rii l'￥: Kata l talkative box 'J52 [!
1 1 to 4 country

Claims (1)

[Claims] In a system in which a plurality of I/O devices are controlled by a microcomputer, a hardware-specific address setting in which different setting values are set for each I/O device allocated to the same I/O address space. means (12); a software register (11) to which values corresponding to different settings for each I/O device are dynamically set by the microcomputer; and hardware-specific address setting means (12). a comparator (13) that compares the set value held by the software with the value set in the software register (11); and a fixed address decode circuit (10) that decodes the address allocated to the I/O address space. , means (14) for outputting a signal for selecting one of the I/O devices based on the comparison result by the comparator (13) and the decoding result by the fixed address decoding circuit (10). Features I/O address decoding method.