JPH056665Y2 - - Google Patents
Info
- Publication number
- JPH056665Y2 JPH056665Y2 JP16300585U JP16300585U JPH056665Y2 JP H056665 Y2 JPH056665 Y2 JP H056665Y2 JP 16300585 U JP16300585 U JP 16300585U JP 16300585 U JP16300585 U JP 16300585U JP H056665 Y2 JPH056665 Y2 JP H056665Y2
- Authority
- JP
- Japan
- Prior art keywords
- electronic components
- soldering
- stack
- electronic component
- dimension
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000005476 soldering Methods 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 4
- 238000003780 insertion Methods 0.000 claims description 2
- 230000037431 insertion Effects 0.000 claims description 2
- 239000002184 metal Substances 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 12
- 125000006850 spacer group Chemical group 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 235000014676 Phragmites communis Nutrition 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【考案の詳細な説明】
〔産業上の利用分野〕
本考案はスタツク型電子部品の半田揚治具に関
するものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a soldering jig for stack-type electronic components.
デユアルインライン型電子部品は、その殆んど
がスールホールを有するプリント回路配線基板へ
実装され、同時に上記配線基板に搭載される他の
電子部品と共に所望の回路を構成する。ところ
で、三次元的実装の観点から見ると、同時に搭載
される形状の大きい電子部品、例えばコンデン
サ、ボリユーム等と上記デユアルインライン型電
子部品とを比較した場合、デユアルインライン型
電子部品は空間利用度が劣る。
Most of the dual-in-line type electronic components are mounted on a printed circuit wiring board having through holes, and at the same time constitute a desired circuit together with other electronic components mounted on the wiring board. By the way, from the perspective of three-dimensional packaging, when comparing the dual-in-line type electronic components with large-sized electronic components such as capacitors and volumes that are mounted at the same time, the dual-in-line type electronic components have less space utilization. Inferior.
この点に鑑みて、三次元的実装空間をより有効
に使用する為、一般的にはデユアルインライン型
電子部品を積み重ねて電気リードのオーバーラツ
プ部を半田付けする方式がとられており、例えば
デユアルインライン型集積回路ではスタツクIC
と呼ばれている。この型のICでもプリント基板
に実装する際の半田付性を高める為に端子部に
は、一般的に半田デツピングによるメツキ処理が
施される。 In view of this, in order to use the three-dimensional mounting space more effectively, a method is generally used in which dual-in-line type electronic components are stacked and the overlapping parts of the electrical leads are soldered. Stack IC in type integrated circuit
It is called. Even with this type of IC, the terminals are generally plated with solder to improve solderability when mounted on a printed circuit board.
この処理を半田揚と称し、これを第5図に基い
て説明する。即ち、従来スタツクICの半田揚に
おいては、同図に示す如くマグネツト内蔵型の半
田揚治具1に前もつて予備半田された上部IC3
及び下部IC4をスペーサ5を介して、所望の寸
法範囲内に積み重ねた状態で搭載する。ここで、
2は上記半田揚治具中に装着されたマグネツトで
ある。 This process is called soldering, and will be explained based on FIG. 5. That is, in the conventional soldering of stacked ICs, as shown in the figure, the upper IC 3, which has been pre-soldered, is placed in a soldering jig 1 with a built-in magnet.
and the lower IC 4 are mounted via the spacer 5 in a stacked state within a desired size range. here,
2 is a magnet installed in the soldering jig.
そして、下方に配置される半田揚装置6を矢印
の如く上下動させ、上部IC3及び下部IC4の電
気リードオーバーラツプ部8を溶融半田7にデイ
ツプさせる事により、この電気リードオーバーラ
ツプ部8を半田付けし、スタツク化を実現してい
る。 Then, by moving the soldering device 6 disposed below up and down as shown by the arrow, the electrical lead overlap portions 8 of the upper IC 3 and the lower IC 4 are dipped in the molten solder 7. are soldered to realize stacking.
しかしながら、IC等のデユアルインライン型
電子部品をスタツク化する為に上記従来の半田揚
治具を用いる場合、例えばICにおいては、予め
上部及び下部ICを所望の寸法に積み重ねる作業
と、半田揚治具に搭載する作業の2工程を必要と
し作業能率が悪いという問題点があつた。
However, when using the conventional soldering jig to stack dual-in-line electronic components such as ICs, for example, in the case of ICs, it is necessary to stack the upper and lower ICs to the desired dimensions in advance, and to use the soldering jig. The problem was that it required two steps, one for loading the machine, and the work was inefficient.
従つて本考案は、以上述べた問題を解消し、上
部及び下部電子部品の積み重ね作業と半田揚治具
への搭載作業とを同時に完了出来るという作業性
に優れたスタツク型電子部品の半田揚治具を提供
する事を目的とする。 Therefore, the present invention solves the above-mentioned problems and provides a soldering process for stack-type electronic components that has excellent workability by allowing stacking of upper and lower electronic components and mounting on a soldering jig to be completed at the same time. The purpose is to provide tools.
本考案に係るスタツク型電子部品の半田揚治具
は、上記電子部品の本体が挿着されるよう長さ方
向を横切る方向に形成された多数の溝部と、上記
電子部品に搭載される上部の電子部品を保持する
と共に挿着位置と一致させるよう上記溝間の上側
縁部において対向して形成された多数の突起部と
を有する半田接合しない金属板を並列に多数連結
させるものである。
The soldering jig for stack type electronic components according to the present invention has a large number of grooves formed in a direction transverse to the length direction so that the main body of the electronic component is inserted, and an upper part to be mounted on the electronic component. A large number of non-solder metal plates are connected in parallel, each having a large number of protrusions facing each other at the upper edge between the grooves so as to hold the electronic components and align with the insertion position.
以上のように本考案を構成したので、デユアル
インライン型電子部品を搭載する場合、下部電子
部品は溝部に挿着固定され、また上部電子部品は
金属板の上側縁部にて対向して形成された突起部
により挿着案内されかつ保持される。この為、搭
載の位置決めが必然的になされると共に下部及び
上部電子部品の電気リードのずれを許容範囲内に
収める事が出来る。
With the present invention configured as described above, when dual in-line type electronic components are mounted, the lower electronic components are inserted and fixed in the groove, and the upper electronic components are formed facing each other at the upper edge of the metal plate. It is inserted, guided and held by the protrusion. Therefore, the mounting position can be determined naturally, and the misalignment of the electrical leads of the lower and upper electronic components can be kept within an allowable range.
以下、図に基いて本考案の一実施例を詳細に説
明する。まず第1図は、この実施例を示す概要図
である。同図において、1は半田接合しない金
属、例えばチタン材から成る金属板で、たわみが
発生せず十分厚みのあるものとする。そして上面
の側縁部には板状の突起部2が所定間隔を置き対
向して配設されており、またこれら突起部2間に
は所定深さの溝部3が形成されている。そして、
このような多数の突起部2及び溝部3の形成され
た金属板1を用いる事により、大量の電子部品を
一度に半田揚処理する事が出来る。上記金属板1
は、連結板4により多数並列に連結される。5は
側部支持棒で、半田揚装置のキヤリア部(図示せ
ず)に位置決めする穴6が加工されている。7は
半田揚装置のキヤリア部にセツトする際の取手
で、連結棒8により上記側部支持棒5と連結され
ている。
Hereinafter, one embodiment of the present invention will be described in detail based on the drawings. First, FIG. 1 is a schematic diagram showing this embodiment. In the figure, reference numeral 1 denotes a metal plate made of a metal that is not soldered, for example, titanium, and is sufficiently thick so that it does not bend. On the side edges of the upper surface, plate-shaped protrusions 2 are arranged facing each other at a predetermined interval, and a groove 3 of a predetermined depth is formed between these protrusions 2. and,
By using the metal plate 1 having such a large number of protrusions 2 and grooves 3, it is possible to solder a large number of electronic components at once. The above metal plate 1
are connected in parallel by a connecting plate 4. Reference numeral 5 denotes a side support rod, which is provided with a hole 6 for positioning it in a carrier section (not shown) of a soldering device. Reference numeral 7 denotes a handle for setting in the carrier section of the soldering device, and is connected to the side support rod 5 by a connecting rod 8.
第2図は、第1図の指示個所aを拡大し、IC
の搭載状況を示したものであり、第3図は第2図
cの搭載部断面図である。そして、第4図はスタ
ツクICの完成図である。以下、デユアルインラ
イン型電子部品としてICを例にとり、これら各
図に示されている寸法について説明する。 Figure 2 is an enlarged view of the indicated location a in Figure 1, and the IC
FIG. 3 is a sectional view of the mounting portion of FIG. 2c. Figure 4 is a diagram of the completed stack IC. Hereinafter, the dimensions shown in these figures will be explained using an IC as an example of a dual-in-line electronic component.
まず第2図aに示すA寸法は、上部IC13及
び下部IC14の両端電気リード間寸法、即ち第
4図に示すB寸法+0.1mm程度とする。また第2
図cのI寸法は、上部IC13と下部IC14のリ
ード間の位置ずれ防止の為、溝加工により第3図
のJ寸法より大きく形成されている。そして第2
図aのC寸法は、第3図のE寸法−0.1mm程度と
して、下部IC14の下面を溝部3に突き当てる
構造となるようにする。 First, the dimension A shown in FIG. 2a is the dimension between the electrical leads at both ends of the upper IC 13 and the lower IC 14, that is, the dimension B shown in FIG. 4 + about 0.1 mm. Also the second
The I dimension in FIG. c is made larger than the J dimension in FIG. 3 by groove machining in order to prevent misalignment between the leads of the upper IC 13 and lower IC 14. and the second
The C dimension in FIG. 3 is set to about 0.1 mm less than the E dimension in FIG. 3, so that the lower surface of the lower IC 14 abuts against the groove 3.
また第2図bのD寸法は、第4図に示す上部
IC13と下部IC14のパツケージ縦幅G寸法+
0.1mm程度とする。さらに第2図bのH寸法は、
搭載される上部IC13の上面と一致する程度と
し、これにより上部IC13と下部IC14の放熱
効果を高める事を目的とする0.3mm厚程度のスペ
ーサ15挿入案内、及び上部IC13の離脱防止
が図れる。同図aのJ寸法は、上記スペーサ15
を挿着される下部IC14の上面に密着させる為、
下部IC14の上面より低くする。また同図の9
は溝部3の逃げ加工部で、第4図にてbで指示す
るモールドバリに対拠する為と第4図Z寸法との
干渉をさける為に、両隅に加工されているもので
ある。 In addition, the D dimension in Figure 2b is the upper part shown in Figure 4.
Package vertical width G dimension of IC13 and lower IC14 +
It should be about 0.1mm. Furthermore, the H dimension in Fig. 2b is
The spacer 15 is designed to match the upper surface of the upper IC 13 to be mounted, and thereby the spacer 15 with a thickness of about 0.3 mm can be inserted and guided to enhance the heat dissipation effect between the upper IC 13 and the lower IC 14, and the upper IC 13 can be prevented from coming off. The J dimension in figure a is the spacer 15
In order to make it stick closely to the top surface of the lower IC 14 to be inserted,
Lower than the top surface of the lower IC14. Also, 9 in the same figure
4 is a relief part of the groove part 3, which is machined at both corners in order to counter the mold burr indicated by b in FIG. 4 and to avoid interference with the dimension Z in FIG. 4.
よつてICの搭載は、まず第2図aの如く金属
板1の各溝部3に夫々下部IC14を挿着し、そ
の上に同図bのようにスペーサ15を配し、次に
上部IC13を搭載する(同図c)という一連の
手順によつて行われる。ここで、金属板1を上述
したような構成とする為、下部IC14に上部IC
13を搭載するだけで、位置決めが必然的になさ
れる。そして、電気リードのオーバーラツプ部1
0を前述の如く半田処理することによつて、第4
図に示すスタツクICが得られる。 Therefore, to mount the IC, first insert the lower IC 14 into each groove 3 of the metal plate 1 as shown in Fig. 2a, place the spacer 15 on top of it as shown in Fig. 2b, and then insert the upper IC 13. This is done through a series of steps: loading (c in the same figure). Here, in order to configure the metal plate 1 as described above, an upper IC is attached to the lower IC 14.
13, positioning is inevitably performed. Then, overlap part 1 of the electrical lead.
0 as described above, the fourth
The stacked IC shown in the figure is obtained.
なお本実施例においては、半田揚治具はデユア
ルインライン型集積回路用として述べたが本考案
の技術的思想からすれば、超小型のリードリレー
や抵抗等の全てのデユアルインライン型電子部品
に適用出来る事は言うまでもない。また金属板1
も、上記チタン材に限定されず、半田接合しない
金属材を広く対象とする事が出来る。 In this example, the soldering jig was described for dual-in-line integrated circuits, but from the technical idea of this invention, it can be applied to all dual-in-line electronic components such as ultra-small reed relays and resistors. It goes without saying that it is possible. Also metal plate 1
However, the present invention is not limited to the above-mentioned titanium material, and can be applied to a wide range of metal materials that are not soldered.
以上詳細に説明したように、本考案は半田接合
しない金属板に下部電子部品を挿着固定させる多
数の溝部と、この溝部間の上側縁部に上部電子部
品を挿着案内し保持する相対向した突起部とを形
成し、しかもこの金属板を多数並列に連結する構
成とするものである。
As explained in detail above, the present invention consists of a number of grooves for inserting and fixing lower electronic components into a metal plate that is not soldered, and a pair of opposing grooves for inserting, guiding and holding the upper electronic components at the upper edges between the grooves. In addition, a large number of these metal plates are connected in parallel.
従つて、上部電子部品を積み重ねる作業と半田
揚治具に搭載する作業とを同時に行う事が出来、
その上大量の電子部品を一度に半田揚処理する事
が出来る為、作業能率並びにスループツトを向上
させる事が出来るという効果がある。 Therefore, the work of stacking the upper electronic components and the work of mounting them on the soldering jig can be done at the same time.
Furthermore, since a large amount of electronic components can be soldered at once, there is an effect that work efficiency and throughput can be improved.
第1図は本考案の一実施例を説明する一部切欠
斜視図、第2図は同実施例を用いたIC搭載状況
を説明する要部斜視図、第3図は第2図cに示す
IC搭載部断面図、第4図は同実施例を用いたス
タツクIC完成図、第5図は従来例の説明図であ
る。
1……金属板(チタン材)、2……突起部、3
……溝部、10……電気リードのオーバーラツプ
部、13……上部電子部品(上部IC)、14……
下部電子部品(下部IC)、15……スペーサ。
Fig. 1 is a partially cutaway perspective view illustrating an embodiment of the present invention, Fig. 2 is a perspective view of main parts illustrating the IC mounting situation using the same embodiment, and Fig. 3 is shown in Fig. 2c.
FIG. 4 is a sectional view of the IC mounting part, FIG. 4 is a completed diagram of a stacked IC using the same embodiment, and FIG. 5 is an explanatory diagram of a conventional example. 1...Metal plate (titanium material), 2...Protrusion, 3
...Groove portion, 10...Overlapping portion of electrical leads, 13...Upper electronic component (upper IC), 14...
Lower electronic component (lower IC), 15...Spacer.
Claims (1)
み重ねて、半田揚処理を施す際に使用するスタツ
ク型電子部品の半田揚治具において、上記電子部
品の本体が挿着されるよう長さ方向を横切る方向
に形成された多数の溝部と、上部電子部品を保持
すると共に下部電子部品の挿着位置と一致させる
よう上記溝間の上側縁部において対向して形成さ
れた多数の突起部とを有する半田接合しない金属
板を並列に多数連結させた事を特徴とするスタツ
ク型電子部品の半田揚治具。 In a soldering jig for stack type electronic components used when stacking dual-in-line type electronic components and performing a soldering process, the soldering jig is formed in a direction transverse to the length direction so that the main body of the electronic component can be inserted. and a large number of protrusions formed oppositely at the upper edge between the grooves so as to hold the upper electronic component and match the insertion position of the lower electronic component. A stack-type soldering jig for electronic components characterized by a large number of plates connected in parallel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16300585U JPH056665Y2 (en) | 1985-10-25 | 1985-10-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16300585U JPH056665Y2 (en) | 1985-10-25 | 1985-10-25 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6273557U JPS6273557U (en) | 1987-05-11 |
| JPH056665Y2 true JPH056665Y2 (en) | 1993-02-19 |
Family
ID=31090807
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16300585U Expired - Lifetime JPH056665Y2 (en) | 1985-10-25 | 1985-10-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH056665Y2 (en) |
-
1985
- 1985-10-25 JP JP16300585U patent/JPH056665Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6273557U (en) | 1987-05-11 |
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