JPH0572766B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a variable impedance device used in a noise reduction device or the like that includes a signal compressor and a signal expander.

Conventionally, in order to improve the S/N ratio of a particular communication system or a particular recording/reproduction system, it has been known to use a noise reduction device equipped with a signal compressor and a signal expander in that system. .

In particular, the circuit components of the signal compressor and the signal expander are used in common, and the function of the signal compressor and the function of the signal expander can be switched by switching the mode switch. The equipment is manufactured by the Society of Electronics and
Radio Technician Magazine Volume 8 May 6, 1974
Suggested by the monthly issue.

FIG. 1 shows a circuit block diagram of this switchable signal compressor/signal expander. This type of switchable signal compressor/stretcher is known in the art as a Dolby B noise reduction system (the word Dolby is a registered trademark of Dolby Laboratories).

By switching this Dolby B noise reduction system to a signal compressor, the system becomes an encoder. A signal compressor (encoder) compresses the dynamic range of the input signal before it is recorded on audio tape. By switching the system to a signal expander, the system becomes a decoder. A signal expander (decoder) restores the linearity of the dynamic range to the input signal. The noise introduced during the recording/playback process is considerably reduced, so that the signal compressor-signal expander combination acts as a noise reduction device.

In Dolby B noise reduction systems, signal compression/signal expansion operations are typically performed on signal components above a frequency value of 200 Hz.

The well-known encoder/decoder will now be described in detail with reference to the circuit block of FIG.

_The noise reduction device _shown in FIG.
and a side bus l _s between SW and the output terminal T ₂ .

On the main bus l _n there is a coupling circuit 10, an inverter 1
1 is placed.

A variable filter 12, a signal amplifier 13, a control amplifier 14, a rectifier/smoothing circuit 15, and an overshoot subtractor 16 are arranged on the side bus _Ls .

If mode switch SW is connected to terminal _T3 , this circuit block becomes an encoder.
The coupling circuit 10 and the inverter 11 on the main bus l _n perform linear amplification.

The variable filter 12 changes the amount of transmission for signal components with frequencies of 200 Hz or higher in accordance with the control signal S _c generated by the rectifier/smoothing circuit 15. To explain in more detail, due to the loop of the variable filter 12, signal amplifier 13, control amplifier 14, and rectifier/smoothing circuit 15, when the level of the input signal at the common terminal _T5 of the mode switch SW decreases, the amount of transmission from the variable filter 12 decreases. increases.
Therefore, as the input signal level decreases, the signal components on the side bus _Is with frequencies above 200 Hz increase.

If the circuit block is configured as an encoder, the signals on the side bus l _s are routed to the main bus l _n
Added to the above signal. Therefore, the amplitude in Fig. 2 -
As shown in the frequency characteristics, the signal components of 200 Hz or higher gradually have larger amplitude values as the signal level decreases.

On the other hand, if mode switch SW is connected to terminal _T4 , this circuit block becomes a decoder. The inverter 11 on the main bus _ln is configured as a signal inverter, and the output signal of this inverter 11 is applied to the common terminal _T5 of the mode switch SW, so the input signal on the side bus _ls is A signal having the opposite phase to the input signal applied to the terminal _T1 is now supplied. Therefore, since the signal on the side bus l _s is subtracted from the signal on the main bus l _n , the amplitude-frequency characteristic of the decoder output signal is
Signal components of 200 Hz or more gradually have smaller amplitude values as the signal level decreases.

The overshoot suppressor 16 limits the amplitude value of the inter-terminal voltage applied to the variable filter 12. If this overshoot subtractor 16 were not in place, undesirable changes would occur in high level transient signals.

By the way, one of the recent technological trends in electronic devices, such as portable tape recorders, is to make them smaller and lighter. In such a case, it is desirable to use a small power supply battery, and the power supply voltage will be as low as, for example, 3V.

In view of the above-mentioned technological trends, we will consider whether the above-described noise reduction operation is possible with an ultra-low voltage power supply of about 3V. According to the inventor's study, the power supply voltage
It has been found that the signal compressor circuits and signal expansion circuits that make up the noise reduction device cannot operate at around 3V.

This cannot be achieved by simply changing the circuit constants of each circuit constituting the noise reduction device for use with a low voltage power supply. Therefore, the inventor of the present invention has carefully studied each circuit that constitutes the noise reduction device. We have now come up with a new technical idea regarding the variable filter 12 that constitutes the noise reduction device.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a variable impedance device that operates reliably with a low voltage power supply.

Hereinafter, the present invention will be specifically explained with reference to the drawings.

FIG. 3 shows a circuit block diagram of a switchable signal compressor/expander according to one embodiment of the present invention, with the components within the dashed line IC being implemented in a monolithic semiconductor integrated circuit. The numbers in circles indicate the terminal numbers of the integrated circuit.

A coupling circuit 10 and an inverter 11 are arranged on the main bus l _n between the input terminal T ₁ and the output terminal T ₂ . The input terminal T ₁ is connected to the No. 1 terminal of the integrated circuit via the input coupling capacitor C ₁ . The input amplifier 20 is configured in the form of a so-called operational amplifier,
It has a non-inverting input terminal (+), an inverting input terminal (-), and an output terminal. This non-inverting input terminal (+) is connected to the above-mentioned No. 1 terminal, and this output terminal is connected as the No. 3 terminal of the integrated circuit to the terminal _T3 of the mode switch SW outside the integrated circuit and to the main bus _ln. It is connected. A negative feedback network 21 composed of resistors R ₁ and R ₂ is connected between the output terminal and the inverting input terminal (-) of the input amplifier 20, thereby setting the voltage gain of the input amplifier 20. .

One end of the resistor R ₂ of the negative feedback network 21 is AC grounded through a capacitor C ₃ connected to the No. 4 terminal. The reference voltage generator 22 supplies this No. 4 terminal with a DC reference voltage V _REF set at a level approximately half of the power supply voltage V _cc . By connecting a resistor R ₁₀₀ between the first terminal and the fourth terminal, the DC reference voltage V _REF is supplied to the first terminal. Therefore, the DC potential at the output terminal of input amplifier 20 is also at a level approximately close to this DC reference voltage V _REF .

On the side _path between the mode switch SW and the output terminal _T2 , there is a variable filter 12, a signal amplifier 13, a control amplifier 14, a rectifier/smoothing circuit 15,
An overshoot subpressor 16 is arranged. The variable filter 12 has capacitances C ₄ , C ₅ and resistance.
It is composed of R ₁₀₁ , R ₁₀₂ and a variable impedance 23.

The mode switch SW is connected to the No. 5 terminal of the integrated circuit via capacitors C ₄ and C ₅ . The variable impedance 23 is connected to this fifth terminal.

The variable impedance 23 is a variable impedance device according to the present invention, and has a circuit configuration as shown in FIG. Transistors Q ₁ , Q ₃
are held at a predetermined reference voltage V _REF . An input signal V _io is supplied to the bases of the transistors Q ₂ and Q ₄ . A control signal current _SC1 is supplied to each emitter of the transistors _Q5 and _Q6 configured as a differential pair from a voltage-current converter 27a (hereinafter referred to as a V/I converter), which will be described later. Transistor Q ₉ controls the current flowing through transistors Q ₃ and Q ₄ by control signal current SC ₂ supplied from V/I converter 27b, which will be described later.

Note that the V/I converter 27b is connected to a reference power source.
ES ₂ is provided. The purpose of this is to
This is to keep transistors Q ₃ and Q ₄ in a non-operating state when the input signal supplied from the terminal is at a normal signal level, and to put them into an operating state when the input signal is at a predetermined level or higher. Furthermore, the resistor _R33 is provided to increase the dynamic range, and may be replaced with a constant current circuit.

The input impedance at point A in the variable impedance device 23 as described above is determined. Let the voltage level at point A be V _A. At this time, there is a relationship between the voltage level V _A and the respective collector currents _ic1 and _ic2 of the transistors Q ₁ and Q ₂ as shown in the following equation.

i _c1 = - (V _A・R ₃₃ ) / {(r _e1 + R _n ) ・(r _e1 + R _n +2R ₃₃ )} ...(1) i _c2 = {V _A / (r _e1 + R _n )} ・[ 1-{{R ₃₃ /(r _e1 +R _n +2R ₃₃ }) ……(2) However, in the above equations (1) and (2), R _n is the resistance R ₃₁ ,
R ₃₂ , and r _e1 is each emitter equivalent resistance (not shown) of the transistors Q ₁ and Q ₂ .

Next, transistors Q ₅ and Q ₆ by i _c1 and i _c2
Find the voltage difference between each base.

V _BE5 −V _BE6 = r _e2 (i _c2 − i _c1 ) V _RE5 −V _RE6 = (r _e2・V _A )/(r _e1 +R _n ) ……(3) However, r _e2 is the diode D ₁ , D ₂ equivalent resistance (not shown).

Furthermore, if the current flowing through point A is I _A , I _A = ( _re2 ·V _A )/{( _re1 + R _n )·2r _e3 } (4). However, r _e3 is the emitter equivalent resistance (not shown) of the general formulas Q ₅ and Q ₆ .

Then, the input impedance R _io is determined from the above VA and I _A as follows: R _io =V _A /I _A =(r _e1 + _{R n )} ·(2r _e3 /r _e2 ) (5).

The operation of the variable impedance device 23 shown in FIG. 4 is as follows.

When the signal level of the input signal Vin increases, the rectified and smoothed output level of the rectifier/smoothing circuit 15 increases accordingly, and the level of the output current (control signal current) _SC1 of the V/I converter 27a increases. The emitter currents of transistors Q ₅ and Q ₆ increase as the level of current SC ₁ increases, so
The equivalent resistance re ₃ of each emitter decreases.

Therefore, the input impedance Rin is calculated using the above formula 5.
As is clear from the above, since it is proportional to the emitter equivalent resistance _re3 , it decreases as the level of the input signal Vin increases.

When the signal level of the input signal Vin further increases, and the input voltage of the V/I converter 27b, that is, the rectified and smoothed output of the rectifier/smoothing circuit 15 becomes higher than the voltage level of the reference power supply _ES2 , this V /I converter 27b outputs control signal current _SC2 . Transistors Q ₃ and Q ₄ are controlled by transistor Q ₉ .
It is brought into operation by being turned on by SC ₂ and forming a collector current I ₀ .

Due to the operation of transistors Q ₃ and Q ₄ , the amount of current change in diodes D ₁ and D 2 brought about in response to the input signal Vin increases, and the amount of current change in diodes D 1 and D ₂ that is brought about in response to the input signal Vin increases, and the amount of current change in transistors Q ₅ and Q ₆ increases.
The signal level provided between the bases of is increased. As a result, the input impedance Rin is further reduced by the operation of transistors Q ₃ and Q ₄ .

Incidentally, in the process of considering the variable impedance device 23 having the configuration shown in FIG. 4, the inventor of the present invention considered a variable impedance device having the configuration shown in FIG. 5. For reference, the variable impedance device 2 in Fig. 5 will be described below.
3, when the power supply voltage is 2V and the input signal Vin is at a large level of 0dB, the encoding characteristics of the noise reduction device (output T for input T ₁ at the time of encoding) As shown by f ₁ in Figure ₆ , the level gradually starts to rise from around 5KHz and reaches 2dB around 20KHz.
A frequency characteristic in which the level also increases was obtained. That is, in this case, although the input signal Vin is at a high level of 0 dB, the power supply voltage is an extremely low voltage of 2 V, and the rectifier diode 15 in the rectifier/smoothing circuit 15 is
Since there is a voltage drop in a and 15b, a rectified and smoothed signal of a sufficient level cannot be obtained from the rectifier/smoothing circuit 15, and accordingly, V/
The output from the I converter 27a, ie, the control output current _SC1 , will no longer be increased to a value sufficient to lower the input impedance Rin of the variable impedance device 23. As a result of the input impedance Rin of the variable impedance device not becoming small, there is insufficient signal attenuation by the variable impedance device in the side bus l _s during encoding, and the side bus
A signal with a relatively high level is supplied from l _s to the coupling circuit 10, resulting in an increase in the level of the high frequency signal.

When using the variable impedance device 23 of the embodiment of the present invention shown in FIG. 4, at the same low power supply voltage and input signal Vin level,
A flat frequency characteristic as shown in f ₂ is obtained. That is, in this case, the input signal Vin is
Rectifier/smoothing circuit 15 due to the high level exceeding the normal signal level such as 0 dB.
whose output becomes higher than the level of the reference power supply ES ₂ coupled to the V/I converter 27b, transistors Q ₃ and Q ₄ are activated, and as a result, the input impedance Rin is sufficiently reduced. It is. To sufficiently increase signal attenuation by a variable impedance device in a side bus l _s for a large level input signal Vin during encoding in accordance with the input impedance Rin being sufficiently lowered for a large level input signal Vin. As a result, it is possible to obtain flat frequency characteristics.

The signal amplifier 13 is configured in the form of a so-called operational amplifier, and has a non-inverting input terminal (+), an inverting input terminal (-), and an output terminal. This non-inverting input terminal (+) is terminal 5 and variable impedance 2
Connected to 3. A negative feedback network 24 composed of resistors R ₃ and R ₄ is connected between the output terminal and the inverting input terminal (-) of the signal amplifier 13, thereby setting the voltage gain of the signal amplifier 13. There is. The output signal at the output terminal of the signal amplifier 13 is supplied to an overshoot suppressor 16.

Overshoot suppressor 16 is provided to prevent undesirable changes due to high level transient signals. The output signal of overshoot suppressor 16 is transmitted via buffer 25 to side path _Is of coupling circuit 10.

On the other hand, the control amplifier 14 is configured in the form of a so-called operational amplifier, and has a non-inverting input terminal (+), an inverting input terminal (-), and an output terminal. This inverting input terminal (+) is connected to the fifth terminal and the variable impedance 23. Resistance R ₆ , R ₇ , R ₁₀₃ ,
The voltage gain of the control amplifier 14 is set by connecting a negative feedback network 26 composed of capacitors C ₆ and C ₇ . The No. 6 terminal is arranged to connect the resistor R ₁₀₃ and capacitors C ₆ and C ₇ of the negative feedback network 26 outside the semiconductor integrated circuit. The output signal of the control amplifier 14 is transmitted to a rectifier/smoothing circuit 15.

The rectifier/smoothing circuit 15 includes a rectifier 15a composed of a diode _D3 , and a smoothing circuit 15b composed of capacitors _C8 and _C9 , resistors _R104 and _R105 , and a diode _D4 . Diode _D4 adjusts the so-called attack time and recovery time to appropriate values. The 7th and 8th terminals are the capacitance C ₈ , C ₉ and the resistance R ₁₀₄ , R ₁₀₅ of the smoothing circuit 15b.
It is arranged for connection outside the semiconductor integrated circuit. The output voltage of the smoothing circuit 15b is supplied to V/I converters 27a and 27b.

The V/I converters 27a, 27b receive control signal currents SC ₁ , corresponding to the output voltage of the smoothing circuit 15c,
Generates SC ₂ at its output. Control signal current SC ₁ ,
According to the magnitude of SC ₂ , the impedance value of the variable impedance device 23 constituting the variable filter 12 is controlled as described above.

Variable filter 12, control amplifier 14, rectifier/
The smoothing circuit 15 and the voltage-current converter 27 control the impedance value of the variable impedance 23 according to the decrease in the signal level at the common terminal _T5 of the mode switch SW. side via
The level of signal components with frequencies above 200 Hz transmitted to the path l _s increases.

The coupling circuit 10 is composed of a resistor _R3 placed on the main bus _ln and a resistor _R9 placed on the side path _ls , and the common connection point of the resistor _R8 and resistor _R9 has a main・Signal components on path l _n and side paths
A signal is obtained that is the sum of the signal components on l _s .

The inverter 11 is configured in the form of a so-called operational amplifier, and has a non-inverting input terminal (+), an inverting input terminal (-), and an output terminal. The non-inverting input terminal (+) is connected to the 4th terminal, and the inverting input terminal (-)
is connected to the common connection point of R ₈ and R ₉ , and the output terminal is connected to the second terminal. By appropriately setting the resistance value of the resistor R ₁₀ connected between the output terminal of the inverter 11 and the inverting input terminal (-) and the resistance values of the above-mentioned resistors R ₈ and R ₉ , the gain can be obtained from the second terminal. It is possible to set the level of the output signal of the switchable signal compressor/signal expander.

If the mode switch SW is connected to the terminal T ₃ , the output signal of the input amplifier 20 on the main path l _n is transmitted to its common terminal T ₅ . In this case, the signal component on the main path and the signal component on the side path are added, so this circuit block operates as an encoder.

On the other hand, when the mode switch SW is connected to the terminal ₄ , the output signal of the inverter 11 is transmitted to the common terminal. In this case, the signal on the side bus _ls is subtracted from the signal on the main path _ln , so that this circuit block acts as a decoder.

Note that the No. 9 terminal is connected to the control circuit 28. When the No. 9 terminal is connected to ground potential by the switch, the control circuit 28 stops the operation of the voltage-current converter 27. Furthermore, the 10th terminal is a power supply voltage supply terminal, and the 11th terminal is a grounding terminal.

The non-inverting input terminal (+) of the control amplifier 14 on the side path l _s is connected to the output terminal of the signal amplifier 13
combined. The variable impedance 23 is supplied with a reference voltage V _REF from the reference voltage generator 22 via the resistors R ₁₀₁ and R ₁₀₂ of the variable filter 12 .
The input impedance at the non-inverting input terminal (+) and the input impedance at the inverting input terminal (-) of the limit amplifier 14 are extremely large, and furthermore, 100% DC negative feedback is applied from the output terminal to the inverting input terminal via the negative feedback circuit 26. Because it is applied,
The DC potentials of the non-inverting input terminal (+), the inverting input terminal (-), and the output terminal of the control amplifier 14 are set to a level substantially close to the reference voltage V _REF . Therefore, the operating point of the rectifier/smoothing circuit 15 is set to a potential level approximately close to this reference voltage V _REF .

Since the DC blocking capacitor C ₆ is installed in the negative feedback network 26 of the control amplifier 14 , no DC current flows through the resistor R ₇ of the negative feedback network 26 .

Therefore, the DC input currents i' _{(+)IN and i' (-)IN} flowing into the non-inverting input terminal (+) and inverting input terminal ( _- ) of the control amplifier 14, respectively, and the voltage V ₀ ' at the output terminal are as follows. Given by the following equation, the output voltage V ₀ ' of the control amplifier 14 has only an extremely small DC offset voltage V' _pff .

V ₀ ′=V _REF −(R ₁₀₁ +R ₁₀₂ )i′ _(+)IN +R ₆・i′ _(-)IN 〕V _REF −V′ _pff ……(2) According to the above embodiment, the reference voltage By setting the DC reference voltage V _REF generated by the generator 22 to a level approximately half of the power supply voltage V _cc , each output DC level of the signal amplifier 13 , control amplifier 14 , input amplifier 20 , and inverter 11 can be adjusted. can be maintained at a level approximately half of the power supply voltage _Vcc , so the dynamic range at each output can be increased to a large value.

As described above, according to the variable impedance device of the present invention, it is possible to control the impedance to a desired value even if the power supply voltage is an extremely low voltage.
If the variable impedance device is used in a noise reduction device, extremely good frequency characteristics can be obtained by the impedance control.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an example of the circuit configuration of the noise reduction device, Figure 2 is a frequency characteristic diagram,
Fig. 3 is a circuit diagram of a noise reduction device to which the variable impedance device of the present invention is applied, Fig. 4 is a circuit diagram of the variable impedance device, and Fig. 5 is a circuit diagram of a noise reduction device to which the variable impedance device of the present invention is applied. A circuit diagram of the variable impedance device, and FIG. 6 is a frequency characteristic diagram. 23...variable impedance device, Q ₁ , Q ₂ ,
Q ₃ , Q ₄ , Q ₅ , Q ₆ , Q ₇ , Q ₈ ...transistor, Q ₉
... Control transistor, 27a, 27b ... Voltage-current converter, SC ₁ , SC ₂ ... Control signal current,
_Vio ...Input signal.

Claims (1)

[Claims] 1. First and second transistors Q ₁ and Q ₃ of a first conductivity type whose bases are commonly connected to a first terminal to which a first reference voltage V _REF is supplied, and an input signal Vin is supplied. the third and fourth transistors Q ₂ and Q ₄ of the first conductivity type whose bases are commonly connected to the second terminals connected to the a resistor R ₃₃ , second and third resistors R ₃₁ and R ₃₂ respectively provided between the emitters of the first and third transistors Q ₁ and Q ₂ and the first connection point; 2. A fifth transistor Q ₉ of the first conductivity type, which is commonly connected to the emitters of the fourth transistors Q ₃ and Q ₄ and whose emitter is connected to the reference potential point of the circuit.
and the power supply terminal Vcc and the first and second transistors.
The first terminal connected between the common collector of Q ₁ and Q ₃
a first amplifier comprising a load means D ₁ and a second load means D ₂ connected between the power supply terminal Vcc and the common collector of the third and fourth transistors Q ₂ and Q ₄ ; First and second transistors Q ₁ , Q ₃
a sixth transistor of a second conductivity type, the collector of which is connected to the common collector of the transistor and the collector of which is connected to the second terminal;
Q ₅ and a second transistor whose emitter is commonly connected to the emitter of the sixth transistor Q ₅ and whose base is connected to the common collector of the third and fourth transistors Q ₂ and Q ₄ .
a seventh transistor Q ₆ of conductivity type, an eighth transistor Q 8 of first conductivity type whose base and collector are connected to the collector of the seventh transistor Q ₆ and whose emitter is connected to the reference potential _point of the circuit; is connected to the second terminal and the base is connected to the eighth terminal.
a second amplifier circuit consisting of a ninth transistor _Q7 of the first conductivity type connected to the base of the transistor _Q8 and whose emitter is connected to the reference potential point of the circuit; The first converter 27a receives the first conversion signal _SC1 through the rectifier/smoothing circuit 15 to form the first conversion signal _SC1 , which is converted into a current signal. ₅ , _Q6 , and the rectifier/smoothing circuit 15.
The second converter generates the second conversion signal SC ₂ converted into a current signal in response to the output of the rectifier/smoothing circuit 15 when the output of the second converter reaches a predetermined level or _higher . A variable impedance device configured to be supplied to the base of the fifth transistor _Q9 , and to provide a variable impedance to the second terminal by the first and second amplifiers.