JPH0583006B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase synchronized oscillator, and more particularly to a phase synchronized oscillator having a steady phase error abnormality detection circuit.

[Conventional technology]

As shown in FIG. 5, a conventional phase synchronized oscillator with a steady state phase error abnormality detection circuit includes a voltage controlled oscillation circuit 3, a frequency conversion circuit 20 that converts its output frequency into a phase comparison frequency, and this output signal. It consists of a phase comparator circuit 1 that generates a signal according to the phase difference with a reference input signal, and a loop filter 2 that removes unnecessary high frequency components from this output and provides a control signal to a voltage controlled oscillation circuit 3. Here, the frequency conversion circuit 20 is the voltage controlled oscillation circuit 3
This converts the nominal output frequency of the input signal into the reference input signal frequency, and a frequency divider circuit or multiplier circuit is usually used. Therefore, if the nominal output frequency of the voltage controlled oscillation circuit 3 is equal to the reference input frequency, it can be omitted. Generally, in a phase synchronized oscillator used in communication equipment, etc., in order to monitor its synchronization state, a steady phase error detection circuit 3 is used as shown in FIG.
0 is added. In FIG. 5, reference numerals 21 and 22 are time limit circuits, which are usually constructed from known circuits such as monostable multivibrators. Also 23,2
4 is a retiming circuit, which is usually realized by a D-type flip-flop. The time limit circuit 21 and the retiming circuit 23 and the time limit circuit 22 and the retiming circuit 24 are effective only when the steady phase error increases in the negative direction and in the positive direction, respectively, so the outputs of the retiming circuits 23 and 24 are The signals are logically summed by an OR circuit 25.

FIG. 6 is a waveform diagram showing the operation of the steady phase error detection circuit when the phase synchronized oscillation circuit shown in FIG. 5 is operating normally. Also, Figure 7 shows the fifth
FIG. 6 is a waveform diagram showing the operation of the steady phase error detection circuit when the phase synchronized oscillator shown in the figure has a steady phase error abnormality. Here, f ₁ , f ₂₀ , f ₂₁ , and f ₂₂ are signals flowing along the lines shown in FIG. 5, respectively.

Further, in FIG. 6, T ₁ and T ₂ are timings determined by timer circuits 21 and 22, respectively, and the two values are usually equal. When the period of the two signals input to the phase comparator circuit 1 is T, the detection threshold t of a steady phase error abnormality is calculated by the following formula:
As shown in (1) and (2).

t=T/2-T ₁ ...(1) or t=T/2-T ₂ ...(2) In other words, if the steady phase error of the phase-locked oscillator circuit in FIG. 5 exceeds the above t, It is determined that the steady phase error is abnormal.

[Problem that the invention seeks to solve]

However, in the conventional steady phase error detection circuit of the phase synchronized oscillator described above, the detection threshold t is shown in equations (1) and (2). It is determined by T, T ₁ and T ₂ ,
Since the phase comparison period T is strongly influenced by the characteristics of the phase synchronized oscillator, the degree of freedom is generally small. Therefore, the detection threshold t is substantially determined by the pulse widths T ₁ and T ₂ generated by the timer circuits 21 and 22. Here, if threshold requirements are not strict, the time limit circuits 21 and 22 can be realized by relatively simple monostable multivibrators or the like. but,
The output pulse width is mainly determined by analog elements such as capacitors and resistors, so it is necessary to set a highly accurate threshold value that cannot ignore the effects of capacitance deviation of these elements, temperature characteristics, changes over time, etc. It had the disadvantage of being difficult. Furthermore, the conventional steady-state phase error detection circuit described above has the disadvantage that the range of possible pulse widths that can be generated is narrow, and that it is difficult to realize this especially when detection of minute phase errors is required. Furthermore, the conventional steady-state phase error detection circuit of a phase-locked oscillator shown in Fig. 5 detects instantaneous phase error abnormalities, such as a sudden change in the phase of the reference input signal, which cannot normally occur due to a failure of the phase-locked oscillator. However, this has the disadvantage that it is difficult to distinguish this from a true alarm caused by a failure of the phase synchronized oscillator.

It is an object of the present invention to eliminate such drawbacks of conventional circuits, to be able to detect even the slightest steady phase error with a simple circuit configuration, and to detect instantaneous phase error abnormalities that are not caused by failures in the phase synchronized oscillator. It is an object of the present invention to provide a phase synchronized oscillator that can easily prevent the occurrence of alarms caused by.

[Means for solving problems]

The phase-locked oscillator of the present invention includes a voltage controlled oscillation circuit, a jitter generation circuit that applies a predetermined phase variation to the output signal of the voltage controlled oscillation circuit, and a jitter generation circuit that is proportional to the phase difference between the output signal of the jitter generation circuit and a reference input signal. a first phase comparison circuit that generates a signal output from the first phase comparison circuit, a loop filter that removes unnecessary high frequency components from the output signal of the first phase comparison circuit and provides a control voltage to the voltage controlled oscillation circuit, and the jitter generation circuit. Compare the phase of the output signal and the reference input signal, and
a second phase comparator circuit that generates two logic levels in response to the phase lead/lag of two signals; It has a signal disconnection detection circuit that detects that the signal level has reached the level.

〔Example〕

Embodiments of the phase-locked oscillator of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a phase synchronized oscillator having a steady phase error detection circuit according to the present invention. FIG. 2 also shows the jitter generation circuit 4 of FIG.
FIG. In FIG. 1, 100 is a reference input terminal for the phase-locked oscillator, and 2
00 is a reference output terminal, and 300 is an alarm output terminal for a steady phase error abnormality of the phase synchronized oscillator.

Further, 1 is the first phase comparison circuit, 2 is the loop filter, 3 is the voltage controlled oscillation circuit, 4 is the jitter generation circuit, 5 is the second phase comparison circuit, and 6 is the output of the second phase comparison circuit 5. This is a signal disconnection detection circuit that outputs a phase error alarm when the logic level of the signal does not change for a predetermined period of time or more. here,
The second phase comparator circuit 5 generates two logic levels depending on the phase difference between the two applied signals, and is constituted by, for example, a D-type flip-flop. Further, the jitter generating circuit 4 adds a predetermined jitter to the output signal of the voltage controlled oscillation circuit 3, and can be constructed from various known circuits, but in this embodiment, the frequency of the output signal of the voltage controlled oscillation circuit 3 is , a frequency conversion circuit (corresponding to the conventional frequency conversion circuit 20 shown in FIG. 5) that converts the frequency of the reference input signal, and the circuit shown in FIG. 2. Here, the jitter generation circuit shown in FIG. 2 will be explained. Reference numeral 500 indicates an input terminal of the jitter generation circuit, and reference numeral 501 indicates an output terminal, which correspond to the terminals with the same numbers in the jitter generation circuit shown in FIG. Further, 10 is a counter with a preset function, and 12 is a frequency dividing circuit.

In Fig. 2, counter 1 with preset function
The output signal output from the Qc terminal 0 is output from the output terminal 501 and is also output from the frequency dividing circuit 12.
is added to the T terminal of The frequency dividing circuit 12 divides the frequency of this signal and supplies it to the B terminal of the counter 10 with a preset function as preset data. As a result, the frequency division ratio of the preset function counter 10 changes periodically every cycle of the frequency divider circuit.
As an example, the counter 1 with preset function shown in Fig. 2
When the preset data is 0, the frequency is divided by 8, and when the preset data is 1, the frequency is divided by 6.
When 2 is a frequency divider circuit, the preset function counter 10 alternately performs frequency division by 8 and frequency division by 6. As a result, the present jitter generation circuit 4:
On average, the frequency is divided by 7 (average of 8 and 6), but the phase of each bit of the output signal is smaller than the input clock signal period compared to the output signal of a normal divide-by-7 circuit. This includes jitter having an amplitude of time corresponding to 1/2 period.

Naturally, jitter from the jitter generation phase appears in the output signal of the first phase comparator circuit 1 of the phase-locked oscillator shown in FIG. is removed by the loop filter 2, so it is not affected by the operation of the phase-locked oscillator.

Next, the operation of the second phase comparison circuit 5 will be explained. 3 and 4 are waveform diagrams showing input and output signals of this second phase comparator circuit 5, and FIG. 3 shows a case where the steady phase error of the phase synchronized oscillator of this embodiment is in a normal state. , and FIG. 4 similarly shows a case where the steady phase error becomes abnormal. Note that the symbols f ₁ , f ₂ , and f ₃ in each figure correspond to those in FIG. 1, respectively.

The waveform f shown by the broken line in FIG. 3 is a hypothetical signal for a normal case in which the feedback loop signal of the phase-locked oscillator does not include jitter (the output signal f ₂₀ of the frequency conversion circuit 20 in the conventional circuit shown in FIG. 5). The corresponding waveforms are shown. In the phase-locked oscillator of the present invention, since the jitter generation circuit 4 is included in the feedback loop, the input signal _f2 of one of the two phase comparison circuits 1 and 5 always contains jitter with an amplitude J. When the phase difference between this signal and the reference input signal _f1 is detected by the second phase comparator circuit 5, which is composed of a D-type flip-flop or the like and generates two logic levels according to the phase difference, the jitter generation circuit 4 detects the phase difference between this signal and the reference input signal f1. If the signal _f2 is behind the reference input signal _f1 , a logic output of "0" is obtained, and if it is ahead of the reference input signal f1, a logic output of "1" is obtained, so the output signal is in the form of a clock signal.
f ₃ is obtained. Here, the period of the output signal _f3 is equal to the jitter period added by the jitter generating circuit 4, and therefore is known.

Next, a case where the steady phase error of the phase synchronized oscillator increases will be explained. In Figure 4,
The waveform indicated by f ₂ ' indicates _{the output signal of the jitter generation circuit 4 during normal operation, that is, f 2 in} FIG. This shows a case where a phase error occurs. Here, when the steady phase error P satisfies the following equation (3), the output signal f ₂ of the jitter generation circuit 4 always leads the reference input signal f 1 , and the output signal f ₂ of the jitter generation circuit 4 always leads the reference input signal f 1 . The output signal _f3 is always "1".

|P|>|J| ...(3) If the output signal _f2 of the jitter generation circuit 4 is delayed by more than P with respect to the reference input signal _f1 , the output of the phase comparator circuit 5 is The signal _f3 is always "0".

As explained above, the output signal _f3 of the second phase comparator circuit 5 becomes a clock signal when the steady phase error of the phase synchronized oscillator is less than the jitter amplitude added in advance, but when it exceeds the jitter amplitude. When a steady phase error occurs, it is fixed at a logic level of "1" or "0".

Therefore, if the output signal _f3 of the phase comparator circuit 5 is regarded as a clock signal and the signal disconnection detection circuit 6 monitors whether the same logic level is output for a certain period of time or more, the steady state of the phase synchronized oscillator can be determined. It is possible to easily detect whether the phase error exceeds the threshold determined by the jitter amplitude.

Incidentally, an instantaneous phase abnormality such as a sudden change in the phase of the reference input signal is resolved in a short time determined by the transient response characteristics of the phase synchronized oscillator, and the state returns to a steady phase error state. Therefore, if the signal loss detection time of the signal loss detection circuit 6 is set to be longer than the transient response time of the phase synchronized oscillator, an alarm will be generated for instantaneous phase error abnormalities that cannot normally occur due to a failure of the phase synchronized oscillator. does not occur.

In this way, in the phase synchronized oscillator of this embodiment, the generation of an alarm can be easily controlled not only with respect to the amount of phase error but also with respect to the length of its duration.

Furthermore, in the phase-locked oscillator of this embodiment, the detection threshold for steady phase error abnormality is determined by the jitter amplitude of the feedback loop generated only by the digital logic element. It is possible to detect phase errors with high precision using the above-mentioned simple circuit without being affected by changes over time, and it is also easy to detect minute phase errors, which was extremely difficult with conventional circuits.

Note that it is possible to provide the first phase comparison circuit 1 with the same phase detection characteristics as the second phase comparison circuit 5 of the phase-locked oscillator of this embodiment, and in this case, the first and second phase comparison circuits of the present invention Of course, one phase comparison circuit can also serve as the phase comparison circuit.

〔Effect of the invention〕

As is clear from the above explanation, the phase synchronized oscillator of the present invention not only can easily detect minute and precise steady phase errors with a simple circuit configuration, but also can This has the effect that the detection threshold can be determined even when the detection threshold is set.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
Fig. 2 is a block diagram showing details of the jitter generation circuit shown in Fig. 1, Figs. 3 and 4 are waveform diagrams showing the operation of each part in Fig. 1, and Fig. 5 is a block diagram showing the conventional circuit. , FIG. 6, and FIG. 7 are waveform diagrams showing the operation of each part of the conventional circuit. 1, 5... Phase comparison circuit, 2... Loop filter,
3... Voltage controlled oscillation circuit, 4... Jitter generation circuit, 6
... Signal disconnection detection circuit, 10 ... Counter with preset function, 11 ... Frequency division circuit, 20 ... Frequency conversion circuit,
21, 22...Time limit circuit, 23, 24...Retiming circuit, 25...OR circuit, 30...Steady phase error detection circuit, 100...Reference input terminal, 200...Output terminal, 300...Phase error alarm output terminal, 500...Jitter Input terminal of the generating circuit, 501... Output terminal of the jitter generating circuit, f... Virtual signal waveform not including jitter, _f1 ... Reference input signal waveform, _f2 , _f2 '... Output signal waveform of the jitter generating circuit, _f3 ... Output signal waveform of the phase comparison circuit, f ₂₀ ... Output signal waveform of the frequency conversion circuit,
f ₂₁ , f ₂₂ ... Output signal waveform of time limit circuit.

Claims (1)

[Claims] 1. A voltage controlled oscillation circuit, a jitter generation circuit that applies a predetermined phase variation to the output signal of this voltage controlled oscillation circuit, and a first jitter generation circuit that generates a signal proportional to the phase difference between the output signal of this jitter generation circuit and a reference input signal. a phase comparison circuit, a loop filter that removes unnecessary high frequency components from the output signal of the first phase comparison circuit and provides a control voltage to the voltage controlled oscillation circuit, and an output signal of the jitter generation circuit and a reference input signal. a second phase comparator circuit that compares the phases of the two signals and generates two logic levels corresponding to the phase lead/lag of the two signals; and a logic level of the output signal of the second phase comparator circuit that is predetermined. 1. A phase synchronized oscillator comprising: a signal disconnection detection circuit for detecting that the same logic level has been maintained for a period of time or more.