JPH0584931B2 - - Google Patents
Info
- Publication number
- JPH0584931B2 JPH0584931B2 JP62102530A JP10253087A JPH0584931B2 JP H0584931 B2 JPH0584931 B2 JP H0584931B2 JP 62102530 A JP62102530 A JP 62102530A JP 10253087 A JP10253087 A JP 10253087A JP H0584931 B2 JPH0584931 B2 JP H0584931B2
- Authority
- JP
- Japan
- Prior art keywords
- stage
- output
- shift register
- exclusive
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Detection And Correction Of Errors (AREA)
- Error Detection And Correction (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62102530A JPS63268037A (ja) | 1987-04-24 | 1987-04-24 | 有限体乗算回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62102530A JPS63268037A (ja) | 1987-04-24 | 1987-04-24 | 有限体乗算回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63268037A JPS63268037A (ja) | 1988-11-04 |
| JPH0584931B2 true JPH0584931B2 (2) | 1993-12-03 |
Family
ID=14329861
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62102530A Granted JPS63268037A (ja) | 1987-04-24 | 1987-04-24 | 有限体乗算回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63268037A (2) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4472808B2 (ja) * | 1999-08-19 | 2010-06-02 | ネッツエスアイ東洋株式会社 | 積和演算装置及びこれを用いた暗号・復号装置 |
| JP4484002B2 (ja) * | 1999-10-04 | 2010-06-16 | ネッツエスアイ東洋株式会社 | 演算プロセッサ |
-
1987
- 1987-04-24 JP JP62102530A patent/JPS63268037A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63268037A (ja) | 1988-11-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS60144834A (ja) | 有限体の演算回路 | |
| US5227992A (en) | Operational method and apparatus over GF(2m) using a subfield GF(2.sup. | |
| JPH02148225A (ja) | 有限体の乗法的逆数元を計算するデータ処理方法及び装置 | |
| US6052704A (en) | Exponentiation circuit and inverter based on power-sum circuit for finite field GF(2m) | |
| US4638449A (en) | Multiplier architecture | |
| JPH09231742A (ja) | 非同期fifoにおいてハーフフルフラグ及びハーフエンプティフラグを作成するステートマシンの構成 | |
| US5964826A (en) | Division circuits based on power-sum circuit for finite field GF(2m) | |
| JPH0584931B2 (2) | ||
| US5870322A (en) | Multiplier to selectively perform unsigned magnitude multiplication or signed magnitude multiplication | |
| Chren Jr | Low delay-power product CMOS design using one-hot residue coding | |
| US5691930A (en) | Booth encoder in a binary multiplier | |
| Cardarilli et al. | RNS-to-binary conversion for efficient VLSI implementation | |
| JPH10187471A (ja) | ガロア域256演算用の組合せ多項式乗算器 | |
| Gorodecky et al. | Efficient hardware operations for the residue number system by Boolean minimization | |
| JPH03661B2 (2) | ||
| JPS63219066A (ja) | 直交変換装置 | |
| JPH0519170B2 (2) | ||
| JPS5841532B2 (ja) | セキワケイサンカイロ | |
| JPS63221426A (ja) | GF(2▲上m▼)のガロア体に属する元の乗算装置 | |
| JP2701378B2 (ja) | 演算方式 | |
| JP3346204B2 (ja) | 可変長符号復号装置 | |
| JP3433487B2 (ja) | 2進10進変換器 | |
| KR100265358B1 (ko) | 고속의쉬프팅장치 | |
| CN113467987A (zh) | 使用实时可重构生成多项式的快速crc码计算电路 | |
| JPH01300338A (ja) | 浮動小数点乗算器 |