JPH06103752A - Memory circuit - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To provide a memory circuit suitable for a semiconductor integrated circuit and capable of low-speed low-power consumption operation or high-speed operation. [Structure] Static RAM 101 for storing data
A read data signal line 102, a write data signal line 103, a RAM address signal line 104, an address latch 108, an address selection circuit 109, an address comparison circuit 110, and a data bus 10 for data transfer.
5, data latch 106, and data selection circuit 107
A memory circuit including an address signal line 111 and a control circuit 112 for controlling the circuit group and the like according to a read / write state, and it is possible to reduce the operation speed of the memory and the data bus, and to reduce power consumption. The one-chip integrated circuit can be realized. Further, it is easy to realize high-speed operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory circuit particularly suitable for realizing a semiconductor integrated circuit such as a microprocessor and a signal processor in which a high speed memory and a data bus are integrated on one chip.

[0002]

2. Description of the Related Art A conventional memory circuit will be described below with reference to the drawings.

FIG. 3 shows an example of the configuration of a conventional memory circuit. The memory circuit of FIG. 3 is an example of a memory circuit used for a processor or the like for reading / writing data from / to a data bus. In FIG. 3, 301 is a static RAM, 302 is a read data signal line, 303 is a write data signal line, 304 is an address signal line, and 305.
Is a data bus, and 306 is a control circuit.

In the memory circuit of FIG. 3, data is read from the static RAM 301 at the time of reading, and the data is read to the data bus 305 via the read data signal line 302. Data bus 305 when writing
Data is written in the static RAM 301 via the write signal line 303. The control circuit 306 controls the data of the static RAM 301 and the data bus (usually, bus drivers and the like are not particularly described). The address of the static RAM 301 is the address signal line 3
Supplied with 04.

Next, the timing of the conventional memory circuit shown in FIG. 3 will be described with reference to FIG. FIG. 4 is a timing diagram of the conventional memory circuit shown in FIG. 40 when reading
The data of the static RAM 301 is read at the timing of 1. Next, the data read at the timing of 402 is transferred via the data bus 305. 403
At the timing of, nothing is done at the time of reading.

At the time of writing, nothing is done at the timing of 411. Next, at the timing of 412, the data written in the RAM is transferred via the data bus 305. Next, at the timing of 413, the static RAM 30
The data is written in 1. The timing of 403 at the time of reading and the timing of 411 at the time of writing are useless timing, and in order to avoid this, it is necessary to change the bus timing according to reading and writing, but it is difficult for a processor or the like. If the data bus timing is the same for read and write, read timing, 401 and 411, bus (data transfer) timing, 402 and 412, write timing, 403
And 413 have the same timing, and control is performed at three timings of reading, bus (data transfer), and writing.

[0007]

However, in the conventional memory circuit described above, it is necessary to perform read, bus (data transfer), and write in one machine cycle, and the memory requires high-speed operation for both read and write. The bus also needs to operate at high speed. Further, it is difficult to increase the speed when the capacity of the memory is large, and it is difficult to increase the speed when the circuit size of the data bus is large. Further, in order to realize high-speed operation, there is a problem that power consumption increases in the one-chip semiconductor integrated circuit.

The present invention solves the above problems and provides a memory circuit suitable for semiconductor integrated circuits and capable of low-speed low-power consumption operation or high-speed operation.

[0009]

The present invention has the following constitution in order to solve the above problems. That is, a static RAM for storing data, a read data signal line for outputting read data of the static RAM, a write data signal line for inputting write data of the static RAM, and a RAM address for inputting an address of the static RAM. A signal line, an address latch for holding a write address of the address signal line at the time of writing, the address latch connected to the address signal line, the output of the address latch at the time of writing, the address signal line at the time of reading, and the RAM address An address selection circuit that outputs a selected address to a signal line and an address connected to the address latch and the address signal line and held in the address latch at the time of reading and the address of the address signal are compared and matched. Address comparison circuit that outputs a signal to the control circuit, a data bus that performs data transfer, a data latch that holds the write data of the data bus at the time of writing and outputs the write data that is held in the write data signal line, and the read data signal Line and the write data signal line, and when the match signal is output from the address comparison circuit at the time of reading, the data on the write data signal line is selected, and when the match signal is not output at the time of reading, the read data signal A data selection circuit for selecting line data and outputting the selected data to the data bus, and the static RAM, the data latch, the data selection circuit, the address latch, and the address selection circuit according to a read / write state. And the control circuit for controlling the address comparison circuit Characterized in that it consists of.

[0010]

According to the structure of the present invention, at the time of writing, the data transferred is latched by the data latch by the data latch, and the static RAM writes the data latched in the previous data latch. With the above function, the static RAM can perform the write operation without waiting for the data on the data bus at the time of writing. The control can be performed at two or one timing of reading, data bus (data transfer) or writing. Therefore, the memory and the data bus can operate at a lower speed than the conventional example. In particular, with regard to writing to the memory, it is possible to operate at a significantly lower speed than before. Further, high speed operation of the memory circuit and the bus can be easily realized.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is an example of a configuration diagram of a memory circuit. In FIG. 1, 101 is a static RAM, 10
2 is a read data signal line, 103 is a write data signal line, 104 is a RAM address signal line, 105 is a data bus, 106 is a data latch, 107 is a data selection circuit, 108 is an address latch, 109 is an address selection circuit, and 110 is An address comparison circuit, 111 is an address signal line, and 112 is a control circuit.

In the memory circuit of FIG. 1, for address control, the address latch 108 latches and holds the write address of the address signal line 111 at the time of writing. Further, the write address previously latched in the address latch 108 is selected by the address selection circuit 109, is output to the RAM address signal line 104, and becomes the write address of the static RAM 101. The address latch 108 is composed of a master-slave type two-stage latch, and the output does not change immediately after latching, and the static R
It changes after the end of the write operation of the AM 101. At the time of reading or when reading and writing are not performed, the address latch 108 does not latch the address and holds the previously latched address. At the time of reading, the read address of the address signal line 111 is selected by the address selection circuit 109, output to the RAM address signal line 104, and becomes the address of the static RAM 101.

The address selection circuit 109 is connected to the output of the address latch 108 and the address signal line 111, selects the output of the address latch 108 at the time of writing, and outputs the previous write address to the RAM address signal line 104. At the time of reading, the address signal line 111 is selected and the read address is output to the RAM address signal line 104. Therefore, the address of the RAM 101 is the read address of the address signal line 104 at the time of reading, and the write address before being latched by the address latch 108 at the time of writing.

The address comparison circuit 110 operates only at the time of reading, compares the output of the address latch 108 with the address of the address signal line 111, and outputs a coincidence signal to the control circuit 11.
Output to 2. The address comparison circuit 110 is latched by the data latch 106 at the time of reading, and the static RAM 1
The read control of the data not written in 01 is performed.

The operations of the address latch, the address selection circuit, and the address comparison circuit are controlled by the control circuit 112 in accordance with read, write, and read / write.

Regarding data control, data latch 1
Reference numeral 06 latches and holds write data on the data bus 105 during writing. Further, the write data previously latched by the data latch 106 is output to the write data signal line 103 and becomes the write data of the static RAM 101. The data latch 106 is composed of a master-slave two-stage latch, and the output does not change immediately after latching, but changes after the write operation of the static RAM 101 is completed. At the time of reading, the data latch 106 does not latch the data but holds the previously latched data.

The data selection circuit 107 is controlled by the coincidence signal of the address comparison circuit 110 and the control signal of the control circuit 112, and outputs data to the data bus 105 at the time of reading. The data output from the data selection circuit 107 is the data of the write data signal line 103 when the match signal is output from the address comparison circuit 110 during the read, and the read data signal line when the match signal is not output during the read. It is the data of 102. The operations of the data latch and the data selection circuit are controlled by the control circuit 112 in accordance with read, write, and read / write.

The static RAM 101 comprises a control circuit 1
Controlled by 12, access to the address of the RAM address signal line 104 is performed. At the time of reading, the read data is output to the read data signal line 102. At the time of writing, the data on the write data signal line 103 is written.

In the memory circuit of this embodiment, the write data is temporarily latched by the data latch 106, and the static RAM 101 writes the data latched in the data latch 106 before. Therefore, the data transfer can be performed in parallel with the write operation. It is possible. Therefore, while the conventional circuit requires three timings of reading, bus (data transfer), and reading, the operation can be performed at two or one timing of reading, data transfer, or writing. However, when writing data, the data to be written is latched by the data latch 106 and is not immediately written to the static RAM 101.
Data written in AM101 or data latch 1
It is necessary to determine whether or not the data is stored in 06 and perform the data read control.

Next, the timing of the memory circuit of the present invention shown in FIG. 1 will be described with reference to FIG. FIG. 2 is a timing chart of the memory circuit of this embodiment shown in FIG. At the time of reading, the data of the static RAM is read at the timing of 201. Next, the data read at the timing of 202 is transferred via the data bus. At the time of writing, data is written in the static RAM at the timing of 211. In a processor or the like, it is easy to change the timing of the static RAM according to reading and writing, and if the two timings of the reading timing 201 and the data bus (data transfer) timing 202 are set to the writing timing 211, the reading is performed. , Bus (data transfer), and writing can be controlled at two timings.

As can be seen from FIG. 2, in the memory circuit shown in FIG. 1, at the time of writing, the data latch 106 latches the data transferred by the data bus 105, and the static RAM 101 stores the data previously latched in the data latch 106. Write. With this function, at the time of writing, the static RAM 101 can perform the writing operation without waiting for the data on the data bus 105. Read, data bus (data transfer) or write 2
The control can be performed at one or one timing. Therefore, the memory and the data bus can operate at a lower speed than the conventional example. In particular, with regard to writing to the memory, it is possible to operate at a significantly lower speed than before. Further, high speed operation of the memory circuit and the bus can be easily realized.

[0022]

As described above, according to the present invention,
Both the memory and the data bus can operate at low speed, and low power consumption operation can be realized. Further, it is easy to realize high-speed operation, and there is an effect that it is suitable for a semiconductor integrated circuit.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a memory circuit according to an embodiment of the present invention.

FIG. 2 is a timing diagram of a memory circuit according to an embodiment of the present invention.

FIG. 3 is a configuration diagram of a conventional memory circuit.

FIG. 4 is a timing diagram of a conventional memory circuit.

[Explanation of symbols]

 101 static RAM 102 read data signal line 103 write data signal line 104 RAM address signal line 105 data bus 106 data latch 107 data selection circuit 108 address latch 109 address selection circuit 110 address comparison circuit 111 address signal line 112 control circuit 201 write timing 202 Bus (data transfer) timing 211 Write timing 301 Static RAM 302 Read data signal line 303 Write data signal line 304 Address signal line 305 Data bus 306 Control circuit 401 Read timing 402 Bus (data transfer) timing 403 No execution timing 411 What Not executed 412 Bus (data transfer) timing 413 Read Timing

Claims (1)

[Claims] 1. A static RAM for storing data,
Of the read data signal line for outputting the read data of the static RAM, the write data signal line for inputting the write data of the static RAM, the RAM address signal line for inputting the address of the static RAM, and the address signal line at the time of writing. An address latch that holds a write address, an address that is connected to the address latch and the address signal line, selects an output of the address latch when writing, selects an address signal line when reading, and outputs the selected address to the RAM address signal line A selection circuit, an address comparison circuit connected to the address latch and the address signal line, an address comparison circuit that compares an address held in the address latch at the time of reading with an address of the address signal, and outputs a match signal to a control circuit, and data. A data bus for sending, a data latch for holding the write data of the data bus at the time of writing and outputting the write data held in the write data signal line, and a read data signal line and the write data signal line connected at the time of reading When the match signal is output from the address comparison circuit, the data on the write data signal line is selected, and when the match signal is not output on the read, the data on the read data signal line is selected and selected to the data bus. A data selection circuit for outputting data, and a control circuit for controlling the static RAM, the data latch, the data selection circuit, the address latch, the address selection circuit, and the address comparison circuit according to a read / write state. Memory circuit characterized by.