JPH0614541B2 - Photoelectric conversion device and manufacturing method thereof - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a photoelectric conversion device employing a static induction transistor structure and a method for manufacturing the same.

[Prior Art and its Problems] Conventionally, as a transistor type photoelectric conversion device, a bipolar type and a field effect type have been put into practical use. Recently, the SIT (Static Induction Transis
ter; static induction transistor) type image sensor
(IEEE Trans on Electron Devices Vol.ED-26, No.12
(Dec.1979) pp, 1970-1977).

An electrostatic induction transistor is used as a photoelectric conversion unit in this image sensor. The electrostatic induction transistor as the photoelectric conversion device will be described below. The photoelectric conversion in the static induction transistor is mainly performed in the vicinity of the second conductivity type region on the first main surface side, and the potential of the second conductivity type region changes in proportion to the incident amount of light. Controlling the current flowing between the first main electrode region formed of the conductive layer formed through the extremely thin oxide film and the second main electrode region on the second main surface side in accordance with the change in the potential. . That is, the current flowing between the first main electrode region and the second main electrode region is controlled in proportion to the amount of incident light. Regarding its specific manufacturing method, Japanese Patent Application No. 57-218589, Japanese Patent Application No. 57-218590.
The invention is disclosed in Japanese Patent Application No. 57-218591 and Japanese Patent Application No. 57-218591. The Japanese Patent Application No. 57-218589 relates to a method for manufacturing the SIT image sensor having the simplest planar structure,
FIG. 2 shows the main part of the manufacturing process. Less than,
The prior art will be described with reference to the drawings. In FIG. 2, (A) n ⁺ buried layer 2 on n ⁺ substrate or p ⁻ substrate
After the formation of B, a high resistance n ^- epitaxial growth 3 (which may be any of n ⁻ , p ⁻ , i) and ion implantation or diffusion of boron B into the field oxide film 7 and the control gate 6 are carried out. ) And drive-in.

(B) A predetermined source portion 5 is opened by a mask aligning process, and a doped polysilicon 8 of phosphorus P or arsenic As or a non-doped polysilicon 8 is deposited by CVD (Ch
Emical Vapor Deposition: One of vapor deposition methods) Deposit by technology and dope phosphorus P or arsenic As to drive in.

(C) After etching by mask alignment leaving the source electrode portion 8 and the wiring portion 8 made of polysilicon,
PSG (Phospho-Silicate Glass) film 9
Are formed by CVD.

(D) After removing the field oxide film 7 and the PSG film 9 above the control gate portion 6 by mask alignment, the CVD of the nitride film 10 and the transparent electrode SnO ₂ 1
MI for accumulation in the upper part of the control gate 6 by performing CVD of 1
An S (Metal Insulator Semiconductor structure; metal electrode-thin insulator-semiconductor structure) capacitor is formed.

(E) SnO above the control gate 6 and wiring
A contact hole to the shielding gate portion 4 is opened while leaving only ₂ films 11 by mask alignment and etching process.

Finally, Al vapor deposition and wiring etching are performed. Al electrode
12 is in contact with the SnO ₂ electrode. Al electrode 13
Is an Al electrode for contact with the shielding gate 4.

As is clear from the above description, in the manufacturing method disclosed in Japanese Patent Application No. 57-218589, passivation (Passivation;
7 masks are required except for surface stabilization technology)
In addition, the n ⁺ source portion 5 and the p ⁺ gate portions 4 and 6 are
They are formed by different masks by different mask alignment steps. In response to this manufacturing method, the present inventors have proposed a self-alignment process for a SIT image sensor in which a mask for defining the n ⁺ source portion 5 and the P ⁺ gate portion is provided by one sheet, and Japanese Patent Application No. 57-218590 is proposed. Disclosed. The final sectional structure is shown in FIG.

Next, the manufacturing process of the device shown in FIG. 3 will be briefly described. After forming the n ⁺ buried layer 2 on the n ⁺ substrate or on the p ⁻ substrate 1, after n ⁻ high resistance epitaxial growth 3 (this can be n ⁻ , p ⁻ , i), LOCOS (Localized
Oxidation of Silicon; a selective oxidation structure of a silicon substrate using a silicon nitride film) technology is used to form regions to be the source parts and gate parts 4, 6 of the SIT. That is, the thick oxide film 7 of LOCOS is covered except for the regions to be the source portion 5 and the gate portions 4 and 6 of the SIT. Area to be the gate after mask alignment process
The Si ₃ N ₄ films on 4, 6 are removed, and boron B ion implantation and heat treatment steps are performed to form the gate portions 4, 6 of the SIT.

Next, after the mask aligning step, the Si ₃ N ₄ film and the SiO ₂ film on the region 5 to be the source portion are removed, n ⁺ doped polysilicon 8 is entirely formed by the CVD technique, and a heat treatment step is performed to n ^+. The source diffusion region 5 is formed. The n ⁺ polysilicon 8 is etched to form a wiring portion. Next, after the PSG film is grown by CVD, the SiO ₂ film on the control gate region 6 is removed by a mask alignment process. After Si ₃ N ₄ having a predetermined thickness is entirely formed by the CVD technique, the SnO ₂ film 11 is further grown by CVD. Above SnO ₂ 11 / Si ₃ N ₄ 10 / Si
An MIS structure is formed on the control gate 6 by the (p ⁺ ) 6 structure. After etching the SnO ₂ film 11, a contact hole to the shielding gate portion 4 is opened and Al vapor deposition sintering is performed. Excluding passivation, 7 masks are required up to the Al electrode wirings 12 and 13.

In the manufacturing process of the SIT image sensor pixel having the structure shown in FIG. 3, the positions of the source 5, gates 4 and 6 are defined by the first mask, so that compared with the manufacturing method shown in FIG. Variations among the source, gate, and gate can be suppressed. However, the number of masks required for both the method of FIG. 2 and the method of FIG. 3 is 7 in the method of FIG. 3 because the positions of the gates 4 and 6 and the source 5 of the SIT are the first. This is because the diffusion process of the gates 4 and 6 and the source 5 is performed by using different masks, and is the same when the SnO ₂ film 11 on the control gate 6 is etched later. Since all the masks are used, it is the total number of masks. Since the formation of the gate portions 4 and 6 and the formation of the source portion 5 are performed in separate processing steps,
It has the drawback that it is weak against variations in characteristics.

The present inventors further disclose another manufacturing method of the SIT image sensor in Japanese Patent Application No. 57-218591. The final cross-sectional shape of the device is shown in FIGS. 4 (A) and 4 (B). The feature of the manufacturing method shown in this figure is that LOCOS or plasma etching + LOCOS technology is used to deeply form the shielding gate portion 4. In FIG. 4 (A), the shielding gate portion 4 is formed. 4, control gate part 6
In this example, the p ⁺ gates 4 and 6 are deeply diffused by the LOCOS technique, and the position of the n ⁺ source region 5 is determined by mask alignment. That is, it is not self-aligned. In the structure shown in FIG. 4B, the p ⁺ gate diffusion 4 is deeply formed in the shielding gate portion 4 by using plasma etching and the LOCOS technique, and the p ⁺ control gate 6 diffusion positioning and the n ⁺ source portion 5 are formed. The positioning of diffusion is performed by mask alignment using separate masks.

In FIG. 4 (A), the total mask diffusion is 7 excluding passivation, and in FIG. 4 (B), it is 7 to 8.

As described above, there are four methods of manufacturing the SIT image sensor which have been disclosed and proposed by the present inventors. Second
In the manufacturing method shown in the figure, the gate diffusion and source diffusion of the SIT are positioned by the mask alignment process using different masks, so when a large number of cells are arranged in a matrix, the sensitivity characteristics between pixels vary widely. There is a drawback to say. However, since the final structure of the device is flat, it is advantageous in increasing the light receiving efficiency. In the manufacturing method described with reference to FIG. 3, the positions of the gate and the source of the SIT are defined by the first mask, so that the dimensional variation is far suppressed as compared with the method shown in FIG. However, a thick oxide film by the LOCOS process exists between the SIT gate and source, and the transmittance of light to the SIT channel is poor. Also, due to the effect of the oxide film due to LOCOS, the device surface has an uneven shape,
Light is scattered due to the uneven shape, which makes it difficult to effectively incorporate the light into the device. Further, since the gate diffusion and the source diffusion are eventually performed by different mask alignment, the total number of masks is 7, which is the same as in the case of FIG. In the manufacturing method described in FIG. 4 (A), since the p ⁺ gate diffusion is performed under the thick oxide film of LOCOS at the same time as the oxidation of LOCOS technology, the light receiving surface is uneven and the source region is Positioning is performed by mask alignment, and variations in the positions of the source diffusion regions have a large adverse effect on the characteristics of the solid-state imaging device in which a plurality of cells are finally arranged. Further, in the method of manufacturing the SIT image sensor described in FIG. 4B, since the control gate diffusion and the source diffusion are positioned by the mask alignment process, the channel width variation, the source-gate dimension, and the like. Is likely to occur, and when a plurality of cells are arranged in a matrix, the characteristics of each pixel greatly vary.

As described above, in the method shown in FIGS. 2 and 4 (A) and (B), the gate and source positions are determined separately in the mask alignment process, which causes variations in characteristics between elements. There was a flaw.

Further, in the method shown in FIG. 3, the device surface becomes uneven, and the source diffusion and the gate diffusion are performed separately, so there are variations in that amount, and there is the drawback that the light absorption efficiency is poor.

In addition, considering the total number of masks,
In both of the preceding examples of FIGS. (A) and (B), the number is 7 to 8.

[Object of the Invention] It is an object of the present invention to provide a novel SIT photoelectric conversion device and a manufacturing method thereof in which the above-mentioned drawbacks of the prior art are eliminated.

[Summary of the Invention] Therefore, the present invention is characterized in that the source region has a tunnel injection structure in the electrostatic induction transistor type photoelectric conversion device.

[Embodiment of the Invention] FIGS. 1 (A) to 1 (G) show respective manufacturing steps of a method for manufacturing a SIT photoelectric conversion device according to an embodiment of the present invention. Below, the same manufacturing process
(A) to (G) will be described step by step.

(A) n ⁺ high-resistance epitaxial growth layer 3 on substrate 2
Is performed to a thickness of about 5 μm to 10 μm. The conductivity type of this epitaxial growth layer 3 may be either n ⁻ or p ⁻ . It may also be an i-layer. Next, Wet oxidation is performed on the entire surface. The field oxide film 7 has a thickness of about 5000Å to 8000Å.

Next, by the first mask alignment step, the regions of the gate and tunnel injection portions of the SIT photoelectric conversion device are determined, and the window of the field oxide film is opened by etching. Next, an extremely thin oxide film 15 is formed on the entire surface by dry oxidation. The thickness of the oxide film 15 is about 10Å to 100Å. A thermal nitride film may be used instead of the extremely thin oxide film 15.

Further, before forming the extremely thin oxide film 15, ion implantation may be performed in order to control the final impurity concentration value of the channel region immediately below.

Next, a conductive layer 14 of (doped or non-doped) polysilicon, refractory metal (Mo, W, etc.), or silicide is formed on the entire surface by using a technique such as electron beam evaporation or sputtering.

(B) Next, by the second mask aligning step, leaving the conductive layer 14 in the region to be the source portion of the tunnel injection structure,
The remaining portion is removed by etching. After that, using this conductive layer 14 as a mask, an extremely thin oxide film is etched to open windows where the shielding gate and control gate regions should be and expose the Si surface in those regions.

Next, boron B is ion-implanted on the entire surface to form p ⁺ ion-implanted layers (hereinafter referred to as p ⁺ diffusion layers) 4, 6 in the shielding gate region 4 and the control gate region 6.

(C) Next, an insulating film 9 such as a PSG film or a CVDSiO ₂ film having a thickness of 3000 Å is formed on the entire surface, and then the heat treatment of ion implantation performed in (B) is performed. The impurity density near the surface of the p ⁺ diffusion layers 4 and 6 is about 1 × 10 ¹⁹ cm ⁻³ , and the diffusion depth of the p ⁺ diffusion layers 4 and 6 is about 1 μm to 5 μm.

(D) Next, a PSG film (or CV) for opening a window to the control gate region 6 is formed by the third mask alignment process.
Plasma etching of the DSiO ₂ film 9 is performed to expose the Si surface on the p ⁺ control gate region 6.

(E) Next, the Si ₃ N ₄ film 10 is formed on the entire surface by the CVD technique. The thickness is about 500Å ~ 1000Å. CVDSi ₃ N ₄
After forming the film, SnO ₂ or ITO (indium oxide,
A transparent electrode 11 such as a tin oxide film is formed by using a technique such as CVD and a control gate electrode is formed. A SnO ₂ transparent electrode 11 is formed by using a technique such as CVD and a control gate electrode is formed. As a method of forming the SnO ₂ transparent electrode 11, a CVD technique by thermal decomposition (400 to 600 ° C.) of SnCl ₄ using SbCl ₃ as a doping source in N ₂ carrier is used.

(F) SnO ₂ portions 11 on the control gate region and, after the plasma etching the SnO ₂ electrode 11 while leaving the SnO ₂ 11 of the wiring portion, shielding gate region 4, a further contact hole in the conductive layer 14 to open Perforate (4th, 5th
Step of masking, but the opening of the contact hole to the conductive layer 14 is not shown). In SnO ₂ plasma etching, CCl ₄ gas is used at 0.1 torr. Further, an Al electrode is formed on the entire surface by vapor deposition, and an Al wiring portion for contact with the conductive layer 14 serving as a predetermined source electrode (not shown) and an Al wiring portion for contact 13 and SnO ₂ 11 of the seal dig gate 4 are formed. Etching of Al is performed while leaving the Al wiring portion 12 for contact with. Further, after sintering, a final passivation step such as CVD growth of the Si ₃ N ₄ film is performed (sixth and seventh mask aligning steps).

Next, the operation of the photoelectric conversion device manufactured through the above steps (A) to (F) is shown as the first (F) showing the final device cross-sectional shape.
Will be explained.

First, it is assumed that there is no accumulation of photocarriers in the P ⁺ region of the control gate 6 in the absence of light. In order to use the electrostatic induction transistor as a photoelectric conversion device, the impurity density of the n ⁻ region 16 which becomes a channel is approximately 1 × 10 ¹⁶ cm 2.
^-3 or less, and the impurity density of the gate, source and drain regions is set to approximately 1 × 10 ¹⁸ cm ^-3 or more. In order that the drain-source current does not flow even if the gate voltage is 0 V, the dimensions and the gate interval are selected so that the gate-to-gate and the channel are already depleted only by the diffusion potential. The potential distribution in the device thickness direction immediately below the p ⁺ region of the control gate 6 is a junction in which a diode is formed between the gate region 4 and the Si n ⁺ substrate 14 with a high potential on the surface side (p layer side). There is. Also, the source region 14
The potential distribution in the device thickness direction immediately below is equal unless the voltage of the drain 17 and the source 14 is applied, and the potential has a maximum value at a certain point (called a true gate) between both regions. Therefore, even if a voltage is applied between the source 14 and the drain 17, the tunnel current, that is, the drain current is not pinched off due to the expansion of the depletion layer due to the barrier and does not flow. Moreover, even if a pulse voltage is applied to the gate electrode 11 without applying a voltage between the source 14 and the drain 17, the current does not flow (such an operating state is called “normally off”, and the opposite state is “normally on”). Call). Of course, by changing the element size, it is possible to prevent the current from flowing even when light is irradiated with either the gate pulse voltage or the source-drain voltage applied, or to allow it to flow. You can also That is, in the photoelectric conversion device using the static induction transistor, the source 14,
With the voltage applied between the drains 17, the true gate potential formed immediately below the source 14 is set to a certain value. In this state, the control gate 6 is irradiated with light, and holes, which are one of the photoexcited charges, are accumulated in the p ⁺ region immediately below according to the amount of light, and the potential of the gate 6 p ⁺ region changes according to the amount of light. Therefore, the true gate potential is lowered from the previous state according to the change in the gate potential,
As a result, for the first time, a drain-source current flows beyond the potential barrier. After that, a pulse voltage is applied to the gate electrode 11 to perform the next photometry, and the gate electrode 1
1, the voltage is measured according to the gate capacitor formed by the Si ₃ N ₄ film 10 and the like, and in terms of an equivalent circuit to the gate capacitor, it is formed in series from the control gate 6p ⁺ region toward the drain electrode 17. Since the diode junction capacitance (C _DS ) is connected, the applied pulse voltage is partly divided by the gate capacitor and the diode junction capacitance (C _DC ) and then applied to the terminal voltage of the diode. It As a result, since the diode is heavily charged, the gate 6p ⁺ region is returned to the initial state, and photometry can be repeatedly performed. Furthermore, by externally applying a voltage to the shielding gate 4 region, the current flowing through the source 14 and the drain 17 can be freely controlled.

The above is the description of the operation of the photoelectric conversion device according to the present invention, but according to the above-described method for manufacturing the photoelectric conversion device of the present embodiment, since the tunnel injection structure is adopted for forming the source region, the diffusion holes in the source region can be formed. The manufacturing process is extremely simple because it is unnecessary. At the same time, the occupied area of the source region and the gate region can be minimized to the limit of the fine processing technology. Also, the number of masks is reduced by one compared with the manufacturing process according to the prior art shown in FIG. In addition, the source region having the tunnel injection structure, the shielding gate and the control gate region are simultaneously determined by the second mask process, and the diffusion (ion implantation) for forming the transistor is performed only once. The channel dimensions of the SIT portion constituting the above, the distance between the shielding gate region 4, the control gate region 6 and the source region are all made uniform. Therefore, the characteristics of the tunnel injection type SIT photoelectric conversion device manufactured according to the present embodiment are made uniform, the variation of the output characteristics with respect to the received light intensity of light is suppressed to a very low level, and a high yield can be expected from an industrial viewpoint.

In addition, the Si surface is on the same plane and is flattened, so that the ratio of scattering by unevenness on the semiconductor surface when receiving light is smaller than in the conventional manufacturing method.

Furthermore, compared to the conventional manufacturing method, it is extremely simple, and since source diffusion is not required in particular, the higher density that SIT has in the past is further advanced, and the source length can be made longer in the same area. High output is possible.

Although the tunnel injection gate storage type SIT photoelectric conversion device having the gate divided into the shielding gate region 4 and the control gate region 6 has been described in the above embodiment, an insulator or a junction may be used instead of the shielding gate region 4. You may use the guard ring by. At that time, since only the control gate region 6 becomes the gate region of the SIT, the structure of the SIT is such that the control gate region 6 surrounds the tunnel injection region. However, it is clear that the same process as the manufacturing process of the present invention can be applied.

In addition, in the above-mentioned embodiment, the PSG film or the CVD is used so that the wiring of the source electrode and the wiring of the gate electrode may intersect.
Although an example in which the SnO ₂ film 9 is formed is shown, it is apparent that the manufacturing process can be further simplified if the two wirings do not intersect with each other depending on how the mask pattern is designed.

It will be apparent to those skilled in the art that the conductivity types of the respective parts in FIG. 1 of the above-described embodiment may be completely opposite.

As described above, according to the present invention, the tunnel injection structure is adopted in the source region, and the source region, the shielding gate, and the control gate region are determined by using the same mask, and the diffusion process is performed only once. Since the device is manufactured only once, the uniformity between the elements is remarkably excellent, the sensitivity characteristics hardly vary, the yield is high, and the devices after manufacturing are flattened. A photoelectric conversion device with high sensitivity, high density and high output can be obtained.

[Brief description of drawings]

FIGS. 1 (A) to (F) are explanatory views of a manufacturing process of a SIT photoelectric conversion device according to an embodiment of the present invention, and FIGS. 2 (A) to (E) are prior examples of a gate storage type SIT photoelectric conversion device. And FIG. 3 and FIGS. 4 (A) and 4 (B) are structural sectional views showing another prior art example of the gate storage type SIT photoelectric conversion device. 2 ... n ⁺ substrate, 3 ... high-resistance epitaxial layer, 4 ...
… Shielding gate area of split gate SIT, 6 ……
Control gate region of the split gate SIT, 7 ...... field oxide electrode, 9 ...... PSG or CVD SiO ₂ film of the insulating film, 11 ...... transparent electrode, 12 ...... Al electrode portion, 13 Al contacts ...... shielding gate Electrodes, 14 ... Conductive film that will be the source electrode, 15 ... Very thin oxide film, tunnel injection region, 16 ... Channel region, 17 ... Drain electrode.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-53-57769 (JP, A) JP-A-59-107570 (JP, A)

Claims (2)

[Claims] 1. A static induction transistor type photoelectric conversion device formed on a substrate, comprising: a drain region of a first conductivity type and a high impurity density; a high resistance channel region formed on the drain region; A second conductivity type high impurity density control gate region and a shielding gate region formed in a part of the upper part of the channel region, and a source insulation of 10 to 100Å formed between the control gate region and the shielding gate region. A film and a conductive layer serving as a source region formed on the source insulating film,
A photoelectric conversion device comprising: a gate insulating film formed on the control gate region; and a gate electrode made of a transparent conductive layer formed on the gate insulating film. 2. A method of forming an electrostatic induction transistor type photoelectric conversion device on a substrate, comprising the steps of forming a high resistance epitaxial growth layer on a first conductivity type substrate and forming a field oxide film thereon. A step of forming a window in the area where the electrostatic induction transistor is to be formed by the first mask aligning step, forming a first insulating film of 10 to 100Å to be the source insulating film there, and then forming a conductive layer on the entire surface. Second
A step of forming a source region by etching away the other part of the conductive layer in the part which will be the source region of the static induction transistor by a mask alignment step, and forming the source region by using the source region as a mask. A step of removing the etching to open a window of the second conductive type shielding gate area and a control gate area forming area, a step of implanting ions in the area where the window is opened, and a second insulating film over the entire surface. To a predetermined thickness, the ion-implanted layer is activated to form a shielding gate region and a control gate region of the second conductivity type, and a third mask aligning step is performed to cover the upper portion of the control gate region. A step of opening the window by removing the second insulating film by etching, and forming a third insulating film to be a gate insulating film on the entire surface. The step of forming a conductive electrode material transparent to the electromagnetic wave to be detected on the entire surface of the third insulating film, and processing the conductive electrode material into a desired shape by a fourth mask matching step. A step of forming a control gate electrode by performing a step of forming a control gate electrode, a step of forming a hole at a predetermined position in order to establish conduction between the shielding gate region and the source region and the extraction electrode by a fifth mask aligning step, and the extraction electrode. Photoelectric conversion comprising a step of forming an electrode material for wiring and wiring on the entire surface, and a step of forming a passivation film after processing the electrode material into a desired shape by a sixth mask aligning step. Device manufacturing method.