JPH0622360B2 - Asynchronous read state transition holding circuit - Google Patents

Description

DETAILED DESCRIPTION [Table of Contents] Outline Industrial field of use Conventional technology Problems to be solved by the invention Means for solving the problems (i) First invention (ii) Second invention Action (i) ) First Invention (ii) Second Invention Example I. Correspondence between Embodiment and FIG. 1 (i) First Invention (ii) Second Invention II. First Embodiment (i) Configuration (ii) Operation III. Second embodiment IV. Modified Embodiment of the Invention [Outline] An asynchronous read state transition holding circuit for holding a large number of detection data and reading the data asynchronously, for the purpose of reducing the circuit scale, is detected by N state detection units. The state detection data is multiplexed by the multiplexing unit and transmitted. N in the received multiplexed data
The separation unit separates the bits in units of L bits.
An address signal for each access cycle is output in synchronization with this separation, and a read control signal and an output inhibit signal are output in the first half cycle of each access cycle, and a write control signal and an output enable signal are output from the control signal generation circuit in the second half cycle. To do. In the first half cycle of each access cycle,
In response to the read control signal and the address signal, L-bit data is read from the dual port memory and held in the holding circuit. The retained L-bit data and the L-bit data separated by the separation unit are logically ORed by corresponding bits for each corresponding bit, and in the latter half cycle of each access cycle, a write control signal and an address signal are obtained. In response, it is configured to write to the dual port memory.

[Industrial application field]

The present invention relates to an asynchronous read state transition holding circuit, for example, holding alarm detection data of a large number of state detection units,
The present invention relates to an asynchronous read state transition holding circuit used when an alarm is read out by asynchronously reading this.

[Conventional technology]

Conventionally, such an asynchronous read state transition holding circuit has a state detection unit that detects a large number of alarm signals, for example, 1024. Even when an alarm is displayed based on the state detecting unit, the alarm signal detected by the state detecting unit cannot be overlooked even when the alarm signal is restored to normal before reading the alarm signal. Therefore, when an alarm signal is detected, it must be held until it is read.

Therefore, the alarm signal detected by the state detection unit is held by the state transition holding circuit until the reading is completed, and this is read asynchronously to display an alarm.

A small-scale circuit configuration is desirable for the asynchronous read state transition holding circuit used in such a case and having many state detection units.

FIG. 5 shows a conventional asynchronous read state transition holding circuit. This asynchronous read state transition holding circuit includes N state detection units 511 (state detection units 511 _{1 to} 511 _N ), where the state detection units 511 are installed and where the state is read. Is usually away from. Therefore, the N-bit state detection data detected by the _N state detection units 511 _{1 to} 511 _N are multiplexed by the multiplexing unit 513 and sent to the demultiplexing unit 515 to be demultiplexed into N-bit data. Each of the N-bit data thus separated is held by each of the eight state holding circuits 517 that hold the state in 1-bit units. Then, the data is sent to the 3-state buffer 519 in units of 8.

When reading these data, a read control signal is sent to each of the 3-state buffers 519 to read them in 8-bit units. After the reading, the clear signal is sent to each read state holding circuit 517 to clear.

In this way, the state transition data is read asynchronously.

It should be noted that the reason why the data is read in units of 8 bits is that the bus is usually 8 bits when a computer is used, and this is matched with that.

[Problems to be solved by the invention]

By the way, in the above-described conventional circuit, for example, if the number of state detecting units 511 is 1024 (N = 1024), the number of state holding circuits 517 and the number of 3-state buffers 519 will be correspondingly 1024. Therefore, there is a problem that the circuit scale becomes extremely large when the number of state detection units 511 is large.

The present invention was created in view of the above point, and an object thereof is to provide an asynchronous read state transition holding circuit having a small circuit scale.

[Means for solving problems]

FIGS. 1A and 1B are block diagrams of the principle of the asynchronous read state transition holding circuit of the present invention.

(I) First Invention In FIG. 1 (a), each of the N state detecting units 111 detects a state and outputs bit data according to the detected state.

The multiplexing unit 113 multiplexes the N-bit state detection data output from the N state detection units 111.

The demultiplexing unit 115 receives the N-bit data multiplexed by the multiplexing unit 113 and demultiplexes it into L-bit blocks.

The control signal generation circuit 127 outputs a sequential address signal 117 for each access cycle synchronized with the separation of the block of L bits, and outputs a read control signal 119 and an output prohibition signal in the first half cycle of each access cycle. , And outputs the write control signal 116 and the output permission signal in the latter half cycle.

The dual port memory 121 uses the read control signal 11
9 and the address signal 1 in response to the address signal 117.
Data written from the storage area designated by 17 is read from the read terminal, and the write signal supplied to the write terminal in response to the write control signal 116 and the address signal 117 is designated by the address signal 117. Write to storage.

The holding circuit 123 holds the L-bit data read from the dual port memory 121.

The L OR circuits 125 logically OR the L-bit data held in the holding circuit 123 and the L-bit data of one block output from the separating unit 115 at corresponding bits, In response to the output prohibition signal, the logical sum is added to the dual port memory 12
No output is made during reading from 1, and the logical sum is output to the write terminal of the dual port memory 121 in response to the output permission signal when writing to the dual port memory 121.

Due to these structural requirements, the L-bit data read from the dual port memory 121 in the first half cycle of each access cycle and held in the holding circuit 123 and the L-bit data separated by the separation unit 115 are ORed. The circuit 125 is configured to take a logical OR for each bit and write it to the dual port memory 121 in the latter half cycle of the access cycle.

(Ii) Second Invention Each of the N state detection units 111 detects a state and outputs bit data according to the detected state.

The state generation unit 112 outputs a predetermined coded multi-bit data.

The multiplexing unit 113 multiplexes N-bit state detection data output from the N state detection units 111 or multiple-bit data output from the state generation unit 112.

The demultiplexing unit 115 receives the N-bit data multiplexed by the multiplexing unit 113 and demultiplexes it into L-bit blocks.

The control signal generation circuit 127 outputs a sequential address signal 117 for each access cycle synchronized with the separation of the block of L bits, and outputs a read control signal 119 and an output prohibition signal in the first half cycle of each access cycle. , And outputs the write control signal 116 and the output permission signal in the latter half cycle.

The dual port memory 121 uses the read control signal 11
9 and the address signal 1 in response to the address signal 117.
Data written from the storage area designated by 17 is read from the read terminal, and the write signal supplied to the write terminal in response to the write control signal 116 and the address signal 117 is designated by the address signal 117. Write to storage.

The holding circuit 123 holds the L-bit data read from the dual port memory 121.

The L OR circuits 125 logically OR the L-bit data held in the holding circuit 123 and the L-bit data of one block output from the separating unit 115 at corresponding bits, In response to the output prohibition signal, the logical sum is added to the dual port memory 12
No output is made during reading from 1, and the logical sum is output to the write terminal of the dual port memory 121 in response to the output permission signal when writing to the dual port memory 121.

The control unit 127A determines that there is a plurality of bits of code data output from the state generation unit 112 according to the address signal 117, and controls so as to prohibit the data holding in the holding circuit 123.

Due to these structural requirements, the L-bit data read from the dual port memory 121 in the first half cycle of each access cycle and held in the holding circuit 123 and the L-bit data separated by the separation unit 115 are ORed. The circuit 125 takes a logical OR for each bit and writes it to the dual port memory 121 in the latter half cycle of the access cycle. However, it is an address signal that the data separated by the separation unit 115 is coded data. When judged, the data held in the holding circuit 123 is cleared, so that the data separated by the separation unit 115 is written to the dual port memory 121 as it is.

[Action]

(I) First Invention In the first invention configured as shown in FIG. 1 (a), one bit is detected by each of the N state detection units 111, and N-state detection data in total is obtained. The data is multiplexed by the multiplexing unit 113 and transferred.

The multiplexed state detection data is L
It is separated into blocks of bits.

The address signal 117 is generated in each access cycle in synchronization with the separation for each block unit, the read control signal 119 and the output inhibit signal are in the first half cycle of the access cycle, and the write control signal 1 is in the second half cycle.
16 and the output permission signal are output from the control signal generation circuit 127.

In the first half cycle of the access cycle (hereinafter referred to as the access cycle), that is, the read half cycle, the logical sum circuit 125 outputs a logical sum signal in response to the output prohibition signal supplied to the logical sum circuit 125. In the first half cycle, the control signal generating circuit 127
The holding circuit 123 holds the L-bit data read from the storage area of the dual port memory 121 designated by the address signal 117.

Further, in the first half cycle of the access cycle, the output of the OR signal from the OR circuit 125 is prohibited as described above. However, in the first half cycle, the first half cycle of the access cycle immediately before the access cycle. At the L-bit data read from the dual board memory 121 and held in the holding circuit 123, the separation unit 115 in the access cycle.
Logical sum with the L-bit data separated by
Taken at 25.

Then, in the latter half cycle of the access cycle, that is, the write cycle, the logical signal output from the logical sum circuit 125 in response to the output permission signal output from the control signal generation circuit 127 is the write control signal 116. And the dual port memory 121 in response to the address signal 117.
Is written to.

That is, in the first half cycle of the immediately preceding access cycle, the L-bit data read from the dual vote memory 121 and held in the holding circuit 123 and the L-bit data separated by the separating unit 115 in the access cycle are stored. The logical sum is the address signal 1 output from the control signal output circuit 127 in the access cycle.
It is written in the storage area of the dual port memory 121 designated by 17. In other words, the same state detection unit 11
The state detection data bit detected in 1 is written in the same write area of the dual port memory 121 while retaining its history.

(Ii) Second Invention The second invention configured as shown in FIG. 1 (b) differs from the first invention in the following points.

That is, when the control unit 127A determines from the address signal output from the control signal generation circuit 127 that the data separated by the separation unit 115 is coded data, the data of the holding circuit 123 The holding is prohibited, and the coded data can be written in the dual port memory 121 as it is.

By doing so, even if the coded data and the state detection data are mixed and multiplexed and separated, the data can be accurately transferred to the reading side.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 shows the configuration of an asynchronous read state transition holding circuit according to an embodiment of the present invention. FIG. 4 shows the configuration of an asynchronous read state transition holding circuit according to another embodiment of the present invention.

I. Correspondence between Embodiment and FIG. 1 (i) First Invention Here, the correspondence between the first embodiment of the present invention and FIG. 1 (a) will be shown.

The N state detection units 111 are the state detection units 211 _{1 to} 21 _1.
Equivalent to 1 _N.

The multiplexing unit 113 corresponds to the multiplexing 213.

The separation unit 115 corresponds to the separation unit 215 including the 8-bit shift register 221 and the 8-bit latch circuit 223.

The control signal generation circuit 127 corresponds to the control signal generation circuit 227.

The write control signal 116 is the read / write control signal 2
This corresponds to the write mode 43.

The address signal 117 corresponds to the address signal 241.

The read control signal 119 is the read / write control signal 2
This corresponds to the read mode 43.

The dual port memory 121 corresponds to the dual port memory 231.

The holding circuit 123 corresponds to the 8-bit latch circuit 229.

The L logical sum circuits 125 have OR circuits 225 _{1 to} 225.
₈ and 3 correspond to the OR circuit 230 composed of a state buffers ₂₂₆ 1 to 226 _8.

(Ii) Second Invention Next, the correspondence between the second embodiment of the present invention and FIG. 1 (b) will be shown.

The N state detection units 111 are the state detection units 211 _{1 to} 21 _1.
Equivalent to 1 _N.

The state generation unit 112 corresponds to the state generation unit 411.

The multiplexing unit 113 corresponds to the multiplexing 213.

The separation unit 115 corresponds to the separation unit 215 including the 8-bit shift register 221 and the 8-bit latch circuit 223.

The control signal generation circuit 127 corresponds to the control signal generation circuit 227.

The write control signal 116 is the read / write control signal 2
This corresponds to the write mode 43.

The address signal 117 corresponds to the address signal 241.

The read control signal 119 is the read / write control signal 2
This corresponds to the read mode 43.

The dual port memory 121 corresponds to the dual port memory 231.

The holding circuit 123 corresponds to the 8-bit latch circuit 229.

The L logical sum circuits 125 have OR circuits 225 _{1 to} 225.
₈ and 3 state buffers 226 _{1 to} 226 ₈ correspond to a logical sum circuit 230.

The control unit 127A corresponds to the clear control circuit 415.

An embodiment of the present invention will be described below on the basis of the above correspondence.

II. First Embodiment A first embodiment of the present invention shown in FIG. 2 will be described below.

(I) Configuration In FIG. 2, this asynchronous read state transition holding circuit has an N installed at a place distant from the place where the state is read.
Number of state detection unit 211 (the state detecting unit ₂₁₁ 1 to 21
1 _N ) is included. These N state detection units 211
The N-bit state detection data detected by is supplied to the multiplexing unit 213.

The data multiplexed by the multiplexing unit 213 is supplied to the separation unit 215 including the 8-bit shift register 221 and the 8-bit latch circuit 223. The N-bit data is separated into blocks of 8 bits (L bits) by the separating unit 215, and each of the 8 bits is supplied to each OR circuit 230 composed of an OR circuit 225 and a 3-state buffer 226. Supplied in parallel.

Each of the OR circuits 230 has one OR circuit 2
It consists of 25 and 3-state buffers 226. 8
The respective outputs of the OR circuits 230 are supplied so as to correspond to the data input terminals D _{0 to} D ₇ of the dual port memory 231 respectively.

Addresses A _{0 to} A of this dual port memory 231
_An address signal 241 is supplied to _N−1 , and a read / write control signal 243 is supplied to a data read / write control terminal (OE / WE) from a control signal generation circuit 227. In addition, the control signal generation circuit 22
7 outputs a clock signal 245 and supplies it to a clock input terminal CLK of an 8-bit latch circuit 229 formed by a flip-flop.

The data input terminals D _{1 to} D ₈ of the 8-bit latch circuit 229 are connected to the data input / output terminals D ₀ of the dual port memory 231.
The data read from D ₇ to D ₇ are introduced. In addition, the output terminal Q ₁ of the 8-bit latch circuit 229
To Q ₈ are input to one ends of the OR circuits 225 _{1 to} 225 ₈ forming the eight OR circuits 230.

The clear signal input terminal CLR of the 8-bit latch circuit 229 has a CPU (not shown) for performing operations such as reading data held in the dual port memory 231.
The clear signal 249 is supplied.

(Ii) Operation The operation of the first embodiment having the above-mentioned configuration will be described below.

The N-bit state detection data detected by the N state detection units 211 are multiplexed by the multiplexing unit 213 to be multiplexed data as shown in FIG. This multiplexed data is sent to the 8-bit shift register 221 of the demultiplexing unit 215, where it is demultiplexed into blocks of 8 bits (L bits) as shown in FIG. 3 (b). Each of the 8 bits is an 8-bit latch circuit 223.
Data of each bit latched by the OR circuit 225 (OR circuit 225 ₁
~ 225 ₈ ) respectively.

By the way, since the operation of the OR circuit 225 of each OR circuit 230 and the subsequent stage thereof is the same for each bit, the case of the data A ₀ in one OR circuit 225 ₁ will be described below as a representative example.

The control signal generation circuit 227 generates a clock (clock signal 245) to the 8-bit latch circuit 229 holding the previous data. 3 in the OR circuit 230
Against state buffers 226 _{1 to 226 8,} their outputs in a high impedance when being read data from the dual port memory 231, also, is a normal impedance when writing data to the dual port memory 231 Supply control signals.

The address 241 from the control signal generation circuit 227 is for N addresses A _{0 to} A _N−1 in 8-bit units. The read / write control signal 243 becomes a "read signal" in the read mode, and becomes a "write signal" in the write mode. Hereinafter, the read / write control signal 243 will be referred to as a "read signal" or a "write signal" depending on the mode.

The new data from the 8-bit latch circuit 223 is the third data
As shown in FIG. 6C, the OR circuit 225 is set every 8 bits.
Input to ₁ .

At this time, for example, an address A ₀ (see FIG. 3D) and a read signal (third signal) from the control signal generation circuit 227 are output.
In the figure (e)), the data (0 or 1) before being written in the address A ₀ of the dual port memory 231
Are read out as shown in FIG. After the reading, it is sent to the 8-bit latch circuit 229 to be latched, and the OR circuit 22 is delayed by a half cycle as shown in FIG.
5 Input to ₁ .

The output of the OR circuit 225 _1, as shown in FIG. 3 (h), in the first half of the half cycle, that the logical sum of the previous data A ₀ and data A ₀ is output. On the other hand, in the latter half cycle, the data A ₈ and the previous data A are
The logical OR of ₈ is output.

Therefore, this writing is performed by the control signal generating circuit 227 based on the address A ₀ to be written at the timing shown in FIG. 3D and the write signal to be written in the first half cycle shown in FIG. 3I. At this time, the control signal from the control signal generation circuit 227 controls the output impedance of the 3-state buffer 226 ₁ to be normal.

That is, writing to the dual port memory 231 does not write new data as it is and erases previous data, but takes the logical sum of the new data and the previous data, and the old "1" level data is It is read one after another. This is repeated M (= N / L) times so that the 8-bit latch circuit 229 is held and held until it is bought.

In this way, for example, 1024 bits are written in the address of 1024 in units of 8 bits. When the CPU reads the written data, the address signal 251 and the read signal 253 are input to the other port of the dual port memory 231 in 8-bit units. This allows asynchronous reading. When this reading is completed, the clear signal 249 is supplied to clear the 8-bit latch circuit 229.

In this way, the 8-bit shift register 221 has 6
Even if the number is four or more, the asynchronous read state transition holding circuit has eight OR circuits 225 ₁ to 2 after the separation unit 215.
25 ₈ , 8 3-state buffers 226 _{1 to} 22
The circuit scale can be reduced because it can be configured by 68, one dual port memory 231, an _8- bit latch circuit 229, and a control signal generation circuit 227.

It should be noted that although the description has been made in units of 8 bits in relation to the bus of the computer, this may be made in units of 2 bits, in which case the circuit scale will be further reduced.

III. Second Embodiment In the asynchronous read state transition holding circuit according to the first embodiment of the present invention described above, the detection state data “1” is written and held in the dual port memory 231, and is read by the read signal. It is what is retained.
As a result, the detection state data by the state detection unit 211 is kept held in the dual port memory 231. There, it is assumed that "0" is meaningless.

By the way, for example, after the coded data of “0010” in the state “1” is transferred and written in the dual port memory 231, the changed state “0” of “0” is written.
If you send the encoded data of "100", "011
0 ”is written in the dual port memory 231. That is, the data to be transferred is from“ 0010 ”to“ 010 ”.
Despite the change to "0", the obtained coded data becomes "0110", resulting in different data. This means that " 1 " of "00 1 0" to be transferred is once written. 8-bit latch circuit 2
It is caused by the fact that it is latched in 29, added to “0” in the OR circuit 230, written again in the dual port memory 231, and held. This is because it is premised that "0" is meaningless.

In this way, when "0" also has a meaning, the first
The asynchronous read state transition holding circuit of the embodiment cannot be used. For example, it is not possible to transfer information to the dual port memory 231 side after being multiplexed by the multiplexing unit 213, and to hold the information therein, which has meaning in a code (a group of a plurality of bits).

An asynchronous read state transition holding circuit applicable to the case where it is desired to transfer coded data as described above will be described next as a second embodiment.

(I) Configuration FIG. 4 shows an asynchronous read state transition holding circuit according to the second embodiment of the present invention. Here, what is structurally different from the first embodiment is that, in parallel with the state detection units 211 _{1 to} 211 _N ,
For example, a state generation unit 411 including a thumb rotary switch
Is provided and connected to the multiplexing unit 213, and a clear control circuit 415 that determines the generation timing of the clear signal 413 based on the address signal 241 from the control signal generation circuit 227 is newly provided. The clear control circuit 415 is composed of a ROM and has a clear trigger signal 417.
The clear signal 413 is output upon receiving (corresponding to the clear signal 249 in FIG. 2), and the address to which the "coded data" should be written in the dual port memory 231 is "0" in the clear control circuit 415. Is written. Others are the same as those in the first embodiment shown in FIG.

(Ii) Operation The operation of the second embodiment differs from that of the first embodiment in that when the coded data from the state generation unit 411 is transferred, the operation of the eight OR circuits 230 is performed. That is, the addition operation is not performed.

Now, assuming that the detection data from the state detection units 211 _{1 to} 211 _N and the coded data (for example, 4 bits) from the state generation unit 411 are supplied to the multiplexing unit 213, the multiplexing unit 213. The multiplexed signal output from is a data string in which "detection state data" and "coded data" are mixed. By the way, since the order in which "detection state data" and "coded data" appear in this multiplexed signal is known in advance, "0" is written in the clear control circuit 415 in accordance with the address.
If, in the clear control circuit 415, "0" is written in the address based on the address signal 241 output from the control signal generation circuit 227, the clear signal 413 is written.
Is output.

That is, according to the address, the clear control circuit 415 outputs the clear signal 413 to the 8-bit latch circuit 229 at the timing when the "coded data" appears in response to the clear trigger signal 417 supplied from the CPU on the reading side.
Supply to the clear terminal CLR. This clear signal 413
As a result, the data latched by the 8-bit latch circuit 229 is cleared. Therefore, 8-bit from the latch circuit 229 of the OR circuit 230 OR circuit ₂₂₅ 21 to
The outputs Q _{1 to} Q ₈ supplied to 25 ₈ are “0”.

Therefore, even if the previous data “detection state data” is held in the 8-bit latch circuit 229, the 8-bit latch circuit 229 is cleared when the “coded data” is transferred. The “data” is directly written in the dual port memory 231. Therefore, the CPU will later operate the dual port memory 2
Even if the data is read from 31, the coded data itself to be transferred can be obtained.

However, when only the "detection state data" is transferred and written, the clear signal 413 is supplied to the 8-bit latch circuit 229 to clear its holding, as in the case of the first embodiment. It is a thing.

IV. Modification of Invention In addition, in “I. Correspondence between Example and FIG. 1”,
Although the above-described embodiments and the present invention have been described in association with each other, the present invention is not limited to this, and those skilled in the art can easily contemplate that there are various modifications. .

〔The invention's effect〕

As described above, according to the present invention, an asynchronous read state transition holding circuit can be realized with a small-scale circuit configuration even when the number of state detection units is extremely large, which is extremely useful in practice. .

[Brief description of drawings]

FIG. 1 is a block diagram showing the principle of an asynchronous read state transition holding circuit of the present invention, FIG. 2 is a block diagram showing the configuration of an asynchronous read state transition holding circuit according to an embodiment of the present invention, and FIG. 3 is a book shown in FIG. FIG. 4 is an explanatory diagram showing the operation of the asynchronous read state transition holding circuit according to the embodiment of the invention, FIG. 4 is a block diagram of the configuration of an asynchronous read state transition holding circuit according to another embodiment of the present invention, and FIG. 5 is a conventional asynchronous read state transition holding circuit. It is an explanatory view of a circuit. In the figure, 111 is a state detection unit, 112 is a state generation unit, 113 is a multiplexing unit, 115 is a demultiplexing unit, 116 is a write control signal, 117 is an address signal, 119 is a read control signal, 121 is a dual port memory, 123 is a holding circuit, 125 is an OR circuit, 127 is a control unit, 211 and 511 are state detection units, 213 and 513 are multiplexing units, 215 and 515 are demultiplexing units, 221 is an 8-bit shift register, and 223 is 8 bits. Latch circuit, 227 is a control signal generation circuit, 229 is an 8-bit latch circuit, 230 is a logical sum circuit, 231 is a dual port memory, 411 is a state generator, 415 is a clear control circuit, 417 is a clear trigger signal, and 517 is a state. The holding circuit 519 is a three-state buffer.

Claims (3)

[Claims] 1. N state detectors (111) each of which detects a state and outputs bit data according to the detected state, and N output by the N state detectors (111). Multiplexing unit (113) for multiplexing bit state detection data
And a demultiplexing unit (1 that receives the N-bit data multiplexed by the multiplexing unit (113) and demultiplexes into L-bit blocks.
15) and outputting a sequential address signal (117) for each access cycle in synchronization with the separation of the L-bit block, and outputting a read control signal (119) and an output inhibit signal in the first half cycle of each access cycle. Then, the control signal generating circuit (127) which outputs the write control signal (116) and the output permission signal in the latter half cycle, the read control signal (119) and the address signal (11).
In response to 7), the data written from the storage area designated by the address signal is read from the read terminal and supplied to the write terminal in response to the write control signal (116) and the address signal (117). A dual port memory (121) for writing write data to a storage area designated by the address signal (117), and a holding circuit (123) for holding L-bit data read from the dual port memory (121) And the L-bit data held in the holding circuit (123) and the L-bit data of one block output from the separating unit (115) are ORed at corresponding bits, and the logical OR is performed. In response to the output prohibiting signal, the dual port memory (121) is not output during reading, and the dual port memory (1 1)
And a logical sum circuit (125) for outputting the logical sum to the write terminal of the dual port memory (121) in response to the output permission signal when writing to Characteristic asynchronous read state transition holding circuit. 2. A state detecting section (111) each of which detects a state and outputs bit data corresponding to the detected state, and a state generating section which outputs a predetermined coded multi-bit data. (112) and N-bit state detection data output from the N state detection units (111) or the state generation unit (112)
And a demultiplexing unit (113) for demultiplexing the multi-bit data output from the demultiplexing unit and a demultiplexing unit (N) for receiving the N-bit data multiplexed by the multiplexing unit (113) and separating the L-bit blocks 1
15) and outputting a sequential address signal (117) for each access cycle in synchronization with the separation of the block of L bits, and outputting a read control signal (119) and an output inhibit signal in the first half cycle of each access cycle. Then, the control signal generating circuit (127) for outputting the write control signal (116) and the output permission signal in the latter half cycle, the read control signal (119) and the address signal (11).
In response to 7), the data written from the storage area designated by the address signal (117) is read from the read terminal, and the write control signal (116) and the address signal (11) are read.
7) In response to 7), the write data supplied to the write terminal is written in the storage area designated by the address signal (117), and the read data is read from the dual port memory (121). A holding circuit (123) for holding L-bit data, the L-bit data held in the holding circuit (123), and one block of L-bit data output from the separating unit (115). The logical sum of the corresponding bits is taken, and the logical sum is not output during reading from the dual port memory (121) in response to the output prohibition signal, and the dual port memory (121)
When the data is written to, the logical sum is output to the write terminal of the dual port memory (121) in response to the output permission signal, and the logical sum circuit (125) is output from the state generation unit (112). The address signal (117)
And a control unit (127 A ) for controlling the holding circuit (123) so as to prohibit data holding in the holding circuit (123), and an asynchronous read state transition holding circuit. 3. The control section (127 A ) holds in the holding circuit (123) when one block of data output from the separating section (115) is the coded multi-bit data. The asynchronous read state transition holding circuit according to claim 2, characterized in that it is configured to clear the L-bit data that has been stored.