JPS64831A - Holding circuit for transition of asynchronous read out state - Google Patents

Holding circuit for transition of asynchronous read out state

Info

Publication number
JPS64831A
JPS64831A JP31684087A JP31684087A JPS64831A JP S64831 A JPS64831 A JP S64831A JP 31684087 A JP31684087 A JP 31684087A JP 31684087 A JP31684087 A JP 31684087A JP S64831 A JPS64831 A JP S64831A
Authority
JP
Japan
Prior art keywords
data
circuit
accordance
holding circuit
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP31684087A
Other languages
Japanese (ja)
Other versions
JPH01831A (en
JPH0622360B2 (en
Inventor
Noriyuki Yogoshi
Toshio Ikeda
Kazuyuki Miura
Hirotomo Miyawaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP31684087A priority Critical patent/JPH0622360B2/en
Publication of JPS64831A publication Critical patent/JPS64831A/en
Publication of JPH01831A publication Critical patent/JPH01831A/en
Publication of JPH0622360B2 publication Critical patent/JPH0622360B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE: To reduce circuit scale by adding data held in a holding circuit and data outputted from a circuit and writing data in a dual port memory in accordance with an address signal.
CONSTITUTION: Plural N-bit state detection data each of which is outputted by state detect ion are multiplexed and are demultiplexed into L-bit blocks by a demultiplexing circuit 115 and are written in the address indicated by an address signal 117 in accordance with a write control signal 116. This data is read out in accordance With a read control signal 119 and is held in a holding circuit 123. L-bit data held in the holding circuit 123 and L-bit data of one block outputted from the demultiplexing circuit 115 are added in an adding circuit 125 with respect to respective corresponding bits, and data is written in a dual port memory 121 in accordance with the address signal based on the addition result.
COPYRIGHT: (C)1989,JPO&Japio
JP31684087A 1987-02-03 1987-12-15 Asynchronous read state transition holding circuit Expired - Lifetime JPH0622360B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31684087A JPH0622360B2 (en) 1987-02-03 1987-12-15 Asynchronous read state transition holding circuit

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2283787 1987-02-03
JP62-22837 1987-02-03
JP31684087A JPH0622360B2 (en) 1987-02-03 1987-12-15 Asynchronous read state transition holding circuit

Publications (3)

Publication Number Publication Date
JPS64831A true JPS64831A (en) 1989-01-05
JPH01831A JPH01831A (en) 1989-01-05
JPH0622360B2 JPH0622360B2 (en) 1994-03-23

Family

ID=26360117

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31684087A Expired - Lifetime JPH0622360B2 (en) 1987-02-03 1987-12-15 Asynchronous read state transition holding circuit

Country Status (1)

Country Link
JP (1) JPH0622360B2 (en)

Also Published As

Publication number Publication date
JPH0622360B2 (en) 1994-03-23

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