JPH01831A - Asynchronous read state transition holding circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Conventional technology Problems to be solved by the invention Means for solving the problems (i) First invention (ii) Second invention action ( i) First invention (ii) Second invention embodiment ■, Correspondence between the embodiment and FIG. 1 (1) First invention (ii) Second invention ■, First embodiment (i') Configuration (ii ) Operation ■, Second Embodiment/■0 Modification of the invention Effects of the invention [Summary] Regarding an asynchronous read state transition holding circuit that holds a large amount of detected data and reads it out asynchronously, it is possible to reduce the circuit scale. N state detection sections each detecting a state and outputting bit data according to the detected state, a multiplexing section that multiplexes the output N-bit state detection data, and a multiplexing section. a separation unit that receives N-bit data and separates it into L-bit blocks; and a separation unit that receives N-bit data and separates it into L-bit blocks; A dual port memory that can be read from an address indicated by an address signal in response to a read control signal, a holding circuit that holds data read from the dual port memory, and data from the holding circuit and L bit from the separation section. The L adder circuits are configured to include L adder circuits that add the data in corresponding bits and write the added data into the dual port memory in accordance with the address signal.

[Industrial application field]

The present invention relates to an asynchronous read state transition holding circuit, for example, holding alarm detection data of a large number of state detection units,
The present invention relates to an asynchronous read state transition holding circuit used in cases such as when reading out this information asynchronously and displaying an alarm.

[Conventional technology]

Conventionally, such an asynchronous read state transition holding circuit has a state detection section that detects a large number of alarm signals, for example, 1024 alarm signals. Even when displaying an alarm based on the state detection section, the alarm signal detected by the state detection section cannot be overlooked even if the alarm signal returns to normal before being read. Therefore, once an alarm signal is detected, it must be held until it is read.

Therefore, the alarm signal detected by the state detection section is held in the state transition holding circuit until reading is completed, and is read out asynchronously to display the alarm.

A small-scale circuit configuration is desirable as an asynchronous read state transition holding circuit used in the case of 2, in which there are many state detection units.

FIG. 5 shows a conventional asynchronous read state transition holding circuit. This asynchronous read state transition holding circuit includes N state detecting sections 511 (state detecting sections 511. to 511N), and there is a location where these state detecting sections 511 are installed and a location where the state is read. are usually far apart. Therefore,
N-bit state detection data detected by the N state detection sections 5111 to 511N are multiplexed by a multiplexing section 513, sent to a separation section 515, and separated into N-bit data. Each of the N bits of data separated in this way has 8
The state holding circuits 517 each hold the data. Thereafter, they are sent to the three-state buffer 519 in units of eight.

When reading these data, a read control signal is sent to each of the three-state buffers 519, and the data is read in units of 8 bits. After reading, a clear signal is sent to each read state holding circuit 517 to clear it.

In this way, state transition data is read asynchronously.

Note that the reason why the data is read in 8-bit units is to match the 8-bit bus that is normally used when using a computer.

[Problem that the invention seeks to solve]

In the conventional circuit described above, for example, if there are 1024 state detection units 511 (N=1024), 1024 state holding circuits 517 and 3-state buffers 519 are required accordingly. Therefore, when there are many state detection units 511, there is a problem that the circuit scale becomes extremely large.

The present invention was created in view of these points, and an object of the present invention is to provide an asynchronous read state transition holding circuit with a small circuit scale.

[Means for solving problems]

FIGS. 1(a) and 1(b) are block diagrams of the principle of the asynchronous read state transition holding circuit of the present invention.

In FIG. 1(a), each of the N state detection units 111 performs state detection and outputs bit data according to the detected state.

The multiplexer 113 multiplexes the N-bit state detection data output from the N state detectors 111.

The demultiplexer 115 receives the N-bit data multiplexed by the multiplexer 113 and demultiplexes it into L-bit broncs.

The dual port memory 121 receives the L-bit data blocked by the separation unit 115 as the write control signal 11.
The written data can be written to the address indicated by the address signal 117 in response to the read control signal 119, and the written data can be read from the address indicated by the address signal 117 in response to the read control signal 119.

The holding circuit 123 holds L-bit data read from the dual port memory 121.

The L adder circuits 125 combine the L bit data held in the holding circuit 123 and the 1 bit data output from the separation unit 115.
The data of L bits of the block are added to each corresponding bit, and based on the addition result, control is performed to write to the dual port memory 121 according to the address signal 117.

Therefore, as a whole, the data written in the dual port memory 21 is read out and held in the holding circuit 123,
The configuration is such that the held data and the data from the separation section 115 are added by L adder circuits 125 and then written to the dual port memory 121.

In FIG. 1(b), each of the N state detection units 111 performs state detection and outputs bit data according to the detected state.

The state generating unit 112 outputs predetermined encoded multi-bit data.

The multiplexer 113 multiplexes the N-bit state detection data output from the N state detectors 111 or the multiple-bit data output from the state generator 112.

Separation section 115 receives the N-bit data multiplexed by multiplexing section 113 and separates it into L-bit blocks.

The dual port memory 121 receives the L-bit data blocked by the separation unit 115 as the write control signal 11.
The written data can be written to the address indicated by the address signal 117 in response to the read control signal 119, and the written data can be read from the address indicated by the address signal 117 in response to the read control signal 119.

The holding circuit 123 holds L-bit data read from the dual port memory 121.

The L adder circuits 125 combine the L bit data held in the holding circuit 123 and the 1 bit data output from the separation unit 115.
The data of L bits of the block are added to each corresponding bit, and based on the addition result, control is performed to write to the dual port memory 121 according to the address signal 117.

The control unit 127 uses an address signal 117 to indicate that the code data is a plurality of bits output from the state generation unit 112.
The control is performed to prohibit the holding circuit 123 from holding data.

Therefore, as a whole, after multiplexing and separating the detected state data of the state detecting section 111 and the coded data from the state generating section 112, the data is written to the dual port memory 121, and the written data is read and held. After the data is stored in the circuit 123 and the data from the separation unit 115 is added, the data is stored in the dual port memory 12
It is configured to write to 1.

[For production]

In the first invention shown in FIG. 1(a), the N-bit state detection data from the N state detection sections 111 is multiplexed by the multiplexing section 113, and then The separation unit 115 separates the data into blocks of L bits.

Thereafter, the data is written into the dual port memory 121 in accordance with the address 117 in units of L bits in this block unit. This written data is read out and held in the holding circuit 123. The retained data and separation unit 115
After adding the data from L adder circuits 125, the data is written into the dual port memory 121 again.

In the second aspect of the invention shown in FIG. Part 11
After being multiplexed by 3, the demultiplexing unit 115 demultiplexes the data into blocks of L bits.

If the separated data includes coded data, the control unit 127 clears the holding circuit 123.

After that, address 11 is written every L bits in block units.
7 is written to the dual port memory 121. This written data is read out and stored in the holding circuit 1.
It is held at 23. After the held data and the data from the separation unit 115 are added by L adder circuits 125, the data is written into the dual port memory 121 again.

In the present invention, if the data is coded, the holding state of the holding circuit 123 is cleared, and the coded data and the read data from the dual port memory 121 are not added. The data is written to the dual port memory 121 as is. Therefore, coded data and N state detection units 111
Even if there is a mixture of detection state data and detection state data, it can be accurately transferred to the reading side.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of an asynchronous read state transition holding circuit in an embodiment of the present invention. Further, FIG. 4 shows the configuration of an asynchronous read state transition holding circuit in another embodiment of the present invention.

Here, the correspondence between the first embodiment of the present invention and FIG. 1(a) will be shown.

The N state detection units 111 include state detection units 2111 to 21
Corresponds to 1N.

The multiplexer 113 corresponds to the multiplexer 213.

Separation section 115 corresponds to separation section 215 consisting of 8-bit shift register 221 and 8-bit latch circuit 223.

Write control signal 116 is read/write control signal 2
This corresponds to No. 43 write mode.

Address signal 117 corresponds to address signal 241.

Read control signal 119 is read/write control signal 2
This corresponds to No. 43 read mode.

Dual port memory 121 corresponds to dual port memory 231.

Holding circuit 123 corresponds to 8-bit latch circuit 229.

The L adder circuits 125 include OR circuits 225I to 2258.
and 3-state buffer 226. This corresponds to the adder circuit 230 consisting of .about.2268.

Next, the correspondence between the second embodiment of the present invention and FIG. 1(b) will be shown.

The N state detection units 111 include state detection units 211, -21
Corresponds to 1N.

The state generating section 112 corresponds to the state generating section 411.

The multiplexer 113 corresponds to the multiplexer 213.

Separation section 115 corresponds to separation section 215 consisting of 8-bit shift register 221 and 8-bit latch circuit 223.

Write control signal 116 is read/write control signal 2
This corresponds to No. 43 write mode.

Address signal 117 corresponds to address signal 241.

Read control signal 119 is read/write control signal 2
This corresponds to No. 43 read mode.

Dual port memory 121 corresponds to dual port memory 231.

Holding circuit 123 corresponds to 8-bit latch circuit 229.

The L adder circuits 125 include OR circuits 225I to 2258.
and 3-state buffers 226I to 2268.

The control unit 127 corresponds to the clear control circuit 415.

Examples of the present invention will be described below assuming that the correspondence relationship as described above exists.

A first embodiment of the present invention shown in FIG. 2 will be described below.

In Figure 2, the asynchronous read state transition holding circuit has an N
state detection units 211 (state detection units 211. to 211N)
) is included. The N-bit state detection data detected by these N state detection sections 211 is supplied to the multiplexing section 213.

The data multiplexed by the multiplexer 213 is supplied to the separator 215, which includes an 8-bit shift register 221 and an 8-bit latch circuit 223. The N-bit data is separated into blocks of 8 bits (L bits) by this separating section 215, and each of the 8 bits is sent to each adder circuit 230 constituted by an OR circuit 225 and a 3-state buffer 226. Supplied in parallel.

Each of the adder circuits 230 includes one OR circuit 22
It consists of 5 and 3 state buffers 226. The outputs of the eight adder circuits 230 are supplied to data input terminals D0 to D of the dual port memory 231, respectively.

Address A of this dual port memory 231. ~AH
-1 is supplied with an address signal 241, and the data read/write control terminal (OE/WE) is supplied with a read/write control signal 243 from the control signal generation circuit 227. In addition, this control signal generation circuit 227
outputs a clock signal 245 and supplies it to a clock input terminal CLK of an 8-bit latch circuit 229 formed by a flip-flop.

Data input end of 8-bit latch circuit 229.

~D8 are adapted to receive data read from the data input/output terminals D0~D of the dual port memory 231. Further, output terminals Q and -Q of the 8-bit latch circuit 229 are connected to OR circuits 225 . ~225s is input at one end.

Further, the clear signal input terminal CLH of the 8-bit latch circuit 229 is supplied with a clear signal 249 from a CPU (not shown) that performs operations such as reading data held in the dual port memory 231. There is.

” Artificial hair making The operation of the first embodiment having the above-described configuration will be described below.

The N-bit state detection data detected by the N state detection sections 211 are multiplexed by the multiplexing section 213, resulting in multiplexed data as shown in FIG. 3(a). This multiplexed data is sent to the 8-bit shift register 221 of the separation section 215, where it is separated into blocks of 8 bits (L bits) each as shown in FIG. 3(b).

Each of the 8 bits is latched by the 8-bit latch circuit 223, and the data of each latched bit is sent to the OR circuit 225 of the adder circuit 230 (OR circuits 225, . . . 22).
5e) respectively.

Incidentally, since the operation of the OR circuit 225 of each adder circuit 230 and the subsequent stage thereof is the same for each bit, the case of D i A6 in one OR circuit 2251 will be described below as a representative example.

Note that the -1 control signal generation circuit 227 generates a clock (clock signal 245) to the 8-bit latch circuit 229 holding the previous data. 3 in the adder circuit 230
Control for the state buffers 2261 to 226B so that their outputs are at high impedance when data is being read from the dual port memory 231 and at normal impedance when writing data to the dual port memory 231. supply the signal.

The address 241 from the control signal generation circuit 227 is for N addresses A0 to AM-1 in 8-bit units. The read/write control signal 243 becomes a "read signal" in the read mode, and becomes a "write signal" in the write mode. Hereinafter, this read/write control signal 243 will be referred to as a "read signal" or a "write signal" depending on its mode.

The new data from the 8-bit latch circuit 223 is
As shown in Figure (C), OR circuit 225 is set every 8 bits.
It is input to I.

At this time, the control signal generation circuit 227 generates, for example, address A (see FIG. 3(d)) and a read signal (third
(see figure (e)), the previous data (0 or 1) written to address A0 of the dual port memory 231
is read out as shown in FIG. 3(f). After reading it, it is sent to the 8-bit latch circuit 229 to be latched, and the third
As shown in Figure (g), the OR circuit 225 is delayed by half a cycle.
Let I input.

This OR circuit 225. As shown in FIG. 3(h), in the first half cycle, the output is the logical OR of data AO and previous data A0. On the other hand, in the second half cycle, data A8 and previous data A8
The result of logical OR with is output.

Therefore, this writing is performed by the control signal generation circuit 227 based on the address 80 written at the timing shown in FIG. 3(d) and the write signal written in the first half cycle shown in FIG. 3(i). At this time, the output impedance of the three-state buffer 2261 is controlled by the control signal from the control signal generation circuit 227 so as to be normal.

That is, when writing to the dual port memory 231, the new data is not written as it is and the previous data is erased, but the new data and the previous data are logically ORed and the old 1° is written.

Level data is read out one after another. This is M (=N
/L) times, and is held and written until the 8-bit latch circuit 229 is cleared.

In this way, 1024 bits, for example, are written to 1024 addresses in 8-bit units. When the CPU reads the written data, it inputs the address signal 251 and read signal 253 in units of 8 bits to the other port of the dual port memory 231. This allows asynchronous reading. When the reading is completed, a clear signal 249 is supplied to clear the 8-bit latch circuit 229.

In this way, the 8-bit shift register 221 can be set to 6 bits.
Even if there are four or more asynchronous read state transition holding circuits, after the separation unit 215, eight OR circuits 225. ~22
5. , eight 3-state buffers 226 . ~226. ，
One dual port memory 231.8 bit latch circuit 229. Since it can be configured with the control signal generation circuit 227,
The circuit scale becomes smaller.

Note that although the explanation has been made in units of 8 bits due to the computer bus, this may also be in units of 2 bits, in which case the circuit scale will be further reduced.

l-Bead balance■ In the asynchronous read state transition holding circuit according to the first embodiment of the present invention described above, 1, which is the detected state data, is written and held in the dual port memory 231, and read out by the read signal. It shall be retained until the end of the term. As a result, the state data detected by the state detection section 211 continues to be held in the dual port memory 231.

It is based on the premise that "OPA is meaningless.

By the way, for example, "0010°° in state "1"
After transferring the encoded data and writing it to the dual port memory 231, the changed state 112 I
When you send coded data of "'0100'" of +, "'0110" is written to the dual port memory 231. In other words, the data you want to transfer is "ooio"
” to “0100°”, the resulting encoded data is 0110, resulting in different data.
0'' is once written, read out, latched by the 8-bit latch circuit 229, added to 0'' by the adder circuit 230, and written to the dual port memory 231 again to be held. caused by “0”.
This is because it is based on the premise that "°" is meaningless.

In this case, when "0" also has meaning, the asynchronous read state transition holding circuit of the first embodiment described above cannot be used.For example, for information that has meaning in a code (a group of multiple bits), After being multiplexed by the converting unit 213, it cannot be transferred to the dual port memory 231 side and held there.

An asynchronous read state transition holding circuit that can be applied when it is desired to transfer encoded data as described above will now be described as a second embodiment.

FIG. 4 shows an asynchronous read state transition holding circuit according to a second embodiment of the present invention. Here, the difference in configuration from the first embodiment is that in parallel with the state detection units 2111 to 211N,
For example, a status generating section 411 consisting of a thumb rotary switch
The clear control circuit 415 that determines the generation timing of the clear signal 413 based on the address signal 241 from the control signal generation circuit 227 is newly provided. This clear control circuit 415 consists of a ROM, and clear trigger signal 417
(corresponding to the clear signal 249 in FIG. 2) and outputs a clear signal 413, and the clear control circuit 415 sets "0" to the address where "coded data" is to be written to the dual port memory 231. is written.

Other aspects are the same as those of the first embodiment shown in FIG.

This second embodiment differs from the first embodiment in its operation in that when encoded data is transferred from the state generator 411, the eight adder circuits 230 This means that the addition operation is not performed.

Now, assuming that detection data from the state detection sections 2111 to 211N and coded data (for example, 4 bits) from the state generation section 411 are supplied to the multiplexing section 213, the output from the multiplexing section 213 is The multiplexed signal is a data string in which "detection state data" and "coded data" are mixed. By the way, in this multiplexed signal,
Since the order in which the "detection state data" and the "coded data" appear is known in advance, "'0°°" is written in the clear control circuit 415 in accordance with the address.

If II OII is written in the address based on the address signal 241 output from the control signal generation circuit 227 in the clear control circuit 415, the clear signal 413 is output.

In other words, in accordance with the address, the clear control circuit 415 transfers the clear signal 413 to the 8-bit latch circuit 229 at the timing when "coded data" appears in response to the clear trigger signal 417 supplied from the CPU on the reading side.
is supplied to the clear terminal CLR of. This clear signal 413
As a result, the data latched by the 8-bit latch circuit 229 is cleared. Therefore, from the 8-bit latch circuit 229 to the OR circuits 225I to 22 of the adder circuit 230,
The outputs Q1 to Q8 supplied to the circuit 58 become "0".

Therefore, even if the previous data "detection state data" is held in the 8-bit latch circuit 229, when the "coded data" is transferred, the 8-bit latch circuit 229 is cleared, so the "coded data" will be written to the dual port memory 231 as is. Therefore, the CPU later uses dual port memory 2.
31, the coded data itself that should originally be transferred is obtained.

However, when only the "detection state data" is transferred or written, the clear signal 413 is supplied to the 8-bit latch circuit 229 and its holding is cleared in the same manner as in the first embodiment. It is.

■, II.../l In addition, r [, Correspondence between Examples and Figure 1],
Although the above-mentioned embodiments and the present invention have been described in association with each other, those skilled in the art can easily imagine that the present invention is not limited to this and that there are various modifications. .

〔Effect of the invention〕

As described above, according to the present invention, an asynchronous read state transition holding circuit can be realized with a small-scale circuit configuration even when there are an extremely large number of state detection sections, so that the present invention is extremely useful in practice.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of an asynchronous read state transition holding circuit according to the present invention, FIG. 2 is a configuration block diagram of an asynchronous read state transition holding circuit according to an embodiment of the present invention, and FIG. 3 is a block diagram of the principle of an asynchronous read state transition holding circuit according to the present invention. An explanatory diagram showing the operation of an asynchronous read state transition holding circuit according to an embodiment of the invention, FIG. 4 is a configuration block diagram of an asynchronous read state transition holding circuit according to another embodiment of the present invention, and FIG. 5 shows a conventional asynchronous read B transition. FIG. 3 is an explanatory diagram of a holding circuit. In the figure, 111 is a state detection section, 112 is a state generation section, 113 is a multiplexing section, 115 is a separation section, 116 is a write control signal, 117 is an address signal, 119 is a read control signal, 121 is a dual port memory, 123 is a holding circuit, 125 is an addition circuit, 127 is a control section, 211.511 is a state detection section, 213.513 is a multiplexing section, 215.515 is a separation section, 221 is an 8-bit shift register, 223 is an 8-bit latch circuit , 227 is a control signal generation circuit, 229 is an 8-bit latch circuit, 230 is an adder circuit, 231 is a dual port memory, 411 is a state generation section, 415 is a clear control circuit, 417 is a clear trigger signal, 517 is a state holding circuit, 519 is a 3-state buffer.

Claims (3)

[Claims] (1) N state detection units (111
), a multiplexer (113) that multiplexes the N-bit state detection data output from the N state detectors (111), and a multiplexer (113) that multiplexes the N bits of state detection data output from the N state detectors (111); A separating unit (1) receives bit data and separates it into L bit blocks.
15), the L-bit data blocked by the separation unit (115) can be written to the address indicated by the address signal (117) in response to the write control signal (116), and the written Data is read control signal (119)
a dual port memory (121) that can be read from an address indicated by an address signal (117) in accordance with the address signal (117); and a holding circuit (123) that holds L-bit data read from the dual port memory (121). , Add the L-bit data held in the holding circuit (123) and the L-bit data of one block output from the separation unit (115) at their corresponding bits, and based on the addition result, The address signal (
117) said dual port memory (121) according to
An asynchronous read state transition holding circuit characterized in that it is configured to include L adder circuits (125) for controlling writing to. (2) N state detection units (111
), a state generation unit (112) that outputs predetermined coded multi-bit data, and N-bit state detection data output from the N state detection units (111) or the state generation unit (112)
a multiplexing section (113) that multiplexes multiple bits of data output from the multiplexing section (113); and a separating section (113) that receives the N-bit data multiplexed by the multiplexing section (113) and separates it into L-bit blocks. 1
15), the L-bit data blocked by the separation unit (115) can be written to the address indicated by the address signal (117) in response to the write control signal (116), and the written Data read control signal (119)
a dual port memory (121) that can be read from an address indicated by an address signal (117) in accordance with the address signal (117); and a holding circuit (123) that holds L-bit data read from the dual port memory (121). , Add the L-bit data held in the holding circuit (123) and the L-bit data of one block output from the separation unit (115) at their corresponding bits, and based on the addition result, The address signal (
117) according to said dual port memory (121)
The address signal (117) indicates that the code data is a plurality of bits output from the L adder circuits (125) and the state generator (112).
); and a control unit (127) that performs control to prohibit data retention in the retention circuit (123). (3) The control section (127) controls the separation section (115)
When one block of data output from the holding circuit (
Claim 2 characterized in that the L-bit data held in 123) is configured to be cleared.
The asynchronous read state transition holding circuit described in .