JPH06265601A - Semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] Regarding a semiconductor device having a built-in test circuit, the test circuit can be activated without providing a test circuit control signal input terminal as an external terminal. Increase the number of external terminals used during operation to achieve higher functionality. [Composition] When the input terminal 2 is opened, the input transistor 7 is turned off, the collector of the input transistor 7 becomes the power supply voltage VCC (H level), and the OR circuit 15
Is activated as a test circuit, and the output signal OUT
Is fixed to the H level, and the H level voltage value of the output signal OUT can be easily measured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a test circuit built therein.

[0002]

2. Description of the Related Art FIG. 7 is a diagram showing an essential part of an example of a conventional semiconductor device. 1 is a device body (chip body), 2 is an input terminal, 3 is an input circuit, 4 is a one-shot pulse generation circuit,
Reference numeral 5 is an output terminal.

In the input circuit 3, 6 is a VCC power supply line for supplying a power supply voltage VCC on the high voltage side, and 7 is an NPN.
Type bipolar transistor, an input transistor 8 is a resistor forming a load of the transistor 7, and a reference numeral 9 is a VEE power supply line for supplying a low-voltage power supply voltage VEE.

In the one-shot pulse generation circuit 4, 10 is a non-NOT circuit (through circuit) and 11 is a NOT circuit.
Circuit (inverter), 12 is a non-NOT circuit, 13 is an AN
It is a D circuit.

FIG. 8 is a waveform diagram showing the operation of this semiconductor device. FIG. 8A is an input signal IN input to the input terminal 2, FIG. 8B is an output of the non-NOT circuit 10, and FIG. 8
8C shows the output of the non-NOT circuit 12, and FIG. 8D shows the output signal OUT output from the output terminal 5.

In this semiconductor device, the output signal OU
Since the pulse width of T is short, it is difficult to measure the H level voltage value of the output signal OUT, and it is difficult to test the output level.

Therefore, conventionally, a test circuit 14 is added as shown in FIG. 9, and 15 is an OR circuit,
Reference numeral 16 is a test circuit control signal input terminal to which the test circuit control signal TC is input.

FIG. 10 is a waveform diagram showing the operation in this case. FIG. 10 (A) shows the input signal IN, FIG. 10 (B) shows the output of the non-NOT circuit 10, and FIG. 10 (C) shows the non-NOT circuit. 1
2 output, FIG. 10D shows the test circuit control signal TC, FIG.
0 (E) indicates the output signal OUT.

That is, in this semiconductor device, during normal operation,
The test circuit control signal TC is set to L level. In this case, the output of the one-shot pulse generation circuit 4 can be obtained as the output signal OUT, and the OR circuit 15 does not function as a test circuit.

During the test, the test circuit control signal TC
= H level. In this case, since the output signal OUT is fixed at the H level, the H level voltage value of the output signal OUT can be easily measured and the output level can be easily tested.

[0011]

In recent years, in semiconductor devices, the number of external terminals tends to increase as the functionality of the semiconductor devices increases. Nevertheless, providing the test circuit control signal input terminal 16 as an external terminal as shown in FIG.

In view of the above point, the present invention enables the test circuit to be activated without providing a test circuit control signal input terminal as an external terminal, and the number of external terminals used during normal operation is increased accordingly. However, it is an object of the present invention to provide a semiconductor device capable of achieving high functionality.

[0013]

FIG. 1 is a diagram illustrating the principle of a semiconductor device according to the present invention, in which 17 is a device main body and 18 is a V.
CC power line, 19 VEE power line, 20 input terminal, 2
Reference numeral 1 is an input transistor, 22 is a load of the input transistor 21, 23 is a non-test circuit, and 24 is a test circuit.

Numeral 25 is an input signal IN to the input terminal 20.
When the input signal is input, the test circuit 24 is deactivated, the input terminal 20 is opened, or the input signal IN is input.
Is a predetermined voltage value or less, the test circuit control signal generating circuit generates a test circuit control signal TC for activating the test circuit 24.

That is, in the semiconductor device according to the present invention, the base is connected to the input terminal 20 to which the input signal IN is input, the emitter is connected to the low-voltage power supply line 19 via the load 22, and the non-test circuit is connected. When the input transistor 21 connected to 23 and the input signal IN are input to the input terminal 20, the test circuit 24 is deactivated and the input terminal 20 is opened or the input signal IN is set to a predetermined level. When the voltage value is equal to or lower than the voltage value of, the test circuit control signal generating circuit 25 for generating the test circuit control signal TC for activating the test circuit 24 is provided.

[0016]

In the present invention, the test circuit control signal generating circuit 25 is provided, and the test circuit control signal generating circuit 25 is provided.
When the input signal IN is input to the input terminal 20, the test circuit 24 is deactivated, and when the input terminal 20 is open or the input signal IN is set to a predetermined voltage value or less. Since the test circuit control signal TC for activating the test circuit 24 is generated, the test circuit control signal input terminal is not required as an external terminal.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first embodiment of the present invention will be described below with reference to FIGS.
Examples to fifth examples will be described. 2 to 6, parts corresponding to those in FIGS. 7 and 9 are designated by the same reference numerals, and duplicate description thereof will be omitted.

First Embodiment FIG. 2 FIG. 2 is a diagram showing a main part of the first embodiment of the present invention. In this first embodiment, a portion between a VCC power supply line 6 and a collector of an input transistor 7 is provided. Is connected to the resistor 26, the collector of the input transistor 7 is connected to a terminal to which the test circuit control signal TC of the OR circuit 15 constituting the test circuit 14 is to be input, and the other is connected to the conventional semiconductor device shown in FIG. It is configured in the same manner as.

In the first embodiment, when the input signal IN is input to the input terminal 2, a current flows between the collector and the emitter of the input transistor 7, the potential of the collector of the input transistor 7 becomes L level, and the OR circuit. Reference numeral 15 is an active state as a gate circuit and an inactive state as a test circuit, and the output of the one-shot pulse generation circuit 4 is an output signal O.
It is output as UT.

On the other hand, when the input terminal 2 is opened, the input transistor 7 is turned off, the collector of the input transistor 7 becomes the power supply voltage VCC, that is, the H level, and the OR circuit 15 functions as a gate circuit. Inactive state, active state as test circuit, output signal OU
T is fixed to the H level, and the H level voltage value of the output signal OUT can be easily measured.

The OR circuit 15 can be activated as a test circuit even when the level of the input signal IN is lowered until the level of the collector of the input transistor 7 becomes H level for the OR circuit 15. In this way, the testable state may be set.

As described above, according to the first embodiment, the input terminal 2 is opened or the input transistor 7 is opened.
When the level of the input signal IN is lowered until the level of the collector of the OR circuit 15 becomes the H level, the test circuit 14 can be activated, so that a test circuit control signal input terminal is provided as an external terminal. There is no need to increase the number of external terminals used during normal operation.
Higher functionality can be achieved.

Second Embodiment FIG. 3 FIG. 3 is a diagram showing the essential parts of a second embodiment of the present invention. In this second embodiment, the load on the emitter side of the input transistor 7 is a constant current. It is composed of a source circuit 27.

Further, 28 is an oscillation circuit and 29 is a test circuit. This test circuit 29 is inactivated when the collector of the input transistor 7 is L level, and when the collector of the input transistor 7 is H level. Are activated to stop the oscillation operation of the oscillation circuit 28,
Output is fixed to the H level, for example.

This is necessary, for example, when measuring the H-level voltage value of the oscillation output of the oscillation circuit 28 or when preventing a crosstalk from the oscillation circuit 28 when testing a circuit other than the oscillation circuit 28. Becomes

In the second embodiment, when the input signal IN is input to the input terminal 2, a current flows between the collector and the emitter of the input transistor 7, the potential of the collector of the input transistor 7 becomes L level, and the test circuit 29 is deactivated.

On the other hand, when the input terminal 2 is opened, the input transistor 7 is turned off, the collector of the input transistor 7 becomes the power supply voltage VCC, that is, the H level, and the test circuit 29 is activated. .

The test circuit 29 can be activated even when the level of the input signal IN is lowered until the level of the collector of the input transistor 7 becomes the H level for the test circuit 29. Then, the testable state may be set.

Further, in the second embodiment, the input terminal 2 which is not directly related to the oscillation circuit 28 which is the circuit under test is used for controlling the test circuit. This is possible, and in the case of the first embodiment as well, it can be configured in this way.

As described above, according to the second embodiment,
When the input terminal 2 is opened or when the level of the input signal IN is lowered until the level of the collector of the input transistor 7 becomes H level for the test circuit 29,
Since the test circuit 29 can be activated, it is not necessary to provide a test circuit control signal input terminal as an external terminal, and the number of external terminals used during normal operation can be increased accordingly.
Higher functionality can be achieved.

Further, in the first embodiment shown in FIG.
During normal operation, the collector level of the input transistor 7 fluctuates depending on the level of the input signal IN.
As a result, there is a problem in that the margin of the operation reference level of the test circuit 14 must be tightened.

On the other hand, according to the second embodiment,
Since the load on the emitter side of the input transistor 7 is constituted by the constant current source circuit 27, the collector level of the input transistor 7 can be maintained at a constant value during normal operation, and the operation reference level of the test circuit 29 can be maintained. The margin can be expanded.

Third Embodiment FIG. 4 FIG. 4 is a diagram showing the essential parts of a third embodiment of the present invention. In the third embodiment, a transistor 30 is added, and the other parts are shown in FIG. It has the same configuration as the second embodiment shown.

In this transistor 30, the collector is connected to the VCC power supply line 6, the emitter is connected to the emitter of the input transistor 7, and the base is connected to the reference voltage Vre.
It is configured to apply f. The reference voltage Vref is lower than the L level of the input signal IN.

In the third embodiment, when the input signal IN is input to the input terminal 2, a current flows between the collector and the emitter of the input transistor 7, the potential of the collector of the input transistor 7 becomes L level, and the test circuit 29 is deactivated. In this case, the transistor 30 is not turned on because the reference voltage Vref <the voltage value of the input signal IN at the L level.

On the other hand, when the input terminal 2 is opened or when the level of the input signal IN is made lower than the reference voltage Vref, the input transistor 7 is in the off state,
The transistor 30 is turned on, the collector of the input transistor 7 becomes the power supply voltage VCC, that is, the H level, and the test circuit 29 is activated.

As described above, according to the third embodiment, the test circuit 29 is activated when the input terminal 2 is opened or when the level of the input signal IN is lower than the reference voltage Vref. Therefore, it is not necessary to provide a test circuit control signal input terminal as an external terminal, and the number of external terminals used during normal operation can be increased by that amount, and high functionality can be achieved.

Further, in the second embodiment shown in FIG.
During the test, if the input transistor 7 is turned off, no current flows in the constant current source circuit 27, which adversely affects the circuit to which the emitter of the input transistor 7 is connected.

On the other hand, according to the third embodiment,
During the test, when the input transistor 7 is turned off, the transistor 30 is turned on, a current is supplied to the constant current source circuit 27, and a current can be supplied to the circuit to which the emitter of the input transistor 7 is connected. , The circuit to which the emitter of the input transistor 7 is connected is not adversely affected.

Further, according to the third embodiment, since the collector level of the input transistor 7 can be maintained at a constant value during the normal operation, the margin of the operation reference level of the test circuit 29 can be expanded. it can.

Further, according to the third embodiment, when the level of the input signal IN is made lower than the reference voltage Vref, the test ready state can be immediately set, so that the test time can be shortened. be able to.

Fourth Embodiment FIG. 5 FIG. 5 is a diagram showing a main part of a fourth embodiment of the present invention. In the fourth embodiment, the collector of the input transistor 7 is directly connected to the VCC power supply line 6 Connected to.

The collector of the transistor 30 and V
A resistor 31 is connected to the CC power supply line 6, the collector of the transistor 30 is connected to the test circuit 32, and the other parts are configured similarly to the third embodiment shown in FIG.

Here, the test circuit 32 includes the transistor 3
When the collector of 0 = H level, it is inactivated, and when the collector of the transistor 30 = L level, it is activated.

In the fourth embodiment, when the input signal IN is input to the input terminal 2, the input transistor 7 is turned on, but the transistor 30 has the reference voltage Vref.
<Because it is the L level voltage value of the input signal IN,
The transistor 30 is not turned on, the potential of the collector of the transistor 30 becomes H level, and the test circuit 32 is deactivated.

On the other hand, when the input terminal 2 is opened or when the level of the input signal IN is made lower than the reference voltage Vref, the input transistor 7 is in the off state,
The transistor 30 is turned on, and the transistor 30
The potential of the collector of L becomes L level, and the test circuit 32 is activated.

As described above, according to the fourth embodiment, the test circuit 32 is activated when the input terminal 2 is opened or when the level of the input signal IN is lower than the reference voltage Vref. Therefore, it is not necessary to provide a test circuit control signal input terminal as an external terminal, and the number of external terminals used during normal operation can be increased by that amount, and high functionality can be achieved.

Further, according to the fourth embodiment, the level of the collector of the transistor 30 can be maintained at a constant value during the normal operation, so that the margin of the operation reference level of the test circuit 32 can be expanded. .

According to the fourth embodiment, during the test,
Since the current can be supplied to the circuit to which the emitter of the input transistor 7 is connected, the circuit to which the emitter of the input transistor 7 is connected is not adversely affected.

Further, according to the fourth embodiment, when the level of the input signal IN is made lower than the reference voltage Vref, the testable state can be immediately set, so that the test time can be shortened. be able to.

Fifth Embodiment FIG. 6 FIG. 6 is a diagram showing the essential parts of a fifth embodiment of the present invention. In the fifth embodiment, the load on the emitter side of the input transistor 7 is composed of a resistor 33. However, the other points are the same as those of the fourth embodiment shown in FIG.

In the fifth embodiment, when the input signal IN is input to the input terminal 2, the input transistor 7 is turned on, but the transistor 30 is connected to the reference voltage Vref.
<Because it is the L level voltage value of the input signal IN,
The transistor 30 is not turned on, the potential of the collector of the transistor 30 becomes H level, and the test circuit 32 is deactivated.

On the other hand, when the input terminal 2 is opened or when the level of the input signal IN is made lower than the reference voltage Vref, the input transistor 7 is in the off state,
The transistor 30 is turned on, and the transistor 30
The potential of the collector of L becomes L level, and the test circuit 32 is activated.

As described above, according to the fifth embodiment, the test circuit 32 is activated when the input terminal 2 is opened or when the level of the input signal IN is lower than the reference voltage Vref. Therefore, it is not necessary to provide a test circuit control signal input terminal as an external terminal, and the number of external terminals used during normal operation can be increased by that amount, and high functionality can be achieved.

Further, in the fifth embodiment, the load on the emitter side of the transistor 30 is constituted by the resistor 33, but even in this case, the level of the collector of the transistor 30 during normal operation is It can be set to a constant value regardless of the level change of the input signal IN.

Therefore, according to the fifth embodiment, the margin of the operation reference level of the test circuit 32 can be expanded similarly to the fourth embodiment shown in FIG. 5, and the fourth embodiment shown in FIG. The circuit configuration can be made simpler than that.

According to the fifth embodiment, during the test,
Since the current can be supplied to the circuit to which the emitter of the input transistor 7 is connected, the circuit to which the emitter of the input transistor 7 is connected is not adversely affected.

Further, according to the fifth embodiment, when the level of the input signal IN is made lower than the reference voltage Vref, the test ready state can be immediately set, so that the test time can be shortened. be able to.

[0059]

According to the present invention, the test circuit control for activating the test circuit (24) when the input terminal (20) is opened or the input signal (IN) is set to a predetermined voltage value or less. Since the test circuit control signal generating circuit (25) for generating the signal (TC) is provided, it is not necessary to provide the test circuit control signal input terminal as an external terminal, and the external terminal used in the normal operation is increased accordingly. Therefore, it is possible to achieve higher functionality.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram showing a main part of the first embodiment of the present invention.

FIG. 3 is a diagram showing a main part of a second embodiment of the present invention.

FIG. 4 is a diagram showing a main part of a third embodiment of the present invention.

FIG. 5 is a diagram showing a main part of a fourth embodiment of the present invention.

FIG. 6 is a diagram showing a main part of a fifth embodiment of the present invention.

FIG. 7 is a diagram showing a main part of an example of a conventional semiconductor device.

8 is a waveform chart showing an operation of the semiconductor device shown in FIG.

FIG. 9 is a diagram showing a main part of another example of a conventional semiconductor device.

10 is a waveform chart showing an operation of the semiconductor device shown in FIG.

[Explanation of symbols]

 17 Device Main Body 18 VCC Power Supply Line 19 VEE Power Supply Line 20 Input Terminal 21 Input Transistor 22 Load 23 Non-Test Circuit 24 Test Circuit 25 Test Circuit Control Signal Generation Circuit TC Test Circuit Control Signal

Claims (6)

[Claims] 1. A base is connected to an input terminal (20) to which an input signal (IN) is input, an emitter is connected to a low-voltage side power supply line (19) through a load (22), and is not tested. Input transistor (2 connected to circuit (23)
1) and the input signal (IN) to the input terminal (20).
When the test circuit (24) is deactivated and the input terminal (20) is opened or the input signal (IN) is set to a predetermined voltage value or less, A semiconductor device comprising: a test circuit control signal generating circuit (25) for generating a test circuit control signal (TC) for activating the test circuit (24). 2. The test circuit control signal generating circuit (25)
Is configured to connect the collector of the input transistor (21) to a power supply line (18) on the high voltage side via a load and obtain the test circuit control signal (TC) at the collector of the input transistor (21). The semiconductor device according to claim 1, wherein the semiconductor device is provided. 3. The semiconductor device according to claim 1, wherein the load (22) on the emitter side of the input transistor (21) is composed of a constant current source circuit. 4. A power supply line (18) for connecting the collector to the high voltage side.
4. The semiconductor device according to claim 3, further comprising a transistor having a base connected to the emitter of the input transistor (21) and a base supplied with a reference voltage. 5. The input transistor (21) has a collector connected to a power supply line (18) on the high voltage side, and a load (22) on the emitter side configured by a constant current source circuit, and the test circuit control signal generating circuit is provided. The circuit (25) has a collector connected to the high-voltage side power supply line (18) through a load, an emitter connected to the emitter of the input transistor (21), and a base supplied with a reference voltage. 2. The semiconductor device according to claim 1, wherein the semiconductor device is configured to obtain a test circuit control signal (TC) at the collector of the transistor. 6. The input transistor (21) has a collector connected to a power supply line (18) on the high voltage side and a load on the emitter side made up of a resistor, and the test circuit control signal generation circuit (25) includes: A collector is connected to the high-voltage side power supply line (18) through a load, an emitter is connected to the emitter of the input transistor (21), and a base is provided with a transistor supplied with a reference voltage. 2. The semiconductor device according to claim 1, wherein the collector is configured to obtain the test circuit control signal (TC).