JPH0629108A - Insolatins substrate for microminiaturized chip part - Google Patents
Insolatins substrate for microminiaturized chip partInfo
- Publication number
- JPH0629108A JPH0629108A JP4184935A JP18493592A JPH0629108A JP H0629108 A JPH0629108 A JP H0629108A JP 4184935 A JP4184935 A JP 4184935A JP 18493592 A JP18493592 A JP 18493592A JP H0629108 A JPH0629108 A JP H0629108A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- individual
- pieces
- insulating substrate
- ceramic substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Apparatuses And Processes For Manufacturing Resistors (AREA)
Abstract
(57)【要約】
【目的】 本発明は、従来の超小形チップ部品用絶縁基
板およびその製造方法に関わる問題点を解決し、超小形
チップ部品の大幅な小形化、軽量化、低コスト化を図る
ことを目的とするものである。
【構成】 あらかじめブレイクラインを形成して焼成さ
れたセラミック基板をブレイクラインに沿って割断して
得た個別基板片、または、セラミック基板にブレイクラ
インを形成し、これに沿って割断して得た個別基板片、
または、セラミック基板を切断して得た個別基板片を再
配列、接合して成る絶縁基板であって、基板厚みが薄
く、ピッチ精度が良好で、かつ変形の少ない絶縁基板を
歩留まりよく得ることが可能となり、超小形チップ部品
の大幅な小形化、軽量化、低コスト化を図ることができ
る。
(57) [Summary] [Object] The present invention solves the problems related to the conventional insulating substrate for microminiature chip components and the manufacturing method thereof, and makes the miniaturization of microminiature chip components significantly smaller, lighter, and lower in cost. The purpose is to achieve. [Structure] An individual substrate piece obtained by cutting a ceramic substrate on which break lines have been formed and fired along the break lines, or a break line is formed on the ceramic substrate and cut along the break lines. Individual board pieces,
Alternatively, an insulating substrate obtained by rearranging and joining individual substrate pieces obtained by cutting a ceramic substrate, having a small substrate thickness, good pitch accuracy, and little deformation, can be obtained with high yield. As a result, it is possible to significantly reduce the size, weight and cost of ultra-small chip parts.
Description
【0001】[0001]
【産業上の利用分野】本発明は、電子機器に用いられる
絶縁基板に関し、特に小形、軽量、低コスト化を図った
超小形チップ部品用絶縁基板に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulating substrate for use in electronic equipment, and more particularly to an insulating substrate for ultra-small chip parts which is compact, lightweight and low cost.
【0002】[0002]
【従来の技術】近年、電子機器の小形・軽量化志向、高
集積回路の採用による電子回路の高密度化、あるいは自
動挿入機の普及などに伴い、電子部品に対する小形化の
要請がますます強くなってきている。その中にあって、
コンデンサや固定抵抗器なども他の部品と同様に小形化
への種々の研究開発が試みられている。2. Description of the Related Art In recent years, with the trend toward smaller and lighter electronic devices, higher density of electronic circuits due to the adoption of highly integrated circuits, and the widespread use of automatic insertion machines, there is an increasing demand for smaller electronic components. It has become to. In that,
As with other parts, various research and development efforts have been made to reduce the size of capacitors and fixed resistors.
【0003】チップ固定抵抗器等では、チップブレイク
するためのブレイク用の溝をあらかじめ格子状に形成し
たセラミックグリーンシートを焼成して成るセラミック
絶縁基板が用いられている。A chip fixed resistor or the like uses a ceramic insulating substrate formed by firing a ceramic green sheet in which break grooves for chip breaking are previously formed in a grid pattern.
【0004】また、絶縁基板上に、誘電体層と内部電極
層を積層して成る積層薄膜コンデンサ等では、基板上に
複数のコンデンサ素子を薄膜形成工法により積層した
後、チップブレイクするためのブレイク用の溝をレーザ
ービームを照射することにより形成する方法等が用いら
れている。Further, in a laminated thin film capacitor or the like in which a dielectric layer and an internal electrode layer are laminated on an insulating substrate, a break for chip breaking after laminating a plurality of capacitor elements on the substrate by a thin film forming method. There is used a method of forming a groove for use by irradiating a laser beam.
【0005】[0005]
【発明が解決しようとする課題】チップ部品の小形化に
伴って、それに使用される絶縁基板の薄板化が必要とな
るが、セラミック絶縁基板の薄板化により、基板の機械
強度の低下による基板割れの増加、基板の反り等の変形
の増大等により、基板形状の小形化を余儀なくされてお
り、これにより、これら基板上に素子等を形成する工程
の生産性を阻害するとともに、基板のコストの大幅な高
騰をも招いているのが現状である。With the miniaturization of chip components, it is necessary to reduce the thickness of the insulating substrate used for the chip component. However, thinning of the ceramic insulating substrate reduces the mechanical strength of the substrate and thus cracks the substrate. However, due to the increase in substrate deformation and the increase in deformation such as warp of the substrate, it is inevitable to downsize the substrate shape, which hinders the productivity of the process of forming elements and the like on these substrates and reduces the cost of the substrate. The current situation is that it has caused a sharp rise in prices.
【0006】また、チップブレイクするためのブレイク
用の溝をあらかじめ格子状に形成したセラミックグリー
ンシートを焼成して成るセラミック絶縁基板では、焼成
時の収縮ばらつきが大きいため、チップ固定抵抗器等で
は焼成済みの基板の寸法によりランク分けして使用して
いるのが現状である。Further, in a ceramic insulating substrate made by firing a ceramic green sheet in which grooves for breaking for chip breaking are previously formed in a grid pattern, there is a large variation in shrinkage during firing, so firing is performed in a chip fixed resistor or the like. It is the current situation that ranks are used according to the size of the already used substrate.
【0007】本発明は、このような従来の超小形チップ
部品用絶縁基板に関わる問題点を解決するもので、超小
形チップ部品の大幅な小形化、軽量化、低コスト化を図
った超小形チップ部品用絶縁基板を提供することを目的
とするものである。The present invention solves the problems associated with the conventional insulating substrate for a microminiature chip component. The miniaturization of the microminiature chip component is intended to be greatly reduced in size, weight and cost. An object is to provide an insulating substrate for chip parts.
【0008】[0008]
【課題を解決するための手段】この問題を解決するた
め、本発明の超小形チップ部品用絶縁基板は、あらかじ
めブレイクラインを形成して焼成されたセラミック基板
をブレイクラインに沿って割断して得た個別基板片、ま
たは、セラミック基板にブレイクラインを形成し、これ
に沿って割断して得た個別基板片、またはセラミック基
板を切断して得た個別基板片を再配列、接合して成るも
のである。In order to solve this problem, the insulating substrate for microminiature chip parts of the present invention is obtained by cutting a ceramic substrate which has been previously formed with break lines and fired along the break lines. The individual board pieces formed by breaking lines formed on the individual board pieces or the ceramic board and cut along the break lines, or the individual board pieces obtained by cutting the ceramic board are rearranged and joined. Is.
【0009】上記個別基板片の再配列、接合の方法とし
ては、面実装チップ部品の実装装置を応用して、粘着性
を有するシート面上に、要求される精度以内で規定の隙
間を設けて配列し、その隙間部分の全部、または一部に
スクリーン印刷法またはメタルマスクを用いた印刷法等
によりエポキシ樹脂等の接着剤を塗布し、紫外線照射ま
たは加熱処理により硬化させることにより接合する方法
等が可能である。As a method for rearranging and joining the individual board pieces, a mounting device for surface-mounting chip parts is applied to form a prescribed gap on the adhesive sheet surface within required accuracy. A method of arranging and applying an adhesive such as an epoxy resin to all or part of the gap portion by a screen printing method or a printing method using a metal mask, and bonding by curing by ultraviolet irradiation or heat treatment, etc. Is possible.
【0010】なお、配列する個別基板片の仮固定法とし
ては、エアチャック法の応用等も可能であり、上記粘着
シートを用いる方法に限るものではない。As a method of temporarily fixing the individual substrate pieces to be arranged, the air chuck method can be applied, and the method is not limited to the method using the adhesive sheet.
【0011】また、配列方法としても、格子状の枠を用
いて、ここの枠内に個別基板片を並べることにより要求
される精度以内で規定の隙間を設けて配列することが可
能であり、面実装チップ部品の実装装置の応用に限るも
のではない。Also, as an arrangement method, it is possible to arrange the individual board pieces with a predetermined gap within the required accuracy by using a grid-like frame and arranging the individual substrate pieces in the frame. It is not limited to the application of the mounting device for surface mounting chip parts.
【0012】また、使用する接着剤およびその塗布、硬
化等の方法としても、上記方法に限るものではない。The adhesive to be used and the method of applying and curing the same are not limited to the above methods.
【0013】また、上記のセラミック基板には、アルミ
ナ基板等の一般のセラミック基板のほか、ガラス基板も
含まれることはいうまでもないことである。It goes without saying that the above-mentioned ceramic substrate includes not only a general ceramic substrate such as an alumina substrate but also a glass substrate.
【0014】[0014]
【作用】上記構成により、部品の小形化に必要な基板の
薄板化を実現すると共に、低コスト化の大きな阻害要因
である歩留まり低下や、基板の機械強度の低下による基
板割れの増加、基板の反り等の変形の増大等を招く事な
く、素子部形成時に要求される大きさ、形状の基板を得
ることが可能となる。これにより、チップ部品の小形
化、軽量化、低コスト化が図れる。With the above structure, it is possible to reduce the thickness of the substrate required for downsizing of parts, and to reduce the yield, which is a major impediment factor for cost reduction. It is possible to obtain a substrate having the size and shape required when forming the element portion without causing an increase in deformation such as warpage. As a result, it is possible to reduce the size, weight, and cost of the chip component.
【0015】[0015]
【実施例】以下に、本発明の一実施例の超小形チップ部
品用絶縁基板について、図面を参照しながら具体的に説
明する。図1および図2に、本発明の一実施例の超小形
チップ部品用絶縁基板の外観を示す。図に示すように、
割断された個別基板片を要求される精度以内で規定の隙
間を設けて配列した後、その隙間部分の全部、または一
部に接着剤を塗布し、硬化させることにより接合して成
るものである。DESCRIPTION OF THE PREFERRED EMBODIMENTS An insulating substrate for a microminiature chip component according to an embodiment of the present invention will be specifically described below with reference to the drawings. 1 and 2 show the appearance of an insulating substrate for a microminiature chip component according to an embodiment of the present invention. As shown in the figure,
It is formed by arranging the cut individual substrate pieces with a prescribed gap within the required accuracy and then applying an adhesive to all or part of the gap and curing it to join them. .
【0016】以下に、本発明の具体的実施例を説明す
る。あらかじめブレイクラインを形成して焼成された、
厚さ0.2mmのジルコニア基板(日本ファインセラミッ
クス(株)製、製品名・セラフレックス−A)をブレイ
クラインに沿って割断し、1.0mm×0.5mmの個別基
板片を得た。これらの個別基板片を、長手方向には1.
5mmピッチに、その直角方向には1.0mmピッチに、エ
アチャック穴を有する基台上に、上記エアチャック穴が
個別基板片の中央にくるように、かつ各基板片間の隙間
が0.5mmとなるように、面実装チップ部品の実装装置
を応用した装置にて配列し、仮固定した。これに、図3
に示すパターンを有するメタルマスクを合わせ、各素子
間の隙間部の長辺、単辺それぞれの中央部分に、それぞ
れ隣接する基板片を接合するため、紫外線硬化性のエポ
キシ樹脂接着剤を厚さ0.2mm塗布した後、窒素雰囲気
下で紫外線を照射し硬化させ、100mm×100mmの絶
縁基板を得た。この絶縁基板について、基板の反りを計
測した結果、対角線方向長さ100mm当たり0.1mm以
下であった。これに対して、現行のセラミック基板で
は、焼成時の収縮、変形が大きいため、0.2mm厚の基
板では100mm角の大きさの基板は実用化されていない
のが現状である。また、この絶縁基板について、配列さ
れた個別基板片間のピッチのばらつきは±50μm(9
0mm当たり)であった。これに対して、現行のセラミッ
ク基板では、焼成時の収縮、変形が大きいため、96%
アルミナ基板(0.4mm厚)では、±500μm(90
mm当たり)程度である。従って、実用時には、ピッチを
測定し、10ランク程度に区分けして使用しているのが
現状である。Specific examples of the present invention will be described below. A break line was previously formed and baked,
A zirconia substrate (product name: Seraflex-A, manufactured by Nippon Fine Ceramics Co., Ltd.) having a thickness of 0.2 mm was cut along the break line to obtain an individual substrate piece of 1.0 mm × 0.5 mm. These individual substrate pieces are 1.
A pitch of 5 mm and a pitch of 1.0 mm in the direction perpendicular to the base are provided on the base having air chuck holes so that the air chuck holes are located at the centers of the individual substrate pieces, and the gap between the respective substrate pieces is 0. The devices were arranged so as to have a size of 5 mm by a device to which a mounting device for surface-mounted chip components was applied, and temporarily fixed. In addition to this,
The metal mask having the pattern shown in Fig. 1 is aligned, and the ultraviolet curable epoxy resin adhesive is applied to the central portions of the long sides and the single sides of the gap between the elements to bond the ultraviolet curable epoxy resin adhesive to a thickness of After applying 0.2 mm, it was irradiated with ultraviolet rays and cured in a nitrogen atmosphere to obtain a 100 mm × 100 mm insulating substrate. As a result of measuring the warp of this insulating substrate, it was 0.1 mm or less per 100 mm in the diagonal direction. On the other hand, in the current ceramic substrate, since shrinkage and deformation during firing are large, a substrate having a size of 0.2 mm and a size of 100 mm square has not been put into practical use. Further, in this insulating substrate, the variation in pitch between the arrayed individual substrate pieces is ± 50 μm (9
(Per 0 mm). On the other hand, the current ceramic substrate has a large shrinkage and deformation during firing, so 96%
Alumina substrate (0.4mm thickness) ± 500μm (90
(per mm). Therefore, at the time of practical use, the pitch is measured and divided into about 10 ranks for use at present.
【0017】[0017]
【発明の効果】以上の実施例の説明から明らかなよう
に、本発明によれば、基板厚みが薄く、ピッチ精度が良
好で、かつ変形の少ない絶縁基板が、歩留まりよく得る
ことが可能となった。これにより、超小形チップ部品の
大幅な小形化、軽量化、低コスト化を図ることができ
る。As is apparent from the above description of the embodiments, according to the present invention, it is possible to obtain an insulating substrate having a small substrate thickness, good pitch accuracy, and little deformation with a good yield. It was As a result, it is possible to significantly reduce the size, weight and cost of the ultra-small chip component.
【図1】本発明の一実施例の超小形チップ部品用絶縁基
板の外観図FIG. 1 is an external view of an insulating substrate for a micro chip component according to an embodiment of the present invention.
【図2】本発明の一実施例の超小形チップ部品用絶縁基
板の外観図FIG. 2 is an external view of an insulating substrate for microminiature chip components according to an embodiment of the present invention.
【図3】実施例1にて使用した、個別基板片を接合する
ための接着剤塗布用のメタルマスクのパターン図FIG. 3 is a pattern diagram of a metal mask for applying an adhesive for joining the individual substrate pieces used in Example 1.
1 個別基板片 2 接着剤部 3 マスク穴(0.25×0.5mm) 4 マスク穴(0.5×0.5mm) 5 マスク合わせ時の個別基板片の位置 1 Individual board piece 2 Adhesive part 3 Mask hole (0.25 x 0.5 mm) 4 Mask hole (0.5 x 0.5 mm) 5 Position of individual board piece when aligning mask
Claims (1)
されたセラミック基板をブレイクラインに沿って割断し
て得た個別基板片、または、セラミック基板にブレイク
ラインを形成し、これに沿って割断して得た個別基板
片、または、セラミック基板を切断して得た個別基板片
を再配列、接合して成る超小形チップ部品用絶縁基板。1. An individual substrate piece obtained by cutting a ceramic substrate on which a break line is formed and fired in advance, or a break line is formed on the ceramic substrate, and the ceramic substrate is cut along the break line. An insulating substrate for microminiature chip parts, which is obtained by rearranging and joining the obtained individual substrate pieces or the individual substrate pieces obtained by cutting the ceramic substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4184935A JPH0629108A (en) | 1992-07-13 | 1992-07-13 | Insolatins substrate for microminiaturized chip part |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4184935A JPH0629108A (en) | 1992-07-13 | 1992-07-13 | Insolatins substrate for microminiaturized chip part |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0629108A true JPH0629108A (en) | 1994-02-04 |
Family
ID=16161928
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4184935A Pending JPH0629108A (en) | 1992-07-13 | 1992-07-13 | Insolatins substrate for microminiaturized chip part |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0629108A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5501927A (en) * | 1990-04-27 | 1996-03-26 | Fuji Xerox Co., Ltd. | Electrophotographic photoreceptors |
| US6450382B1 (en) | 2000-01-05 | 2002-09-17 | Tokyo Kikai Seisakusho, Ltd. | Printing web position adjusting apparatus |
| KR100819279B1 (en) * | 2006-08-07 | 2008-04-02 | 삼성전자주식회사 | Panel board assembly |
| WO2017136698A1 (en) * | 2016-02-05 | 2017-08-10 | Jones Ryan Christopher | Adjustable cosmetic brush system |
-
1992
- 1992-07-13 JP JP4184935A patent/JPH0629108A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5501927A (en) * | 1990-04-27 | 1996-03-26 | Fuji Xerox Co., Ltd. | Electrophotographic photoreceptors |
| US6450382B1 (en) | 2000-01-05 | 2002-09-17 | Tokyo Kikai Seisakusho, Ltd. | Printing web position adjusting apparatus |
| KR100819279B1 (en) * | 2006-08-07 | 2008-04-02 | 삼성전자주식회사 | Panel board assembly |
| WO2017136698A1 (en) * | 2016-02-05 | 2017-08-10 | Jones Ryan Christopher | Adjustable cosmetic brush system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4336551A (en) | Thick-film printed circuit board and method for producing the same | |
| EP1365451A1 (en) | Module component | |
| US7656677B2 (en) | Multilayer electronic component and structure for mounting multilayer electronic component | |
| JPH0629108A (en) | Insolatins substrate for microminiaturized chip part | |
| JP2857552B2 (en) | Multilayer electronic component and method of manufacturing the same | |
| JPH0983141A (en) | Manufacturing method of ceramic multilayer substrate | |
| JP2002151994A (en) | Package structure for crystal vibrator and its manufacturing method | |
| JP2007324429A (en) | Module parts and manufacturing method thereof | |
| JP3248294B2 (en) | Chip inductor and manufacturing method thereof | |
| JPH0378793B2 (en) | ||
| JP2000150303A (en) | Manufacturing method of solid composite parts | |
| JPH0574943B2 (en) | ||
| JP3632504B2 (en) | Manufacturing method of chip-shaped electronic component | |
| JP2002203739A (en) | Capacitor element | |
| JPS59134803A (en) | Manufacturing method of chip resistor | |
| JP2001015930A (en) | Multilayer wiring board and method of manufacturing the same | |
| JPH1164369A (en) | Semiconductor sensor | |
| JP2007149991A (en) | Circuit module manufacturing method | |
| JP2536627B2 (en) | Chip-shaped piezoelectric component | |
| JPH0555045A (en) | Chip inductor and manufacturing method thereof | |
| JP2003324168A (en) | Printed wiring board for mounting semiconductor integrated circuit | |
| JPS6341003A (en) | Manufacture of chip electronic parts | |
| JPH06318534A (en) | Chip type composite electronic component and manufacture of the same | |
| JPH04309283A (en) | Manufacture of ceramic circuit board | |
| JP2632151B2 (en) | Manufacturing method of circuit block |