JPH0630005B2 - Programmable counter - Google Patents

Description

The present invention relates to a programmable counter for performing various controls according to a count value.

[Conventional technology]

A programmable counter that can increase or decrease the count value according to the movement of various processing materials and can change the set value arbitrarily to perform the desired processing when the preset count value is reached. Is used. In such a programmable counter, a plurality of count setting values are paired with the output designation in the output designating unit that indicates what processing is to be performed when the count value of the counter matches the set value. Are programmed in advance, and various processes are performed according to the program.

[Problems to be Solved by the Invention]

However, in the conventional programmable counter, only the type of output corresponding to the set value of the count is determined.
Therefore, it is not possible to perform highly sophisticated control such as temporarily stopping the output or stopping the output according to the counting state of the counter.

The present invention has been made in view of the inconvenience of using such a conventional programmable counter, and in addition to the count setting unit and the output designating unit, a control mode for performing various controls is added, and complicated control is performed. It is intended to provide a programmable counter capable of performing.

[Means for Solving the Problems]

The present invention is a programmable counter that has a counter that counts an input clock and a storage unit that stores a count setting value and an output state corresponding to the count setting, and that controls based on the count output of the counter. The storage unit includes a plurality of steps each having a count setting unit, an output designating unit, and a control mode designating unit, the count setting unit is an area for setting a set value of the counter, and the output designating unit is an arbitrary unit. The control mode designating unit is a region for designating the control mode defining the control inside the counter except the output state, and the programmable counter is the count value of the counter and each step of the storage unit. A comparator that sequentially compares the set values of the count setting unit and determines whether they match, and the output set in the step of the storage unit based on the match output of the comparator. It is characterized in that it comprises a control unit to output the corresponding output of the constant portion of the control mode of the control mode designating unit.

[Action]

According to the present invention having such a feature, the count setting unit, the output designating unit, and the control mode designating unit are stored in each step of the storage unit. Then, the input clock signal is counted by the counter and the comparator sequentially compares the count value with the set value of the count setting unit of each step. Then, when it matches with the set value of the count setting unit of a certain step, the output is performed according to the output state and the control mode specified by the output designating unit and the control mode designating unit of the step. For example, in the invention of claim 2, since the control mode designating unit uses the end control command, the execution of the counter is stopped after outputting the designated output. Further, in the invention of claim 3, since the control mode designating unit uses the lockout control command, the output designated by the output designating unit is stopped. In the invention according to claim 4, the control mode designating unit uses a clear command, and therefore, when the set value is reached, the count value of the counter is cleared. Further, in the invention of claim 5, since the control mode designating section uses the forecast signal, the output set by the output designating section is output as the forecast signal. Further, according to the invention of claim 6 of the present application, the control mode designating section uses the count control instruction for outputting the output only during either the up-counting or the down-counting. Or, control to stop.

〔Example〕

FIG. 1 is a block diagram showing an electrical configuration of a programmable counter according to the present invention. As shown in this figure, this programmable counter has a central processing unit (hereinafter referred to as CPU) 1. A key input unit 2 is connected to the CPU 1 as an input unit, and a memory 3 is connected as a storage unit. The memory 3 has a region for storing a plurality of steps including a count setting unit, an output designating unit, and a control mode designating unit as described later, in addition to the arithmetic processing procedure of the CPU 1. The output of the CPU 1 is given to the display 4 and the counter 5. The counter 5 is a counter for counting the clock signals obtained from the clock generator 6 under the control of the CPU 1, and the count output is given to the comparator 7. The comparator 7 compares the count setting section of each step of the memory 3 provided by the CPU 1 with the count value of the counter 5, and gives the coincidence output to the output section 8. Output unit 8
Is to give a corresponding output to the control target based on the output designation from the CPU 1. A control input signal is applied to the counter 5, the comparator 7, and the output section 8 from the control input section 9.

FIG. 2 is a view showing front panel surfaces of the key input unit 2 and the display unit 4. On the upper part of the panel surface, a count display section 4a showing a 3-digit step number and a count display section 4b showing a 7-digit count value are provided. On the key input unit 2, a ten-key 2a and various function keys 2b for writing a program, writing various control modes, and changing
Etc. are provided.

FIG. 3A is a diagram showing a memory map of the memory 3.
In the figure, the memory 3 has, in addition to a program area for storing the arithmetic processing procedure of the CPU 1, a step area for storing a series of control steps, a step counter indicating a step under control, and a position thereof when setting or changing a control mode. It has a control mode pointer area for pointing. Each of the steps 1 to n has a count setting section for setting the count value of the counter 5, an output designating section for designating the type of output at that time, and a control mode setting section which is a feature of the present invention.

Here, the output designation unit is a designation unit that determines the state of the output itself. The output state is, for example, a coincident output state in which a contact signal is closed for one count, a one-shot output state in which a contact signal is closed for a predetermined count number, or a contact is opened or closed at a set value, or closed. The set and reset output states are switched to open, and the control mode setting section is an area for designating a mode for executing control other than the output state such as the operating state of the counter and the end of the operation. In this embodiment, FIG.
As shown in more detail in (b), the control mode setting section is in the control mode including a 5-bit signal. This control mode includes an end control (EN
D), lockout control for temporarily stopping the program output, counter clear control for clearing the count value of the counter 5, forecast output control indicating that an output is output as a forecast before controlling the control target, counting Each region of the count control that determines when the counter 5 outputs the up-count or the down-count is defined. Each of these controls is set by setting the corresponding bit to "0" or "1".

Next, the operation of the programmable counter will be described with reference to the flowchart. FIG. 4 is a flowchart showing the overall processing of the programmable counter. When the operation is started, the system is first initialized (routine 20). When the initialization is completed, the routine proceeds to step 21, where it is checked whether it is the program setting mode. If it is in the setting mode, the routine proceeds to routine 22 to execute the key processing program, and if it is not in the setting mode, the execution processing of the user program written in the step area is performed (routine 23).

The key processing program is processing for writing the program in each step area of the memory 3, and its operation will be described with reference to the flowchart of FIG. If this process is started, it is first checked in step 30 whether or not the shift key is pressed, and if it is pressed, step 31
Go to and check if it is in control mode. If it is not the control mode, the counter setting or the output is designated, so that the processing corresponding thereto is performed. If it is the control mode, the control mode pointer of the memory 3 is updated and the process returns to step 21. When the shift key is pressed one after another, the control mode pointer is updated in the same manner, and the pointer is updated to the bit position to be changed in the control mode shown in FIG. 3 (b). This pointer is displayed in the display area of the display unit 4 such that the decimal point blinks. Then, if the numeric key is pressed instead of the shift key, step 30,3
Proceed to step 34 via step 3 to check if the control mode is set. If it is not the control mode, other processing is performed. In the case of the control mode, each mode is indicated by 1 bit, that is, "0" or "1", so it is checked whether this is "0" or "1". (Step
35). If it is not "0" or "1", error processing is performed,
If it is "0" or "1", write "0" or "1" of the control mode at the position indicated by the pointer (step 3
6) Return to step 21.

Next, if the write key is pressed, the process proceeds to step 38 through steps 30, 33 and 37 to check the program buffer. If the program is normal, the program is registered in step 40 through step 39, the step counter is incremented, and step 21
Return to. If the program is abnormal in step 39, error processing of the program is performed in step 42. In this way, the count setting value is sequentially registered, the output is designated, and the control mode is designated from step 1 to the required step.

Next, in step 21, if it is not the program setting mode, the routine of the user program execution processing of the routine 23 is performed. FIG. 6 is a flowchart showing this processing routine. When the execution is started, the process waits in step 50 until the count output of the counter 5 becomes equal to the set value of the count setting section set in the step of the first step counter. For example, in the example of the memory map shown in FIG. 3 (a), since the set value of 100 is set in step 1, it waits until the count output of the counter 5 reaches 100, and if this becomes equal to the set value, the step In step 51, the output designation and control mode designation in step 1 are read from the memory 3. At the same time, output of step 1 (this output state is
And ) Is set (step 52), and the output is executed according to the control mode and the type of output designated by the control mode designation section (step 53). That is, for example, if lockout is instructed in the control mode, execution is not performed, and if the counter clear in the control mode is set, an output is output and the count value of the counter 5 is cleared, and the forecast output is set. If it is output as a forecast. When the counter is set to be up, the output is executed only when the counter 5 is counting up. Fig. 3 (a)
Assuming that the up control is written as the control mode as in the example of the memory map shown in (1), its output (A), for example, one-shot output is executed only when the counter 5 is counting up. Then, the routine proceeds to step 54, where it is checked whether or not the control mode is the end command (END). If this is not an end command, the process proceeds to step 55, the step counter in the memory 3 is incremented, the process returns to step 50, and the same processing is repeated for the next step.

For example, in the case shown in FIG. 3 (a), since the count set value in the next step 2 is 295, it waits until the count of the counter 5 reaches 295 in step 50, and when it becomes 295, it proceeds to step 51. Calls the output designation and control mode designation with.
In step 2, the output state (B) is, for example, coincidence output, and since the bit of the forecast output is set, it is output as the forecast. Further, the process proceeds to step 3, and when the count value of the counter 5 reaches 300, the output designation and control mode designation of step 3 are read. When the counter 5 is counting up, the count value is 300.
Therefore, the output state (C) of the output designating unit, for example, a set output is output. Similarly, the counter 5 continues counting,
If the set value 350 of the count setting unit designated in step 4 is reached, this count value is reached in the up-counting state, so an output is output. If this output gives a signal for reversing the counting of the counter 5 to the counter 5, the count value is successively decreased thereafter. In this way, a series of steps are controlled,
If the control mode is the end command in step 54, the process proceeds to step 56 and the step counter is reset to end the execution process of the user step.

As described above, in the programmable counter of the present invention, a control mode capable of various controls is added to each step, so that various control targets can be dealt with flexibly.

〔The invention's effect〕

Therefore, in the programmable counter according to the present invention, complicated control is possible by making various designations in the control mode designation unit, and the control target can be greatly expanded. Also, the versatility of the programmable counter can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an electrical configuration of a programmable counter of the present invention, FIG. 2 is a diagram showing a front panel surface of a key input section and a display section, and FIG. 3 (a) is a memory map of a memory 3, FIG. 3 (b) is a diagram showing the stored contents of the control mode designating unit, FIG. 4 is a flowchart showing the overall processing, FIG. 5 is a flowchart showing a key processing program, and FIG.
The figure is a flow chart showing the execution processing of the user program. 1 ... CPU, 2 ... key input section, 3 ... memory, 4 ...
… Display, 5 …… Counter, 7 …… Comparator

Claims (6)

[Claims] 1. A programmable counter having a counter that counts an input clock and a storage unit that stores a count set value and an output state corresponding to the count setting, and performs control based on the count output of the counter. In the above, the storage unit includes a plurality of steps each having a count setting unit, an output designating unit and a control mode designating unit, the count setting unit is an area for setting a set value of the counter, and the output designating unit is An area for designating an arbitrary output state, the control mode designating section is an area for designating a control mode for defining control inside the counter except the output state, and the programmable counter is a count value of the counter. Based on the coincidence output of the comparator, which sequentially compares the set values of the count setting unit of each step of the storage unit and determines the coincidence, Programmable counter, characterized in that it comprises a control unit for outputting in response to the control mode of the control mode designating unit output of output designation section which is set in the step of the storage unit Te. 2. The programmable counter according to claim 1, wherein the control mode designating section of each step of the storage section includes an end control instruction for stopping the execution of the program. 3. The control mode designating unit of the storage unit includes a lockout control command for determining whether or not to output the output state set by the output designating unit. Programmable counter described. 4. The programmable counter according to claim 1, wherein the control mode designation unit of the storage unit includes a clear control instruction for clearing the count value of the counter. 5. The programmable counter according to claim 1, wherein the control mode designating unit of the storage unit includes a forecast output command for outputting the output as a forecast signal. 6. The control mode designating unit of the storage unit includes a count control command for outputting an output only when the counter is counting up or counting down. The programmable counter according to item 1.