JPH0642196B2 - 倍密度走査用ラインメモリ - Google Patents

倍密度走査用ラインメモリ

Info

Publication number
JPH0642196B2
JPH0642196B2 JP63141979A JP14197988A JPH0642196B2 JP H0642196 B2 JPH0642196 B2 JP H0642196B2 JP 63141979 A JP63141979 A JP 63141979A JP 14197988 A JP14197988 A JP 14197988A JP H0642196 B2 JPH0642196 B2 JP H0642196B2
Authority
JP
Japan
Prior art keywords
read
data
write
input
shift
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP63141979A
Other languages
English (en)
Japanese (ja)
Other versions
JPH01310433A (ja
Inventor
邦雄 村松
清吾 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP63141979A priority Critical patent/JPH0642196B2/ja
Priority to US07/363,276 priority patent/US4945518A/en
Priority to KR1019890007942A priority patent/KR920003754B1/ko
Priority to DE68925307T priority patent/DE68925307T2/de
Priority to EP89110481A priority patent/EP0345807B1/fr
Publication of JPH01310433A publication Critical patent/JPH01310433A/ja
Publication of JPH0642196B2 publication Critical patent/JPH0642196B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/16—Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Image Input (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
JP63141979A 1988-06-09 1988-06-09 倍密度走査用ラインメモリ Expired - Fee Related JPH0642196B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP63141979A JPH0642196B2 (ja) 1988-06-09 1988-06-09 倍密度走査用ラインメモリ
US07/363,276 US4945518A (en) 1988-06-09 1989-06-08 Line memory for speed conversion
KR1019890007942A KR920003754B1 (ko) 1988-06-09 1989-06-09 속도변환용 라인메모리
DE68925307T DE68925307T2 (de) 1988-06-09 1989-06-09 Zeilenspeicher für Geschwindigkeitsumwandlung
EP89110481A EP0345807B1 (fr) 1988-06-09 1989-06-09 Mémoire de ligne pour conversion de vélocité

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63141979A JPH0642196B2 (ja) 1988-06-09 1988-06-09 倍密度走査用ラインメモリ

Publications (2)

Publication Number Publication Date
JPH01310433A JPH01310433A (ja) 1989-12-14
JPH0642196B2 true JPH0642196B2 (ja) 1994-06-01

Family

ID=15304574

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63141979A Expired - Fee Related JPH0642196B2 (ja) 1988-06-09 1988-06-09 倍密度走査用ラインメモリ

Country Status (5)

Country Link
US (1) US4945518A (fr)
EP (1) EP0345807B1 (fr)
JP (1) JPH0642196B2 (fr)
KR (1) KR920003754B1 (fr)
DE (1) DE68925307T2 (fr)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5086388A (en) * 1988-03-18 1992-02-04 Hitachi Maxell, Ltd. Semiconductor serial/parallel-parallel/serial file memory and storage system
US5167020A (en) * 1989-05-25 1992-11-24 The Boeing Company Serial data transmitter with dual buffers operating separately and having scan and self test modes
JPH04188243A (ja) * 1990-11-21 1992-07-06 Nippon Steel Corp 記憶装置
JP2999845B2 (ja) * 1991-04-25 2000-01-17 沖電気工業株式会社 シリアルアクセスメモリの倍速コントロール方式
JPH05198163A (ja) * 1991-10-08 1993-08-06 Mitsubishi Denki Eng Kk 半導体記憶装置におけるアドレスポインタ
GB9208493D0 (en) * 1992-04-16 1992-06-03 Thomson Consumer Electronics Dual port video memory
JPH06274528A (ja) * 1993-03-18 1994-09-30 Fujitsu Ltd ベクトル演算処理装置
JP4018159B2 (ja) * 1993-06-28 2007-12-05 株式会社ルネサステクノロジ 半導体集積回路
JPH0784870A (ja) * 1993-06-30 1995-03-31 Sanyo Electric Co Ltd 記憶回路
US5508967A (en) * 1993-08-09 1996-04-16 Matsushita Electric Industrial Co., Ltd. Line memory
US5479128A (en) * 1994-03-16 1995-12-26 Industrial Technology Research Institute Single ram multiple-delay variable delay circuit
TW293107B (fr) * 1994-10-28 1996-12-11 Matsushita Electric Industrial Co Ltd
US5621337A (en) * 1995-08-30 1997-04-15 National Semiconductor Corporation Iterative logic circuit
JP3789173B2 (ja) * 1996-07-22 2006-06-21 Ｎｅｃエレクトロニクス株式会社 半導体記憶装置及び半導体記憶装置のアクセス方法
KR100602399B1 (ko) * 1998-02-16 2006-07-20 소니 가부시끼 가이샤 메모리 장치 및 방법
JP2000315147A (ja) * 1999-04-30 2000-11-14 Oki Electric Ind Co Ltd データ速度変換回路
JP2001195899A (ja) 2000-01-06 2001-07-19 Mitsubishi Electric Corp 半導体記憶装置
KR100372247B1 (ko) * 2000-05-22 2003-02-17 삼성전자주식회사 프리페치 동작모드를 가지는 반도체 메모리 장치 및 메인데이터 라인수를 줄이기 위한 데이터 전송방법
US6748039B1 (en) 2000-08-11 2004-06-08 Advanced Micro Devices, Inc. System and method for synchronizing a skip pattern and initializing a clock forwarding interface in a multiple-clock system
GB0211173D0 (en) * 2002-05-16 2002-06-26 Zarlink Semiconductor Inc Virtual counter for data rate conversion
KR20040022102A (ko) * 2002-09-06 2004-03-11 위니아만도 주식회사 김치저장고의 표시장치
KR102681179B1 (ko) * 2017-01-23 2024-07-04 에스케이하이닉스 주식회사 메모리 모듈

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3577086A (en) * 1968-09-30 1971-05-04 Ivan M Kliman Generator of delayed sequences employing shift register techniques
US4287577A (en) * 1979-09-27 1981-09-01 Communications Satellite Corporation Interleaved TDMA terrestrial interface buffer
JPH07113821B2 (ja) * 1986-04-21 1995-12-06 日本テキサス・インスツルメンツ株式会社 半導体記憶装置
US4785415A (en) * 1986-08-29 1988-11-15 Hewlett-Packard Company Digital data buffer and variable shift register
JPH083956B2 (ja) * 1986-09-18 1996-01-17 日本テキサス・インスツルメンツ株式会社 半導体記憶装置
EP0272869B1 (fr) * 1986-12-19 1993-07-14 Fujitsu Limited Dispositif de mémoire à semi-conducteurs à double accès effectuant une opération de lecture à haute vitesse

Also Published As

Publication number Publication date
DE68925307T2 (de) 1996-05-30
US4945518A (en) 1990-07-31
EP0345807B1 (fr) 1996-01-03
KR920003754B1 (ko) 1992-05-09
KR910001777A (ko) 1991-01-31
EP0345807A3 (fr) 1991-09-25
EP0345807A2 (fr) 1989-12-13
JPH01310433A (ja) 1989-12-14
DE68925307D1 (de) 1996-02-15

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees