JPH0658945B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0658945B2 JPH0658945B2 JP57215277A JP21527782A JPH0658945B2 JP H0658945 B2 JPH0658945 B2 JP H0658945B2 JP 57215277 A JP57215277 A JP 57215277A JP 21527782 A JP21527782 A JP 21527782A JP H0658945 B2 JPH0658945 B2 JP H0658945B2
- Authority
- JP
- Japan
- Prior art keywords
- input
- semiconductor device
- resistor
- polycrystalline silicon
- field oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
Landscapes
- Protection Of Static Devices (AREA)
- Amplifiers (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 本発明は半導体装置、特に内部回路としてのＭＯＳ型電
界効果トランジスタの集積装置（以下「ＭＯＳＩＣ」と
略記する）に関するもので、ＭＯＳＩＣの信号用入力出
力端子とクランプ保護ダイオード等からなる破壊防止用
素子とを、多結晶シリコンを用いて電気的に接続し、該
多結晶シリコンの信号伝播方向の長さＬと、上記多結晶
シリコン長と直交をなす方向の幅Ｗの比、L/Wをマスク
上で５以下にして、静電気や、定格以上の高電圧による
ＭＯＳＩＣの破壊に対する耐量を改善すること及び寄生
サイリスタのターンオン現象（以下ラッチアップ現象と
呼ぶ）を誘起することを防止することを目的とする。特
に比例縮小則から大きく逸脱させて入力保護抵抗体の抵
抗率を低下させたり、フィールド酸化膜の膜厚を厚くす
ることなしに、入力パッドと抵抗体とを接続するコンタ
クト部における絶縁膜破壊を防止することを目的とす
る。The present invention relates to a semiconductor device, and more particularly to an integrated device of a MOS field effect transistor (hereinafter abbreviated as “MOSIC”) as an internal circuit, which has a signal input / output terminal for a MOSIC and a clamp protection diode. And a breakdown preventing element made of polycrystal silicon are electrically connected to each other, and the length L of the polycrystal silicon in the signal propagation direction and the width W of the polycrystal silicon in the direction orthogonal to the length of the polycrystal silicon. Ratio, L / W should be 5 or less on the mask to improve the resistance to static electricity and damage to the MOSIC due to high voltage above the rating, and to induce the turn-on phenomenon of the parasitic thyristor (hereinafter referred to as the latch-up phenomenon). The purpose is to prevent. In particular, without deviating significantly from the proportional reduction rule, the resistivity of the input protection resistor is reduced, and without increasing the film thickness of the field oxide film, the insulation film breakdown at the contact portion connecting the input pad and the resistor is prevented. The purpose is to prevent.
ＭＯＳＩＣの静電気等の過大サージによる破壊現象は、
その開発当初からの問題であったため、これまでに各種
の対策が提案され、改良の手が加えられてきた。ところ
が、現在の様にＭＯＳＩＣの集積密度が一段と高まる
と、従来の対策をそのまま上記ＭＯＳＩＣに用いること
は、ＭＯＳ型電界効果トランジスタのゲート酸化膜以外
の絶縁酸化膜（以下「フイールド酸化膜」と呼ぶ）の静
電気破壊や、ＭＯＳＩＣ内に必然的に存在してしまう、
ラツチアツプ現象を招く結果になる。The destruction phenomenon due to excessive surge such as static electricity of MOSIC
Since it was a problem from the beginning of its development, various measures have been proposed and improvements have been made so far. However, when the integration density of the MOSIC is further increased as in the present situation, it is necessary to use the conventional measures as they are for the MOSIC as described above. ) Static electricity destruction and inevitably exist in MOSIC,
This results in a ratcheap phenomenon.
本発明は、上記の状況を十分ふまえ、ＭＯＳＩＣの入出
力端子と破壊防止用保護素子を接続する多結晶シリコン
層の長さＬ及び、幅Ｗの比を改良したものである。ここ
で本発明の入力保護抵抗の長さ、即ち電気的信号伝播方
向に沿った長さとは、実際に抵抗体として作用する部
分、言い換えれば抵抗体の一端のコンタクト部から他端
のコンタクト部との間の長さのことをいう。即ち、第３
図を用いて説明すると、ボンディングパッド１から引き
延ばされた接続用アルミ配線１０４と接続するコンタク
ト部１０７に接続した部分から破壊防止用素子であるク
ランプ保護ダイオード３に接続するためのコンタクト部
１０８の間に位置する多結晶シリコン１０５をいう。In view of the above situation, the present invention has improved the ratio of the length L and the width W of the polycrystalline silicon layer for connecting the input / output terminals of the MOSIC and the protection element for destruction prevention. Here, the length of the input protection resistor of the present invention, that is, the length along the electrical signal propagation direction, refers to the portion that actually acts as a resistor, in other words, from the contact portion at one end of the resistor to the contact portion at the other end. It is the length between. That is, the third
Explaining with reference to the drawings, a contact portion 108 for connecting from the portion connected to the contact portion 107 connected to the connecting aluminum wiring 104 extended from the bonding pad 1 to the clamp protection diode 3 which is a destruction prevention element. The polycrystalline silicon 105 located between the two.
従来の相補型絶縁ゲート半導体集積装置（以下「Ｃ−Ｍ
ＯＳＩＣ」と略す）の入出力端子における代表的な破壊
保護回路は、第１図に示す如く、入力パッドとしてのボ
ンデイングパツド１に入った信号が、保護抵抗２，クラ
ンプ保護ダイオード３に電位を与えたのち、内部回路で
あるＣ−ＭＯＳＩＣの入力部としての入力ゲート４に伝
えられる回路になっており、その保護抵抗２は、第２図
ａに示す如く、Ｎ型半導体１０１中に設けられた、該半
導体基板１０１の導電型とは異なる導電型、すなわちＰ
型拡散層１０２によって形成されるか、第２図ｂに示す
如く、半導体基板１０１の表面上にフイールド酸化膜１
０３を形成され、次いでフイールド酸化膜１０３の表面
上に多結晶シリコン層１０５を設けることによって、上
記保護抵抗２が得られている。この様な構造によって静
電気等の破壊耐量は向上してきたが、上記でも説明した
様に、ＭＯＳＩＣが高集積化されると、Ｐ型拡散層１０
２による保護抵抗２の形成は、Ｃ−ＭＯＳＩＣ特有のラ
ツチアツプ現象を引き起し易くするという欠点を有して
いる。ところで、このラツチアツプ現象は、従来の半導
体装置、例えば、特公昭５５−２９１３９号公報の明細
書に示されている如く、半導体基板中に高濃度拡散層を
設けた構造で半導体基板の電位勾配をなくし、かつ、Ｍ
ＯＳ型電界効果トランジスタのマスク上のレイアウトを
変更することによって、寄生サイリスタ特性を劣化させ
て、生じにくくすることが可能であるが、高集積度のＭ
ＯＳＩＣにおいては、更に上記P+拡散層１０２に代り、
保護抵抗として多結晶シリコン層１０５を採用するのが
望ましい。しかるに該多結晶シリコン層による高抵抗値
の、すなわち、多結晶シリコン長Ｌ／多結晶シリコン幅
Ｗの値が大きい保護抵抗を設けると、ボンデイングパツ
ド１に加った静電気等による過大電圧が、保護ダイオー
ド２を通じて中和されるに要する時間は長くなり、フイ
ールド酸化膜１０３の破壊をもたらす。Conventional complementary insulated gate semiconductor integrated device (hereinafter referred to as "CM
A typical destruction protection circuit at an input / output terminal (abbreviated as “OSIC”) has a signal input to a bonding pad 1 as an input pad, which causes a potential to a protection resistor 2 and a clamp protection diode 3 as shown in FIG. After being given, it is a circuit which is transmitted to the input gate 4 as an input portion of the C-MOSIC which is an internal circuit, and the protection resistor 2 thereof is provided in the N-type semiconductor 101 as shown in FIG. Also, a conductivity type different from that of the semiconductor substrate 101, that is, P
Formed by the mold diffusion layer 102, or as shown in FIG. 2 b, the field oxide film 1 is formed on the surface of the semiconductor substrate 101.
No. 03 is formed, and then the polycrystalline silicon layer 105 is provided on the surface of the field oxide film 103, whereby the protection resistor 2 is obtained. Although the breakdown resistance against static electricity and the like has been improved by such a structure, as described above, when the MOSIC is highly integrated, the P-type diffusion layer 10 is formed.
The formation of the protection resistor 2 by 2 has a drawback that it is easy to cause a latch-up phenomenon peculiar to the C-MOS IC. By the way, this latch-up phenomenon is caused by the conventional semiconductor device, for example, in the structure in which a high-concentration diffusion layer is provided in a semiconductor substrate as shown in the specification of Japanese Patent Publication No. 55-29139, the potential gradient of the semiconductor substrate is Lost and M
By changing the layout on the mask of the OS type field effect transistor, it is possible to deteriorate the parasitic thyristor characteristics and make it difficult to occur, but it is possible to obtain high integration density of M.
In the OSIC, instead of the P + diffusion layer 102,
It is desirable to adopt the polycrystalline silicon layer 105 as the protection resistance. However, when a protective resistor having a high resistance value due to the polycrystalline silicon layer, that is, a large value of the polycrystalline silicon length L / the polycrystalline silicon width W is provided, an excessive voltage due to static electricity applied to the bonding pad 1 is generated. The time required for neutralization through the protection diode 2 becomes long, and the field oxide film 103 is destroyed.
従って本発明は、第３図に示す如く、ボンデイングパツ
ド１とクランプ保護ダイオード３とを接続する多結晶シ
リコン１０５の長さＬと幅Ｗの比L/Wを５以下にして、
ラツチアツプ現象を避けつつ、過大入力電圧によるフイ
ールド酸化膜の破壊という欠点を除去せしめたものであ
る。従来の様に、L/Wを大きくとったものと比較する
と、例えば、多結晶シリコンのL/Wを10とした時、入力
端子と半導体基板間に４００〜５００ボルトの電圧が瞬
間的に加わっただけで、ボンデイングパツド１からの接
続用アルミ配線１０４と多結晶シリコン１０５とのコン
タクト部１０７において、容易にフイールド酸化膜が破
壊したのに対し、L/W＝５での同条件では、フイールド
酸化膜破壊は全く出現せず、また、ラツチアツプ耐量は
L/W＝10のそれと同水準であった。ちなみに抵抗体の多
結晶シリコン１０５の膜厚は、４５００Åであり、シー
ト抵抗は、１０Ω／□である。Therefore, according to the present invention, as shown in FIG. 3, the ratio L / W of the length L and the width W of the polycrystalline silicon 105 connecting the bonding pad 1 and the clamp protection diode 3 is set to 5 or less,
It avoids the latch-up phenomenon and eliminates the defect that the field oxide film is destroyed by an excessive input voltage. Compared to the conventional one with a large L / W, for example, when the L / W of polycrystalline silicon is 10, a voltage of 400 to 500 V is instantaneously applied between the input terminal and the semiconductor substrate. However, the field oxide film was easily destroyed at the contact portion 107 between the connecting aluminum wiring 104 from the bonding pad 1 and the polycrystalline silicon 105, but under the same condition at L / W = 5, No field oxide breakdown appears, and the ratchet up capacity is
It was at the same level as that of L / W = 10. By the way, the film thickness of the polycrystalline silicon 105 of the resistor is 4500Å, and the sheet resistance is 10Ω / □.
なお第２図乃至第３図において、１０６はフイールド酸
化膜、１０８はコンタクトホールである。In FIGS. 2 to 3, 106 is a field oxide film and 108 is a contact hole.
以上述べた様に、本発明は、ＭＯＳＩＣの微細化を進め
る上でフイールド酸化膜厚を薄くする際遭遇する、定格
外の高電圧や、静電気によるフイールド酸化膜の破壊を
防ぐために十分な効果が発揮されるとともにラツチアツ
プを防止する。即ち、本発明はボンディングパッドから
の配線と抵抗体とを接続するコンタクト部において生じ
るフィールド絶縁膜破壊を防止するために、具体的には
印加された静電荷がボンディングパッド周辺から速やか
に放電するように、一端がボンディングパッドに接続す
るコンタクト部ともう一端が破壊防止用素子に接続する
コンタクト部とに挟まれた抵抗体の電気的伝播方向の長
さとそれに直交する幅の比を６以下にすることを特徴と
しております。またこの構成により同時にラツチアツプ
現象を回避することができるという効果も有するもので
ある。As described above, the present invention has a sufficient effect to prevent the breakdown of the field oxide film due to high voltage outside the rating or static electricity, which is encountered when thinning the field oxide film in advancing the miniaturization of MOSIC. It is demonstrated and prevents ratchet up. That is, according to the present invention, in order to prevent the breakdown of the field insulating film that occurs in the contact portion that connects the wiring from the bonding pad and the resistor, specifically, the applied electrostatic charge is quickly discharged from the periphery of the bonding pad. In addition, the ratio of the length in the electrical propagation direction of the resistor sandwiched between the contact portion whose one end is connected to the bonding pad and the contact portion whose other end is connected to the destruction prevention element and the width orthogonal thereto is 6 or less. It is characterized by that. Further, this structure also has an effect that the ratchet up phenomenon can be avoided at the same time.
本発明の構成によると、半導体装置が微細化されても、
それに伴って内部回路のゲート絶縁膜等の絶縁膜破壊と
フィールド酸化膜の絶縁膜破壊という２つの破壊モード
に対して有効な入力保護抵抗体を提供することが可能と
なるという顕著な効果を有するものである。According to the configuration of the present invention, even if the semiconductor device is miniaturized,
Along with that, there is a remarkable effect that it is possible to provide an input protection resistor effective against two breakdown modes of breakdown of an insulating film such as a gate insulating film of an internal circuit and breakdown of an insulating film of a field oxide film. It is a thing.
また周知の方法として、いちいち静電気破壊耐性を増す
ために、比例縮小則に従うことなく抵抗体の抵抗率を低
下させたり、フィールド酸化膜の膜厚を厚くするという
煩雑な方法をとることなしに、半導体装置の信頼性上必
要な静電破壊耐圧を得ることができるので、設計効率が
向上し、また製造工数も増加しないので、半導体装置の
信頼性が増すという効果も有するものである。Further, as a well-known method, in order to increase the electrostatic breakdown resistance one by one, without lowering the resistivity of the resistor without following the proportional reduction rule, or without taking the complicated method of increasing the film thickness of the field oxide film, Since the electrostatic breakdown voltage necessary for the reliability of the semiconductor device can be obtained, the design efficiency is improved, and the number of manufacturing steps is not increased, so that the reliability of the semiconductor device is also increased.
第１図は、従来のＣ−ＭＯＳＩＣの入力端子における破
壊保護を示す回路図。第２図は従来の保護抵抗の構造を
説明するための断面図。第３図は本発明による破壊保護
機構を示すパターン図である。 １０１……半導体基板 １０３……フイールド酸化膜 １０５……多結晶シリコンFIG. 1 is a circuit diagram showing destruction protection at an input terminal of a conventional C-MOS IC. FIG. 2 is a sectional view for explaining the structure of a conventional protection resistor. FIG. 3 is a pattern diagram showing a destruction protection mechanism according to the present invention. 101 ... Semiconductor substrate 103 ... Field oxide film 105 ... Polycrystalline silicon
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 27/088 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI technical display area H01L 27/088
Claims (1)
タ及び破壊防止用素子を構成要素とし、前記ＭＯＳ型電
界効果トランジスタ及び前記破壊防止用素子と前記パッ
ドとの間に入力保護抵抗体を電気的に接続する半導体装
置において、前記入力保護抵抗体は半導体基板上に絶縁
膜を介して設けられ、かつ電気的信号伝播方向に沿った
長さに対する電気的信号伝播方向と直交する幅の比が、
５以下となる多結晶シリコンからなるものであることを
特徴とする半導体装置。1. An input pad, a MOS type field effect transistor, and a destruction prevention element are components, and an input protection resistor is electrically provided between the pad and the MOS type field effect transistor and the destruction prevention element. In the semiconductor device to be connected, the input protection resistor is provided on the semiconductor substrate via an insulating film, and the ratio of the width orthogonal to the electrical signal propagation direction to the length along the electrical signal propagation direction is
A semiconductor device comprising a polycrystalline silicon of 5 or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57215277A JPH0658945B2 (en) | 1982-12-07 | 1982-12-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57215277A JPH0658945B2 (en) | 1982-12-07 | 1982-12-07 | Semiconductor device |
Related Child Applications (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4058162A Division JPH0758737B2 (en) | 1992-03-16 | 1992-03-16 | Semiconductor device |
| JP4058161A Division JPH0758736B2 (en) | 1992-03-16 | 1992-03-16 | Semiconductor device |
| JP4058163A Division JPH0758738B2 (en) | 1992-03-16 | 1992-03-16 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59105369A JPS59105369A (en) | 1984-06-18 |
| JPH0658945B2 true JPH0658945B2 (en) | 1994-08-03 |
Family
ID=16669643
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57215277A Expired - Lifetime JPH0658945B2 (en) | 1982-12-07 | 1982-12-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0658945B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61263276A (en) * | 1985-05-17 | 1986-11-21 | Matsushita Electronics Corp | Semiconductor device |
| JP6958474B2 (en) * | 2017-09-28 | 2021-11-02 | 三菱電機株式会社 | Silicon carbide semiconductor device |
| CN115497412A (en) * | 2022-10-11 | 2022-12-20 | 摩星半导体(广东)有限公司 | Display driving system, display panel and display device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51120684A (en) * | 1975-04-16 | 1976-10-22 | Agency Of Ind Science & Technol | Semicondactor resistance element |
| JPS53116788A (en) * | 1977-03-23 | 1978-10-12 | Toshiba Corp | Circuit element structuring body |
| JPS562664A (en) * | 1979-06-21 | 1981-01-12 | Nec Corp | Semiconductor device |
| JPS56146277A (en) * | 1980-04-15 | 1981-11-13 | Toshiba Corp | Semiconductor device |
| JPS5724563A (en) * | 1980-07-21 | 1982-02-09 | Nec Corp | Semiconductor device |
-
1982
- 1982-12-07 JP JP57215277A patent/JPH0658945B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59105369A (en) | 1984-06-18 |
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