JPH0697376A - Semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] BiC including output buffer, suppressing the effect of power supply noise due to precharging of array peripheral circuits etc.
The power supply margin of a MOS dynamic RAM or the like is increased. In addition, the output transistor T that constitutes the output buffer
The saturation of 1 is prevented and the reliability of the BiCMOS dynamic RAM including the output buffer is improved. An array peripheral circuit including a memory array and an array peripheral circuit using a power supply voltage VCC as its operating power supply, an output transistor T1 provided between a power supply voltage VCCO and a data output terminal IO0, and a P-channel drive MOSFET P1. In a BiCMOS dynamic RAM or the like including an output drive circuit that drives the output transistor T1 in accordance with the substantial output signal of the above, that is, an inverter IV1, at least the source of the drive MOSFET P1 is supplied with the power supply voltage VCCO to stabilize the base potential of the output transistor T1. And prevent its saturation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
For example, a bipolar CMO with a data output buffer
S (hereinafter abbreviated as BiCMOS) dynamic RAM
The present invention relates to a technology that is particularly effective when used for (random access memory) and the like.

[0002]

2. Description of the Related Art A memory array in which one-element type dynamic memory cells are arranged in a lattice and a BiCMOS circuit in which a bipolar circuit and a CMOS (complementary MOS) circuit are combined are basic array peripheral circuits. And a BiCMOS dynamic type R that realizes high-speed operation while achieving high circuit integration and low power consumption.
I have AM. The BiCMOS dynamic RAM includes a plurality of data output buffers provided corresponding to a plurality of bits of stored data that are simultaneously output.

BiC having a plurality of data output buffers
The MOS dynamic RAM is described, for example, in Japanese Patent Application No. 1-65841.

[0004]

Prior to the present invention, the inventors of the present invention have proposed the conventional BiC as described above.
A data output buffer as shown in FIG. 6 that can be used for a MOS dynamic RAM or the like has been developed. The data output buffer DOB0 has a power supply voltage VCCO and a data input / output terminal I.
An output transistor (a bipolar transistor is simply referred to as a transistor in this specification) T1 provided between O0 and an N-channel type output provided between the data input / output terminal IO0 and the ground potential VSSO. MOSFET (metal oxide semiconductor field effect transistor. In this specification, MOSFET is referred to as a general term for an insulated gate field effect transistor) N4. A CMOS type inverter IV1 is provided in the front stage of the output transistor T1, and the non-inverted output signal D of the data latch DL is provided at one of its input terminals in the front stage.
Receiving T (here, a so-called non-inverted signal that is selectively set to a high level when it is valid is indicated by adding T to the end of the name. The same applies hereinafter) to the other input terminal. A NAND gate NA1 that receives an internal control signal DOE serving as an output control signal is provided. Further, a BiCMOS type inverter IV2 is provided in the front stage of the output MOSFET N4, and further in the front stage thereof.
An inverted output signal DB of the data latch DL is input to one of the input terminals (here, a so-called inverted signal that is selectively brought to a low level when it is enabled is indicated by adding B to the end of the name. A NAND gate NA2 for receiving the internal control signal DOE is provided at the other input terminal for receiving the same).

The memory array and array peripheral circuit of the BiCMOS dynamic RAM including the inverters IV1 and IV2, the NAND gates NA1 and NA2, the data latch DL, and the level conversion circuit LC are supplied with the power supply voltage VCC and the ground potential VSS serving as the main power supply. As the operating power supply, as described above, the operating transistor is supplied with the power supply voltage VCCO and the ground potential VSSO supplied through the external terminals VCCO and VSSO, which are independent of the output transistor T1 and the output MOSFET N4 that drive a relatively large load capacitance. By this, it is possible to prevent the operation margin of the memory array and the array peripheral circuit from being deteriorated by the power supply noise accompanying the load driving, and the BiCMOS dynamic RAM
It is intended to promote stabilization of the operation of.

However, BiCMOS dynamic type R
It has been made clear by the inventors of the present application that the conventional data output buffer described above has the following problems as the power supply voltage thereof is reduced as the miniaturization and higher integration of AM and the like progresses. It was That is, in the data output buffer, as shown in FIG.
When the chip enable signal CEB is returned to the high level during this period, read data is output from the data input / output terminals IO0 and the like, but its operating current is relatively large due to precharging of the array peripheral circuits and the like. The power supply voltage Vcc changes and a relatively large power supply noise is superimposed on the power supply voltage VCC. This power supply noise fluctuates the base potential of the output transistor T1 via the P-channel drive MOSFET P1 that constitutes the inverter IV1, particularly at the time of high-level output, so that the data input / output terminal IO
The signal level of read data at 0 fluctuates. When the collector potential of the output transistor T1, that is, the power supply voltage VCCO becomes lower than the base potential thereof, that is, the power supply voltage VCC for the memory array and the array peripheral circuit, the output transistor T1 is saturated, and majority carriers flow into the semiconductor substrate to cause memory cells. The stored data of may be destroyed. These cause a decrease in power supply margin and a decrease in reliability particularly in a BiCMOS dynamic RAM in which the power supply voltage has been lowered.

An object of the present invention is to suppress the influence of power supply noise caused by precharging of array peripheral circuits and the like, and increase the power supply margin of BiCMOS dynamic RAM and the like including an output buffer. Another object of the present invention is to prevent the saturation of the output transistor which constitutes the output buffer and to improve the reliability of the BiCMOS dynamic RAM including the output buffer.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, a memory array and an array peripheral circuit using the first power supply voltage as an operating power supply, an output transistor provided between the second power supply voltage and an output terminal of the circuit, and a P-channel drive MOSFET are included in the array periphery. And an output drive circuit for driving the output transistor according to a substantial output signal of the circuit.
In the dynamic RAM or the like, the second power supply voltage is supplied to at least the source of the drive MOSFET that constitutes the output drive circuit.

[0010]

According to the above means, the base potential of the output transistor is stabilized and the output of the circuit is stabilized even when a relatively large power supply noise is superimposed on the first power supply voltage due to the precharge of the array peripheral circuit or the like. The level fluctuation of the output signal at the terminal can be suppressed. Further, the collector potential of the output transistor, that is, the second power supply voltage is the first
Even when the voltage becomes lower than the power supply voltage of 1, the output transistor can be prevented from being saturated and the majority carriers can be prevented from flowing into the memory cell. As a result, it is possible to increase the power supply margin of the BiCMOS dynamic RAM or the like in which the power supply voltage has been lowered, and to improve its reliability.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a BiCMO to which the present invention is applied.
A block diagram of one embodiment of an S-dynamic RAM is shown. Based on the figure, first, the BiCMO of this embodiment is
An outline of the configuration and operation of the S dynamic RAM and its features will be described. The circuit elements forming each block in FIG. 1 are not particularly limited, but known BiCM
It is formed on one semiconductor substrate such as single crystal silicon by a manufacturing technique of an OS integrated circuit.

In FIG. 1, the BiCMOS of this embodiment is shown.
The basic structure of the dynamic RAM is a memory module MOD arranged so as to occupy most of the semiconductor substrate surface. The memory module MOD includes four memory mats (not shown), and each memory mat includes a memory array, an X address decoder, a column switch and a Y address decoder. Memory module MOD
Further includes a total of eight main amplifiers MA0 to MA7 provided in twos corresponding to the four memory mats. These main amplifiers are connected to two designated memory cells of a corresponding memory mat of the memory module MOD, that is, a corresponding memory array via two corresponding sets of write complementary common data lines or read complementary common data lines. Connected selectively. As a result, in the BiCMOS dynamic RAM of this embodiment, eight memory cells, two from each memory mat of the memory module MOD, are selected at the same time, and are connected to the corresponding main amplifiers MA0 to MA7. It In this embodiment, the memory array, the array peripheral circuit, and the like which constitute the memory module MOD are supplied as a main power supply through a power supply voltage VCC (first power supply voltage) supplied via an external terminal VCC and an external terminal VSS. The ground potential VSS is used as the operating power supply. The power supply voltage VCC
Is a positive power supply voltage such as + 3V. A detailed description of the structure and operation of the memory module MOD is omitted because it is not directly related to the present invention.

BiCMOS dynamic RAM includes
A chip enable signal CEB, a write enable signal WEB, and an output enable signal OEB, which are activation control signals, are supplied via the external terminals CEB, WEB, and OEB, respectively. These start control signals are supplied to the timing generation circuit TG, and various internal control signals for controlling the operation of each unit are formed based on these.

On the other hand, BiCMOS dynamic RAM
Through the address input terminals AX0 to AXi to i + 1
Bit X address signals AX0 to AXi are supplied, and j + 1 bit Y address signals AY0 to AYj are supplied via address input terminals AY0 to AYj. Of these, the X address signals AX0 to AXi are fetched by the X address buffer XAB according to an internal control signal XL (not shown), and then supplied as internal address signals X0 to Xi to the X address decoder of the memory module MOD. Similarly, the Y address signals AY0 to AYj are supplied to the Y address buffer Y according to an internal control signal YL (not shown).
After being taken into AB, it is supplied to the Y address decoder of the memory module MOD as internal address signals Y0 to Yj. Therefore, in the memory module MOD,
X address signals AX0 to AXi and Y address signal AY
8 memory cells designated by 0 to AYj are simultaneously selected, and corresponding main amplifiers MA0 to MA
Connected to 7.

In BiCMOS dynamic RAM,
Further, 3-bit Z address signals AZ0 to AZ2 are supplied via address input terminals AZ0 to AZ2. These Z address signals are internal control signals ZL (not shown).
According to the above, it is fetched into the Z address buffer ZAB and decoded by the main amplifier selection circuit MSL. The output signals of the main amplifier selection circuit MSL are corresponding main amplifiers MA0 to MA0 as main amplifier selection signals Z0 to Z7.
It is supplied to the MA 7 and the data selectors DS20 to DS23 and DS8. As a result, the main amplifier MA0
To MA7 are selectively activated in a predetermined combination, or the output signal thereof is the data output buffer DOB.
It is selectively output via 0 to DOB3.

By the way, in the BiCMOS dynamic RAM of this embodiment, a predetermined coupling wiring is selectively formed so that the bit configuration is selectively set to x4 bit or x1 bit configuration. That is, when the coupling wiring shown by the solid line in FIG. 1 is formed, the BiCMOS dynamic RAM has a x4 bit structure, and the stored data is simultaneously input by 4 bits at a time through the four data input / output terminals IO0 to IO3. Is output. At this time, the main amplifier selection signals Z0 to Z7 are selectively formed simultaneously by 4 bits in accordance with the Z address signal AZ2. Therefore, for example, in the write mode, the data input / output terminal IO
Data input buffers DIB0 to DIB3 from 0 to IO3
4-bit write data inputted via two main amplifiers MA0 and MA1 to MA6 adjacent to each other.
, And MA7, the data is simultaneously written into four designated memory cells of the memory module MOD. In the read mode, the read signals output from the eight designated memory cells of the memory module MOD via the main amplifiers MA0 to MA7 are selected by the corresponding data selectors DS20 to DS23. After that, the data is simultaneously sent out via the corresponding data output buffers DOB0 to DOB3 and the data input / output terminals IO0 to IO3.

On the other hand, when the coupling wiring shown by the dotted line in FIG.
It has a 1-bit configuration and the stored data is stored in the data input terminal D.
Input or output bit by bit via in or the data output terminal Dout. At this time, the main amplifier selection signals Z0 to Z7 are the 3-bit Z address signals AZ0 to AZ.
2 is formed alternatively. Therefore, in the write mode, for example, 1-bit write data input from the data input terminal Din via the data input buffer DIB0 is designated by the memory module MOD via any one of the main amplifiers MA0 to MA7. It is written in the one memory cell that has been written. In the read mode, the read signal output from the eight designated memory cells of the memory module MOD via the main amplifiers MA0 to MA7 is selectively selected by the data selector DS8, and then the data output buffer is selected. DOB
1 and the data output terminal Dout.

In this embodiment, the data output buffers DOB0 to DOB3 each include a bipolar output transistor having a relatively large driving capability, as will be described later, and a part of the circuit including this output transistor has an external terminal VCCO. Power supply voltage VCCO (second
Power supply voltage) is used as the operating power supply. Power supply voltage VCCO
Is a power supply voltage VCC supplied through an external terminal VCC and used as an operating power supply for the memory array and array peripheral circuits.
The same potential as that of the above, but the operating power supplies for the output transistors and the like, which require a relatively large operating current, and the operating power supplies for the memory array and array peripheral circuits are supplied via separate external terminals. And the data output buffer D
A BiCMOS dynamic RAM is provided which suppresses the influence of power supply noise on the memory array and the array peripheral circuit due to the simultaneous operation of OB0 to DOB3.
The operation of can be stabilized.

FIG. 2 shows a circuit diagram of a first embodiment of the data output buffer DOB0 included in the BiCMOS dynamic RAM shown in FIG. 1, and FIG. 3 shows a circuit diagram of the second embodiment. It is shown. Further, FIG. 4 shows a cross-sectional structural view of one embodiment of the output transistor T1 and the driving MOSFET P2 included in the data output buffer DOB0 of FIG. 3, and FIG. 5 shows the data output buffer DOB0 of FIG. 2 and FIG. A signal waveform diagram of one embodiment is shown.
Based on these figures, the specific configuration and operation of the data output buffer of this embodiment and its characteristics will be described. In the following description, the data output buffer DOB0 will be taken as an example, but the data output buffers DOB1 to DOB3 will be described.
For, the circuit configuration is similar to that of the data output buffer DOB0. In the circuit diagrams below, MOSFETs whose channels (back gates) are indicated by arrows
Is a P-channel type (first conductivity type) and is shown separately from an N-channel MOSFET without an arrow.
Further, the illustrated transistors are all NPN type bipolar transistors.

In FIG. 2, the data output buffer DOB
0 is provided with a level conversion circuit LC and a data latch DL, although not particularly limited. Of these, the level conversion circuit L
C has a non-inverted output signal D2 of the data selector DS20.
0T and the inverted output signal D20B are supplied. Further, the data latch DL is supplied with the non-inverted and inverted output signals of the level conversion circuit LC, and is supplied with the internal control signal DOE from the timing generation circuit TG. The non-inverted output signal D20T and the inverted output signal D20B of the data selector DS20 are so-called ECL (Emitter Co).
It is set to the "upled Logic" level. Further, as shown in FIG. 5, when the chip enable signal CEB is set to the low level and the BiCMOS dynamic RAM is in the selected state, the internal control signal DOE is selectively set to the high level in response to the change of the output enable signal OEB to the low level. It is a level.

The level conversion circuit LC of the data output buffer DOB0 outputs the non-inverted output signal D20T and the inverted output signal D20B of the data selector DS20 which have a relatively small signal amplitude such as ECL level, that is, 0.8V,
It is converted into a MOS level that is fully swung between the power supply voltage VCC and the ground potential VSS and transmitted to the data latch DL. When the internal control signal DOE is low level, the data latch DL transmits the non-inverted and inverted output signals of the data latch DL set to the MOS level to the subsequent circuit as they are, and when the internal control signal DOE is high level. ,
Continues to hold the logic level immediately before that. Therefore, as shown in FIG. 5, the non-inverted output signal DT and the inverted output signal DB of the data latch DL are the non-inverted read data of the data selector DS20 when the read data of the specified memory cell is selected in the BiCMOS dynamic RAM. And valid by being established at the inverting output terminal (Va
Then, the inverted internal control signal DOEB is returned to the high level to bring it into the invalid state.

The data output buffer DOB0 further includes
An output transistor T1 provided between the power supply voltage VCCO and the output terminal of the circuit, that is, the data input / output terminal IO0.
And an N-channel type output MOSFET N4 provided between the data input / output terminal IO0 and the ground potential VSSO. Among these, the inverted signal of the output signal of the NAND gate NA1 by the CMOS inverter IV1 (output drive circuit) is supplied to the base of the output transistor T1, and the output signal of the NAND gate NA2 of the BiCMOS type is supplied to the gate of the output MOSFET N4. Inverter IV2
The inverted signal is supplied. The non-inverted output signal DT of the data latch DL is supplied to one input terminal of the NAND gate NA1, and the inverted output signal DB thereof is supplied to one input terminal of the NAND gate NA2. The internal control signal DOE is commonly supplied to the other input terminals of the NAND gates NA1 and NA2.

In this embodiment, the source of the P-channel drive MOSFET P1 which constitutes the inverter IV1 is supplied with the second power supply voltage, that is, the power supply voltage VCCO, and the inverter IV1 uses this power supply voltage VCCO as its operating power supply. To do. The first power supply voltage, that is, the power supply voltage VCC is supplied to the source of the P-channel drive MOSFET P2 and the collector of the transistor T2 that form the inverter IV2, and the inverter IV2
Is the power supply voltage V along with the NAND gates NA1 and NA2.
CC is the operating power supply.

When the internal control signal DOE is set to low level, in the data output buffer DOB0, the output signals of the NAND gates NA1 and NA2 are set to high level regardless of the non-inverted and inverted output signals of the data latch DL. Therefore, the output signals of the inverters IV1 and IV2 are both set to the low level, and the output transistor T1 and the output M are output.
Both OSFETN4 are turned off. As a result, the data input / output terminal IO0 is brought into a so-called high impedance state.

Next, BiCMOS dynamic RAM
Is selected in the read mode and the internal control signal DOE
Is high level, the data output buffer DOB
At 0, the output signal of the NAND gate NA1 is the non-inverted output signal DT of the data latch DL, that is, the data selector DS2.
The non-inverted output signal D20T of 0 is selectively set to the low level on condition that it is at the high level, and the NAND gate NA2
Is selectively set to the low level on condition that the inverted output signal DB of the data latch DL, that is, the inverted output signal D20B of the data selector DS20 is at the high level. When the output signal of the NAND gate NA1 is at low level, the output signal of the inverter IV1 is at high level, which turns on the output transistor T1. As a result, the data input / output terminal IO0 is set to a predetermined high level that is lower than the power supply voltage VCCO by the base-emitter voltage of the output transistor T1. On the other hand, when the output signal of the NAND gate NA2 is at low level,
The output signal of the inverter IV2 is set to a high level such as the power supply voltage VCC, whereby the output MOSFET N4
Is turned on. As a result, the data input / output terminal IO
0 is set to a low level like the ground potential VSSO.

By the way, in the data output buffer DOB0 of this embodiment, as described above, the output transistor T1 is used.
Of the inverter IV1 provided in the preceding stage of the power supply voltage VCC
The power supply voltage VCCO is supplied to the source of the drive MOSFET P1 with O as its operating power supply. For this reason,
As shown in FIG. 5, at the time of high level output, the chip enable signal CEB is returned to the high level while the internal control signal DOE is kept at the high level, so that the array peripheral circuits are precharged and the power supply voltage VCC is supplied. Even when a relatively large power supply noise is superimposed on, the base potential of the output transistor T1 is stabilized, and thus the signal level of the read data output via the data input / output terminal IO0 is stabilized. Similarly, at the time of high level output, even if the potential of the power supply voltage VCCO is set lower than the power supply voltage VCC, the output transistor T1 can be prevented from being saturated and the majority carriers can be prevented from flowing in.
As a result of these, BiC in which the power supply voltage has been particularly lowered
The power supply margin of the MOS dynamic RAM can be increased and its reliability can be improved.

The output transistor T1 can be constituted by a so-called double collector type transistor, as shown in FIG.
Can be more reliably prevented. At this time, the P-channel type drive MOSFET P1 forming the inverter IV1 can be formed integrally with the output transistor T1 as shown in FIG.

That is, in FIG. 4, the output transistor T1 uses the N-type buried layer NBL formed at a relatively deep position of the P-type semiconductor substrate PSUB as its collector. The N-type buried layer NBL has N-type diffusion layers C formed on both sides.
1 and C2 are coupled to the power supply voltage VCCO, and an N ⁻ diffusion layer N ^{− serving as} a collector region of the output transistor T1 is formed on the upper layer thereof together with the N type buried layer NBL. The output transistor T1 is provided inside the N ⁻ diffusion layer N ^−.
A P-type diffusion layer DP2 serving as the base of the output transistor T1 is formed inside the P-type diffusion layer DP2.
An N-type diffusion layer DN1 serving as the emitter of is formed.

In this embodiment, the P type diffusion layer DP2
Is shared as the drain of the drive MOSFET P1,
N ^- diffusion layer the N ^- Inside the further the N ^- diffusion layer N ^-
As an N-type well region, a P-type diffusion layer DP1 serving as a source of the drive MOSFET P1 is formed. P type diffusion layer D
In the middle of P1 and DP2, that is, in the upper layer of the channel,
A polysilicon gate layer FG which will be the gate of MOSFET P1 is formed across a predetermined insulating film. P-type diffusion layer DP1 is coupled to the collector of output transistor T1, ie, power supply voltage VCCO. In addition, the P-type diffusion layer DP
2 is coupled to the drain of MOSFET N1 that forms an inverter IV1 together with MOSFET P1, and N-type diffusion layer DN1 is coupled to the drain of output MOSFET N4 and to data input / output terminal IO0.

As described above, the P-type diffusion layer DP1 serving as the source region of the driving MOSFET P1 is connected to the output transistor T
In the N ⁻ diffusion layer N ^{− serving as} the collector region of 1, that is, N
^- diffusion layer N ^- form as well area, by sharing the P-type diffusion layer DP2 serving as a drain of the base of the output transistor T1, to integrate the drive MOSFETP1 and the output transistor T1, the data output buffer DO
The required layout area as B0 can be reduced, and the operation speed can be increased.

By applying the present invention to a semiconductor device such as a BiCMOS dynamic RAM provided with a data output buffer as shown in the above embodiment, the following operational effects can be obtained. That is, (1) a memory array and an array peripheral circuit that use a first power supply voltage as an operating power supply, an output transistor provided between the second power supply voltage and an output terminal of the circuit, and a P-channel drive MOSFET. BiCMOS dynamic RAM including an output drive circuit for driving the output transistor according to a substantial output signal of the array peripheral circuit
And the like, by supplying the second power supply voltage to at least the source of the drive MOSFET forming the output drive circuit, a relatively large power supply noise is superposed on the first power supply voltage due to the precharge of the array peripheral circuit and the like. Even if it is, stabilize the base potential of the output transistor,
The effect that the level fluctuation of the output signal at the output terminal of the circuit can be suppressed is obtained.

(2) According to the above item (1), even if the collector potential of the output transistor, that is, the second power supply voltage becomes lower than the first power supply voltage, the output transistor is prevented from being saturated and a large number of memory cells are provided. It is possible to prevent the carrier from flowing in and prevent the stored data from being destroyed. (3) A BiCMOS dynamic RAM in which the power supply voltage has been particularly lowered by the above items (1) and (2).
It is possible to obtain the effect that the power supply margin such as the above can be increased and the reliability thereof can be improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, a BiCMOS dynamic RA
M can include a plurality of memory modules, and the number of main amplifiers provided in each memory module is arbitrary. In addition, BiCMOS dynamic RA
M can have an arbitrary bit configuration such as x8 bits or x16 bits, and the block configuration and the combination of the activation control signal and the address signal are not restricted by this embodiment.

2 and 3, the output drive circuit provided in the preceding stage of the output transistor T1 and the output MOSFET N4 can take an arbitrary logic gate form, and these output transistors and output MOSFETs are, for example, level conversion circuits. It may also be driven directly by. In this case, the P-channel MOSFET that constitutes the level conversion circuit corresponds to the drive MOSFET P1. Output transistor T1 and output MOSFET N4
Can be replaced with a plurality of transistors and MOSFETs each in parallel form, and output MOS
The FET N4 can be replaced with a bipolar type output transistor. In this embodiment, only the operating power supply for the output transistor T1 and the inverter IV1 that serves as an output drive circuit for the output transistor T1 is set to the power supply voltage VCCO, but the operating power supply for the entire data output buffer may be set to the power supply voltage VCCO. . The output transistor T1 and the drive MOSFET shown in FIG.
The specific device structure of TP1 is not restricted by this embodiment. Furthermore, various embodiments can be adopted for the specific circuit configuration of the data output buffer DOB0 and the like, the polarity and absolute value of the power supply voltage, the conductivity type of the transistor and MOSFET, and the like.

In the above description, the invention made by the present inventor is the field of application which is the background of the invention.
The case where the present invention is applied to the CMOS dynamic RAM has been described, but the present invention is not limited to this.
It can also be applied to a BiCMOS static RAM or a BiCMOS gate array integrated circuit having a similar data output buffer. The present invention relates to at least a bipolar type output transistor and a drive MOS for driving the same.
It can be widely applied to semiconductor devices having an output buffer including an FET.

[0036]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a memory array and an array peripheral circuit using the first power supply voltage as an operating power supply, an output transistor provided between the second power supply voltage and an output terminal of the circuit, and a P-channel drive MOSFET are included in the array periphery. And an output drive circuit for driving the output transistor according to a substantial output signal of the circuit.
In the dynamic RAM or the like, the second power supply voltage is supplied to at least the source of the drive MOSFET. This stabilizes the base potential of the output transistor even when relatively large power supply noise is superimposed on the first power supply voltage due to precharging of the array peripheral circuit and the like, and the level of the output signal at the output terminal of the circuit is stabilized. Fluctuations can be suppressed. Further, even when the collector potential of the output transistor, that is, the second power supply voltage becomes lower than the first power supply voltage, the output transistor is prevented from being saturated,
It is possible to prevent the majority carriers from flowing into the memory cell and prevent the data held therein from being destroyed. As a result of these, BiCM in which the power supply voltage has been particularly lowered
The power supply margin of the OS dynamic RAM or the like can be increased and its reliability can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a BiCMOS dynamic RAM to which the present invention is applied.

FIG. 2 is a circuit diagram showing a first embodiment of a data output buffer DOB0 included in the BiCMOS dynamic RAM of FIG.

3 is a circuit diagram showing a second embodiment of a data output buffer DOB0 included in the BiCMOS dynamic RAM of FIG.

4 is an output transistor T1 and a P-channel MOSFET P included in the data output buffer DOB0 of FIG.
1 is a cross-sectional structure diagram showing one example of Embodiment 1.

5 is a signal waveform diagram showing an embodiment of the data output buffer DOB0 of FIGS. 2 and 3. FIG.

FIG. 6 B developed by the present inventors prior to the present invention
FIG. 6 is a circuit diagram showing an example of a data output buffer DOB0 included in an iCMOS dynamic RAM.

7 is a signal waveform diagram showing an example of the data output buffer DOB0 of FIG.

[Explanation of symbols]

MOD ... Memory module, MA0-MA7 ...
・ Main amplifier, XAB ... X address buffer, Y
AB ... Y address buffer, ZAB ... Z address buffer, MSL ... main amplifier selection circuit, D
S20 to DS23, DS8 ... Output data selector, DOB0 to DOB3 ... Data output buffer,
DIB0 to DIB3 ... Data input buffer, TG
... Timing generator circuit. LC ... Level conversion circuit, DL ... Data latch, NA1-NA2 ...
NAND gate, IV1-IV2 ... Inverter, P1-P2 ... P-channel MOSFET,
N1 to N4 ... N channel MOSFETs, T1 to T
2 ... NPN type bipolar transistor. PSUB
· · · P-type semiconductor substrate, NBL · · · N-type buried layer, N ^-
... N ^- type diffusion layer, C1 to C2, DN1 ... N type diffusion layer, DP1 to DP2 ... P type diffusion layer, FG ... gate layer.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location 9170-4M H01L 27/06 321 J 9170-4M 27/10 325 V

Claims (4)

[Claims] 1. A predetermined internal circuit that uses a first power supply voltage as an operating power supply, an output transistor provided between the second power supply voltage and an output terminal of the circuit, and a second power supply voltage and the output transistor. A semiconductor device, comprising: an output buffer provided between the base and a gate, the output buffer including a drive MOSFET of a first conductivity type for receiving a substantial output signal of the internal circuit. 2. The output transistor comprises a double collector bipolar transistor, one collector of which is coupled to a second power supply voltage and the other collector of which is coupled to a source of the driving MOSFET. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. 3. The output transistor and drive MOSF
3. The semiconductor device according to claim 1 or 2, wherein the ET has a base and a drain which are integrally formed of a common diffusion layer. 4. The semiconductor device is a bipolar CMOS.
A dynamic RAM, the internal circuit and the output buffer are an array peripheral circuit and a data output buffer of the bipolar CMOS dynamic RAM, respectively, and the drive MOSFET is an output drive circuit for the output transistor of the data output buffer. Claim 1 and Claim 2 which constitute what is characterized by the above-mentioned.
Alternatively, the semiconductor device according to claim 3.