JPH1145575A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Problem] To realize a dynamic RAM or the like capable of optimizing its configuration and enhancing a sub-threshold current reduction effect. For example, in a dynamic RAM or the like employing a subthreshold current reduction method, for example, an X address decoder XD, a word line drive circuit WD, and a Y address which require a short recovery time but have a small number of circuits simultaneously activated. The address buffers XB and YB, which have a large number of circuits which are hardly affected by the recovery time and which are simultaneously operated, adopt a switched source method for the address decoder section such as the decoder YD, and the address predecoder XP.
And two random sub-threshold current reduction schemes according to the characteristics of each block constituting a peripheral circuit such as a dynamic RAM by adopting a well potential control scheme in a random logic section such as an XY and timing generation circuit TG. Are selectively combined.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, for example, a dynamic RAM (random access memory) for reducing a sub-threshold current during standby, and a technique particularly effective for use in optimizing its configuration. About.

[0002]

2. Description of the Related Art When a predetermined logic circuit is constructed and active, its high-potential power supply voltage is, for example, a power supply voltage VCC and its low-potential power supply voltage is, for example, a ground potential VSS, that is, 0 V.
(V) of the logic gates whose input signals are fixed at the high level during standby, the high-potential-side power supply voltage is selectively lowered, for example, by about 0.3 V;
A so-called switched source capable of reducing a subthreshold current during standby of a dynamic RAM or the like by selectively increasing the low-potential-side power supply voltage of a logic gate whose input signal is fixed to a low level, for example, by about 0.3 V. (Switched Source) method. In addition, a predetermined logic gate is supplied to a well region such as a P-channel MOSFET (metal oxide semiconductor field effect transistor; in this specification, a MOSFET is generally referred to as an insulated gate field effect transistor). The substrate voltage is set to, for example, the ground potential VSS, that is, 0 V when active, and is set to, for example, -1 during standby
There is also a so-called well potential control method that can similarly reduce the subthreshold current during standby of a dynamic RAM or the like by setting a predetermined negative potential such as V.

[0003]

The above two sub-threshold current reduction methods have advantages and disadvantages corresponding to the basic principle. That is, the switched source method uses a sub power supply voltage supply line for supplying a sub power supply voltage lower than the high potential power supply voltage by about 0.3 V, for example, and a sub ground potential higher than the low potential power supply voltage by about 0.3 V, for example. And a sub-ground potential supply wiring for supplying the same. For this reason, the power supply wiring requiring a relatively large wiring width is divided into two, and the required layout area increases. If the power supply wiring is made thinner to cope with this, the wiring resistance increases, and the high-speed operation of the circuit is hindered. However, in the switched source method, the time required for the circuit to return from the standby state to the active state is shortened due to small parasitic capacitance, and an internal voltage generating circuit for generating a negative substrate voltage is not required.

On the other hand, in the well potential control method, a power supply wiring is not divided into two parts, so that a sufficient wiring width can be secured, and timing control at the time of switching between standby and active states becomes easier as compared with the switched source method. However, since the parasitic capacitance of the well region or the like receiving the substrate voltage is large, the return time of the circuit from the standby state to the active state becomes long, and an internal voltage generating circuit for generating a negative substrate voltage is also required. Particularly, the well potential control is performed by using P-channel and N-channel MOSFETs.
In the case of performing both of the ET and the ET, a so-called triple well (triple well) structure is essential, and the dynamic RA
The manufacturing process of M or the like becomes complicated.

[0005] In a dynamic RAM or the like, each block constituting its peripheral circuit is of a switched source type or a well potential control type in accordance with, for example, the degree of influence on the recovery time and the number of circuits that are simultaneously operating. Has characteristics that easily fit into either. However, in a conventional dynamic RAM or the like, only one of the switched source method and the well potential control method is adopted regardless of the characteristics of each block.
The configuration of M or the like is not optimized, and the effect of each subthreshold current reduction method is not sufficiently exhibited.

SUMMARY OF THE INVENTION An object of the present invention is to realize a dynamic RAM or the like which can optimize its configuration and enhance the effect of reducing a subthreshold current.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0008]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in a dynamic RAM or the like employing a subthreshold current reduction method, for example,
An address decoder such as an X address decoder, a word line drive circuit, and a Y address decoder which requires a short recovery time but has a small number of circuits which are simultaneously operated is provided.
The well-potential control method is adopted for the random logic part such as the address buffer, the address predecoder, and the timing generation circuit, which are less affected by the return time and are operated at the same time. For example, two sub-threshold current reduction methods are selectively combined in accordance with the characteristics of each block constituting a peripheral circuit such as a dynamic RAM. In a circuit adopting a well potential control method, a method in which the well potential is fixed to a potential at which a subthreshold current is reduced and selectively used is adopted.

According to the above-described means, the switched source method or the well potential control method can be selectively adopted for blocks that can be adapted to each of them. The effect of the threshold current reduction method can be sufficiently exhibited.

[0010]

FIG. 1 is a block diagram showing one embodiment of a dynamic RAM to which the present invention is applied. First, an outline of the configuration and operation of the dynamic RAM according to this embodiment will be described with reference to FIG. Although the circuit elements constituting each block in FIG. 1 are not particularly limited, they are formed on a single semiconductor substrate surface such as single crystal silicon by a known MOSFET integrated circuit manufacturing technique.

In FIG. 1, the dynamic RAM of this embodiment includes, but is not limited to, eight memory mats MAT0 to MAT7, each of which is represented by the memory mat MAT0 in FIG. As shown in the figure, a memory array MARY occupying most of the required area of the layout and an X address decoder XD, a word line drive circuit WD, a sense amplifier SA, a sense amplifier drive circuit SD and Y, which are direct peripheral circuits.
And an address decoder YD.

The memory array MARY of the memory mats MAT0 to MAT7 includes a predetermined number of word lines arranged in parallel in the vertical direction in the figure and a predetermined number of complementary bit lines arranged in parallel in the horizontal direction. Include each. At the intersections of these word lines and complementary bit lines, a number of dynamic memory cells each composed of an information storage capacitor and an address selection MOSFET are arranged in a lattice.

The words forming each of the memory arrays MARY of the memory mats MAT0 to MAT7 are coupled to the corresponding word line drive circuits WD below the memory mats MAT0 to MAT7, and each of them is alternatively selected. Memory mats MAT0-M
A word line drive signal of a predetermined bit is supplied from the corresponding X address decoder XD to the word line drive circuit WD of the AT7. A predecode signal of a predetermined bit is commonly supplied from an X predecoder XP to an X address decoder XD of each memory mat, and a timing generation circuit TG
Supplies an internal control signal XDG in common. This X predecoder XP has i +
One-bit internal address signals X0 to Xi are supplied.
Further, X address signals AX0 to AXi are supplied to the X address buffer XB in a time-division manner via address input terminals A0 to Ai, and an internal control signal XL is supplied from the timing generation circuit TG.

The X address buffer XB converts X address signals AX0 to AXi supplied from an external access device via address input terminals A0 to Ai into an internal control signal XL.
And the internal address signals X0 to Xi are formed based on these X address signals and supplied to the X predecoder XP. X predecoder X
P decodes the internal address signals X0 to Xi supplied from the X address buffer XB in combination by predetermined bits, selectively forms a corresponding predecode signal, and selects each X address decoder XD of the memory mats MAT0 to MAT7. To supply. Memory mats MAT0-MAT
7 is provided with an internal control signal XDG.
Is selectively activated in response to the high level, and the predecode signal supplied from the X predecoder XP is combined and decoded, and the corresponding word line drive signal is alternatively set to the valid level. The word line drive circuit WD receives the alternative valid level of these word line drive signals and selectively sets the corresponding word line of the corresponding memory array MARY to a high level selection state.

Next, the complementary bit lines constituting the memory array MARY of the memory mats MAT0 to MAT7 are coupled to the corresponding sense amplifier SA on the left side, and the complementary common data line CD0 * is connected via the sense amplifier SA.
To CD7 * (here, for example, the non-inverted common data line CD0
In addition, the inverted common data line CD0B is indicated by asterisks like a complementary common data line CD0 *. In addition, a so-called inverted signal or the like which is selectively set to a low level when it becomes valid is indicated by adding a B to the end of its name. The same applies hereinafter).

Each of the sense amplifiers SA of the memory mats MAT0 to MAT7 is supplied with a predetermined number of bit line selection signals from a corresponding Y address decoder YD, and receives a common source line CSP (not shown) from a corresponding sense amplifier driving circuit SD. A power supply voltage VCC and a ground potential VSS as the operation power supply are selectively supplied via the CSN. These sense amplifier drive circuits SD are commonly supplied with an internal control signal PA from a timing generation circuit TG. Further, a predecode signal of a predetermined bit is commonly supplied from a Y predecoder YP to a Y address decoder YD of each memory mat, and an internal control signal YDG is commonly supplied from a timing generation circuit TG. The Y predecoder YP is supplied with i + 1-bit internal address signals Y0 to Yi from a Y address buffer YB. The Y address buffer YB has address input terminals A0 to Ai.
Address signals AY0 to AYi are supplied in a time-division manner through the internal control signal YL from the timing generation circuit TG.
Is supplied.

The Y address buffer YB is provided with a Y address signal AY supplied via address input terminals A0 to Ai.
0 to AYi are captured and held in accordance with the internal control signal YL, and the internal address signals Y0 to Yi are formed based on these Y address signals and supplied to the Y predecoder YP. Y predecoder YP decodes internal address signals Y0 to Yi supplied from Y address buffer YB in combination by predetermined bits, selectively forms corresponding predecode signals, and generates memory mats MAT0 to MAT0.
It is supplied to the Y address decoder YD of MAT7. Y address decoder YD of memory mats MAT0-MAT7
Are selectively turned on in response to the high level of the internal control signal YDG, and are decoded by combining the predecode signals supplied from the Y predecoder YP. Is alternatively set to a high-level selection state.

The sense amplifiers SA of the memory mats MAT0 to MAT7 each include a predetermined number of unit circuits provided corresponding to each complementary bit line of the memory array MARY. Each of these unit circuits is a pair of CMOS circuits.
(Complementary MOS) Includes a unit amplifier circuit in which inverters are cross-coupled and a pair of switch MOSFETs. Of these, the unit amplifier circuit of each unit circuit receives the internal control signal P
A is set to a high level to selectively and collectively operate, and a predetermined number of memory cells coupled to a selected word line of the memory array MARY are output via corresponding complementary bit lines. Each of the small read signals is amplified to be a high-level or low-level binary read signal. Also, switch MOSFET of each unit circuit
Are selectively turned on when the corresponding bit of the bit line select signal is set to a high level, and a corresponding set of complementary bit lines and complementary common data lines CD0 * to CD7 * of each memory array MARY are provided. Are selectively connected to each other.

The complementary common data lines CD0 * to CD7 * are
The data input / output circuit IO is coupled to a corresponding unit circuit. Each unit circuit of the data input / output circuit IO includes a write amplifier and a main amplifier (not shown), a data input buffer and a data output buffer, respectively. Among these, the output terminal of the write amplifier and the input terminal of the main amplifier of each unit circuit are connected to the corresponding complementary common data line CD0 *.
To CD7 *. The input terminals of the write amplifier of each unit circuit are respectively coupled to the output terminals of the corresponding data input buffers, and the input terminals of the data input buffer of each unit circuit are respectively coupled to the corresponding data input / output terminals D0 to D7. Is done. Further, the output terminal of the main amplifier of each unit circuit is connected to the input terminal of the corresponding data output buffer, and the output terminal of the data output buffer of each unit circuit is connected to the corresponding data input / output terminals D0 to D7. Is done.

The data input buffers of the unit circuits of the data input / output circuit IO are provided with data input terminals D0 to D0 when the dynamic RAM is selected in the write mode.
The corresponding bit of the write data supplied via the interface 7 is fetched and transmitted to the corresponding write amplifier. These write data are converted into predetermined complementary write signals by write amplifiers of each unit circuit, and then are supplied to memory mats MAT0 to MAT0 via complementary common data lines CD0 * to CD7 *.
The data is written into a total of eight memory cells, one selected from each of the memory arrays MARY of the MAT7.

On the other hand, when the dynamic RAM is selected in the read mode, the main amplifiers of the unit circuits of the data input / output circuit IO are connected to the memory mats MAT0 to MAT0.
Binary read signals output from the selected eight memory cells of MAT7 via complementary common data lines CD0 * to CD7 * are further amplified and transmitted to corresponding data output buffers. These read data are output from the data output buffers of each unit circuit via the data input / output terminals D0 to D7.

The timing generation circuit TG selects various internal control signals based on a row address strobe signal RASB, a column address strobe signal CASB, and a write enable signal WEB supplied as an activation control signal from an external access device. And supply it to each part of the dynamic RAM. Further, the internal voltage generation circuit VG generates predetermined internal voltages VWL and VBB based on the power supply voltage VCC and the ground potential VSS supplied via the external terminals VCC or VSS, and supplies them to the respective parts of the dynamic RAM. I do. Although not particularly limited, the power supply voltage VCC is set to a predetermined positive potential such as + 3.3V. Further, the internal voltage VWL is set to a predetermined negative potential such as −1 V, and as described later, the P
A substrate voltage is supplied to a well region where a channel MOSFET is formed. Further, the internal voltage VBB is set to the same predetermined negative potential, and is supplied as a substrate back bias voltage to a semiconductor substrate serving as a formation base of the dynamic RAM.

In this embodiment, a dynamic RA
M employs a selective combination of two sub-threshold current reduction methods, that is, a switched source method and a well potential control method, according to the characteristics of each block constituting the peripheral circuit. That is, in the dynamic RAM according to the present embodiment, although not particularly limited, as indicated by hatching in FIG. 1, the X address decoder XD, the word line drive circuit WD, the sense amplifier drive circuits SD and Y
A switched source method is employed in the address decoder YD, and as indicated by hatching in the figure, the well potentials in the X address buffer XB, the X predecoder XP, the Y address buffer YB, the Y predecoder YP, and the timing generation circuit TG. A control method is adopted.
As a result, the switched source method or the well potential control method can be selectively adopted for blocks that can be adapted to each of them, and the configuration of a dynamic RAM or the like can be optimized, and the effect of each method can be fully exhibited. . The advantages and disadvantages of the switched source method and the well potential control method will be described later in detail. Note that the timing generation circuit T
As shown in FIG. 3, G may be a block that does not employ any of the switched source method and the well potential control method.

FIG. 2 is a substrate layout diagram of one embodiment of the dynamic RAM of FIG. Based on the figure,
The outline of the substrate layout of the dynamic RAM according to this embodiment will be described. Note that the memory mats MAT0 to MAT0
The following description regarding MAT7 is based on the description of the memory mat MAT0.
Let's take an example. Further, in the following description, the positional relationship shown in FIG.

In FIG. 2, the dynamic RAM is
A so-called LOC (Lead On Chip) package method is adopted, and the bonding pads are formed on the semiconductor substrate CHI.
P is linearly concentrated along the long side direction of P, that is, along the vertical center line. In the vicinity of these bonding pads, an input circuit (input buffer) and an output circuit (output buffer) including an electrostatic protection circuit, an X address buffer XB and a Y address buffer YB including the same, and a timing generation circuit TG are arranged. Is done.

On the left side of the vertical center line of the semiconductor substrate CHIP, the memory mats MAT0, MAT2, MAT4
MAT6 are sequentially arranged, and on the right side thereof, memory mats MAT1, MAT3, MAT5 and MAT are arranged.
7 are arranged.

Here, memory mats MAT0-MAT7
Have a memory array MARY as described above, and the memory array MARY includes a memory mat MA
As exemplified by T0, the memory cell is divided into eight pairs of sub-memory arrays MARYL and MARYR so as to sandwich the X address decoder XD and the word line drive circuit WD. Sense amplifiers SAL and SAR, which are similarly divided, are arranged inside the sub memory arrays MARYL and MARYR,
Further on the inside, divided Y address decoders YDL and YDR are also arranged. A corresponding sense amplifier drive circuit SD is arranged between a pair of sense amplifiers SAL and SAR.

As described above, in this embodiment, a switched source system is employed for the X address decoder XD, the word line drive circuit WD, the sense amplifier drive circuit SD, and the Y address decoder YD, which are shaded in FIG. , X address buffer XB, X predecoder X indicated by oblique lines
The P, Y address buffers YB, Y predecoder YP, and timing generation circuit TG adopt a well potential control method. Note that the timing generation circuit TG may be a block that does not employ any of the switched source method and the well potential control method as shown in FIG.

FIG. 5 is a basic circuit diagram of an embodiment of an address decoder section (first logic circuit) included in the dynamic RAM of FIG. 1, and FIG. 6 is a circuit diagram of the embodiment. A signal waveform diagram is shown. Based on these figures, the X address decoder XD,
Word line drive circuit WD and Y address buffer YB
The basic circuit configuration of the address decoder unit represented by the above and its features will be described. The circuit configuration shown in FIG. 5 shows the basic configuration of the address decoder section of the dynamic RAM of this embodiment, and does not refer to the actual specific configuration or logical configuration of the address decoder section. Absent. In FIG. 5, the MOSFET with an arrow at its channel (back gate) portion is a P-channel type, and an N-channel MOSF without an arrow.
It is distinguished from ET.

In FIG. 5, although not particularly limited, the address decoder section includes four CMOS inverters V1 to V4 connected in series. These inverters V1 to V
Each of the four, as is well known, comprises a pair of P-channel and N-channel MOSFETs whose gates and drains are commonly coupled. The commonly coupled gate of each pair of P-channel and N-channel MOSFETs is the input terminal of each inverter, and the commonly coupled drain is its output terminal.

The input signal of the first inverter V1 constituting the address decoder section is supplied with an internal signal ADI from a preceding circuit (not shown), and the output signal of the last inverter V4 is supplied to a subsequent circuit (not shown) as an internal signal ADO. Is done. Although not particularly limited, when the dynamic RAM and the system including the dynamic RAM are in a standby state, the internal signal ADI is fixed at a low level “L” such as the ground potential VSS. Therefore, the logic level of the output signal of the inverter V1 at the standby time becomes a high level “H” like the power supply voltage VCC, and the logic levels of the output signals of the inverters V2 and V3 at the standby time are the low level “L” and the high level, respectively. It becomes level 'H'. Needless to say, the logic level of the output signal of the inverter V4, that is, the internal signal ADO during standby is low level "L". In other words, the logic levels of the input signals of the inverters V1 and V3 at the time of standby are both low level 'L', and the logic levels of the input signals of the inverters V2 and V4 are both high level 'H'.

In this embodiment, a switched source system is employed for the address decoder section including the X address decoder XD, the word line drive circuit WD and the Y address decoder YD in order to reduce the subthreshold current. That is, when the dynamic RAM and the system including the same are in the standby state, the high potential side power supply terminals of the inverters V1 and V3 whose input signal logic levels are fixed to the low level "L" are connected to the power supply line. Although coupled to SVCC, its lower potential side power supply terminal is coupled to sub-ground potential supply line SVST. In the inverters V2 and V4 in which the logic level of the input signal is fixed to the high level "H", the low-potential-side power supply terminal is coupled to the ground potential supply line SVSS, but the high-potential-side power supply terminal is It is coupled to power supply voltage supply wiring SVCT.

The power supply voltage supply line S of the address decoder section
Between VCC and the sub power supply voltage supply line SVCT, a gate is provided with a switch control signal, that is, an internal control signal CSP.
A P-channel type switch MOSFET P1 is provided between the ground potential supply line SVSS and the sub-ground potential supply line SVST.
N-channel type switch MOSFET N1 receiving N
Is provided. The power supply voltage supply wiring SVCC has
As shown in FIG. 6, the power supply voltage VCC is always supplied irrespective of the operation state of the dynamic RAM, and the ground potential VSS, that is, 0 V is always supplied to the ground potential supply wiring SVSS. On the other hand, when the dynamic RAM is in the standby state, the internal control signal CSP is set to a high level such as the power supply voltage VCC, and the dynamic RA
When M is activated, the ground potential VSS
Is set to a low level. Also, the internal control signal CS
N is set to a high level such as the ground potential VSS when the dynamic RAM is in the standby state, and N is set when the dynamic RAM is in the active state.
It is set to a high level like the power supply voltage VCC.

When the dynamic RAM is activated, the switch MOSFET P1 is turned on in response to the low level of the internal control signal CSP, and the switch MOSFET N1 is turned on in response to the high level of the internal control signal CSN. Accordingly, power supply voltage VCC is supplied to sub power supply voltage supply wiring SVCT via switch MOSFET P1, and ground potential VSS is supplied to sub ground potential supply wiring SVST via switch MOSFET N1.

On the other hand, when the dynamic RAM is in the standby state, the switch MOSFET P1 is turned off in response to the high level of the internal control signal CSP,
The switch MOSFET N1 is turned off in response to the low level of the internal control signal CSN. Therefore, the potential of sub power supply voltage supply line SVCT is
According to the off-resistance ratio between TP1 and the P-channel MOSFETs constituting the inverters V2 and V4, for example, it is set to 3.0 V lower than the power supply voltage VCC by 0.3 V, and the potential of the sub-ground potential supply line SVST is set to the inverter V1.
And 0.3 V higher than the ground potential VSS by 0.3 V in accordance with the off-resistance ratio between the N-channel MOSFET and the switch MOSFET N1 forming V3.

From these facts, in the inverters V1 and V3 of the address decoder unit in which the logic level of the input signal during standby is fixed to the low level "L", the P-channel MOSFET receives the low level of each input signal and turns on. , But N-channel MOSFE
T is in a deep off state due to a reverse bias state between its gate and source, thereby reducing its subthreshold current. On the other hand, in the inverters V2 and V4 of the address decoder unit in which the logic level of the input signal during standby is fixed to the high level “H”,
The N-channel MOSFET is turned on in response to the high level of each input signal, while the P-channel MOSFET is in a deep off state with a reverse bias between its gate and source, thereby reducing its subthreshold current. .

The address decoder section including the X address buffer XB, the word line driving circuit WD, and the Y address decoder YD requires a relatively short recovery time. Is selectively selected, so the number is small. Such characteristics of the address decoder section are compatible with the switched-source method, as described later, so that the configuration of the dynamic RAM can be optimized and the effect of the switched-source method can be fully utilized.

FIG. 7 shows a first example of a random logic section (second logic circuit) included in the dynamic RAM of FIG.
2 is a basic sectional structural view of the embodiment. The basic cross-sectional structure of the random logic section represented by the timing generation circuit TG of the dynamic RAM of this embodiment and its features will be described with reference to FIG. FIG. 7 shows an outline of the basic device structure of the random logic unit, and does not refer to the actual specific device configuration or shape.

In FIG. 7, the dynamic RAM of this embodiment has a P-type semiconductor substrate PSUB as a base body. The P-channel MOSFET (PMOS) constituting the random logic portion has a pair of P-type diffusion layers P ⁺ formed in an N-type well region NWELL on the surface of the semiconductor substrate PSUB as its source and drain, and has an N-channel MOSFET (PMOS). The NMOS has a pair of N-type diffusion layers N ⁺ formed in the P-type well region PWELL on the surface of the semiconductor substrate PSUB as its source and drain. A gate is provided between a pair of P-type diffusion layers P ⁺ or N-type diffusion layers N ^{+ serving} as a source or a drain of the P-channel and N-channel MOSFETs, that is, an upper layer of the channel with an insulating film IL having a predetermined thickness interposed therebetween. The layers FG are respectively formed. A predetermined internal signal for setting the power supply voltage VCC to a high level and the ground potential VSS to a low level is supplied to these gate layers FG, that is, the gates of the MOSFETs. In response to this, each MOSFET is selectively turned on or off. It is said.

In this embodiment, an N-channel MOS
A predetermined internal voltage VWL is supplied to a P-type well region PWELL in which an FET is formed via a corresponding P-type diffusion layer P ⁺ . This internal voltage VWL is
When the AM is in the active state, it is set to the ground potential VSS, that is, 0V, and when the dynamic RAM is in the standby state, it is set to a negative potential such as -1V. As a result, when the dynamic RAM is activated and the internal voltage VWL is set to the ground potential VSS, the N-channel MOSFET constituting the random logic section is in a relatively shallow bias state and can operate at high speed. However, when the dynamic RAM is set to the standby state and the internal voltage VWL is set to a negative potential such as -1 V, a relatively deep reverse bias state is established between the gate and the source, thereby reducing the subthreshold current. It will be.

Although the timing generation circuit TG and the random logic section including the X address buffer XB, the X predecoder XP, the Y address buffer YB and the Y predecoder YP are active at the same time when active, there are many circuits. It is hardly affected by the return time. Such characteristics of the random logic section are compatible with the well potential control method, as described later, so that the configuration of the dynamic RAM can be optimized and the effect of the switched source method can be fully utilized.

The well potential control method has a disadvantage that the return time from the standby state to the active state is relatively long because the parasitic capacitance coupled to the P-type well region PWELL or the like is relatively long. The section is not a serious problem because it is less susceptible to return time. If the recovery time becomes a problem, the well voltage VWL in this portion may be fixed to a potential at which the subthreshold current is reduced. In this case, the operation speed slightly increases.

FIG. 8 is a basic sectional structural view of a second embodiment of the random logic section included in the dynamic RAM of FIG. It should be noted that the random logic section of this embodiment basically follows the embodiment of FIG. 7, and therefore, only the different parts will be described.

In FIG. 8, the dynamic RAM is
So-called SOI (SiliconOn Insulat)
or) a P-channel MOSFET forming a random logic part having a structure, a pair of P-type diffusion layers P ⁺ formed in an N-type well region NWELL on an insulating layer INS as its source and drain,
Is a P-type well region PWELL on the insulating layer INS.
The ⁺ pair of N-type diffusion layer N formed as its source and drain. An internal voltage V that is selectively set to a negative potential during standby is supplied to a P-type well region PWELL where an N-channel MOSFET is formed via a P-type diffusion layer P ^+.
WL is supplied.

As is well known, in the dynamic RAM having the SOI structure, the parasitic capacitance coupled to the P-type well region PWELL and the like becomes relatively small, and the time required to return from the standby state to the active state is correspondingly reduced. . As a result, by employing the SOI structure, it is possible to suppress the disadvantage of the well potential control method that the return time is lengthened, thereby expanding the applicable range.

FIG. 9 shows the dynamic type R of this embodiment.
FIG. 3 is an explanatory diagram for comparing the advantages and disadvantages of two sub-threshold current reduction methods used in AM, that is, a switched source method and a well potential control method. The advantages and disadvantages of the switched source method and the well potential control method will be summarized based on the drawing, and the combination and the characteristics of the dynamic RAM according to the present embodiment will be described.

In FIG. 9, the switched source method is as follows.
As already described with reference to FIGS. 5 and 6, the high-potential-side power supply voltage of a logic gate such as an inverter whose input signal is fixed at the high level during standby is selectively lowered by, for example, about 0.3 V. The sub-threshold current at the time of standby is reduced by selectively increasing the low-potential-side power supply voltage of the logic gate whose signal is fixed at the low level by, for example, about 0.3 V, and the state is changed from the standby state to the active state. Can be short because the parasitic capacitance coupled to the sub power supply voltage supply line and the sub ground potential supply line is small. Further, the potentials of the sub power supply voltage supply line and the sub ground potential supply line are
Since it is set according to the off-resistance ratio between the FET and the P-channel or N-channel MOSFET constituting each logic gate, there is no need to generate a negative potential internal voltage such as -1 V, for example. No circuit installation is required. Further, even if this method is applied to both the P-channel and N-channel MOSFETs, it is not necessary to adopt a triple well structure as in the well potential control method, so that the manufacturing process of the dynamic RAM is simplified.

However, in the switched-source method, the power supply path is divided into a power supply voltage supply line and a ground potential supply line and a sub power supply voltage supply line and a sub-ground potential supply line. On the other hand, if an attempt is made to suppress an increase in the required layout area, on the contrary, the width of the power supply voltage supply wiring and the ground potential supply wiring is reduced, and the wiring resistance is increased.

Next, in the well potential control method, as described with reference to FIG. 7, the substrate voltage supplied to the well region such as the P-channel MOSFET constituting the logic gate is changed to, for example, the ground potential VSS when active. The sub-threshold current at the time of standby is reduced by setting the potential to 0 V and a predetermined negative potential such as -1 V at the time of standby. Becomes longer due to the large parasitic capacitance coupled to the IGBT. Further, since the substrate voltage is set to a negative potential, for example, -1 V, an internal voltage generating circuit for generating the substrate voltage is required, and its supply capability increases in accordance with the parasitic capacitance. Furthermore, when this method is applied to both P-channel and N-channel MOSFETs, it is necessary to separate a well region, and it is necessary to adopt a triple well structure, which has the disadvantage that the manufacturing process of a dynamic RAM is complicated. .

However, in the well potential control method, it is not necessary to perform complicated timing control when switching from the active state to the standby state or from the standby state to the active state, and the sub power supply voltage supply wiring and the sub ground potential supply wiring are not required. There is no need to provide, and this has the advantage that the wiring width of the power supply voltage supply wiring and the ground potential supply wiring is not limited.

As described above, the X address decoder XD and the word line drive circuit W of the dynamic RAM of the present embodiment are used.
In the address decoder section including the D and Y address decoders YD, a switched source system is adopted, and a random logic section including an X address buffer XB, an X predecoder XP, a Y address buffer YB, a Y predecoder YP, and a timing generation circuit TG. Then, a well potential control method is adopted. The advantage of the switched-source method that the recovery time is short is suitable for the characteristics of the address decoder unit that requires a short recovery time, and the disadvantage of the wiring width is that the address decoder has a small number of circuits that are simultaneously operating when active. Saved by the character of the department.
On the other hand, the disadvantage that the recovery time of the well potential control method is long is saved by the characteristics of the random logic portion that does not require a short recovery time, and the advantage that the width of the power supply wiring of the well potential control method does not become thinner is also reduced. It conforms to the characteristics of the random logic unit having a large number of circuits in the operating state.

As described above, the dynamic RAM of this embodiment employs a method of selectively combining the switched source method and the well potential control method according to the characteristics of each block constituting the peripheral circuit. Can be As a result, the configuration of the dynamic RAM or the like can be optimized, and thereby, the effects of the switched source method and the well potential control method can be sufficiently exhibited. The dynamic RAM of this embodiment
Has an internal voltage generation circuit VG, but has an internal voltage VWL.
Is limited to the block to which the well potential control method is applied, so that the supply capacity for the internal voltage VWL can be relatively small.

The operational effects obtained from the above embodiment are as follows. (1) In a dynamic RAM employing a sub-threshold current reduction method, for example, an X address decoder, a word line drive circuit, a Y address decoder, etc. which require a short recovery time but have a small number of circuits which are simultaneously activated. The address decoder section adopts a switched-source method, and is not easily affected by the recovery time and has a large number of circuits that are simultaneously operated. By selectively combining two sub-threshold current reduction methods according to the characteristics of each block constituting a peripheral circuit such as a dynamic RAM by adopting a well potential control method, etc. Method or well potential control method The effect is obtained that the blocks can be selectively adopted.

(2) In a circuit in which the recovery time becomes a problem in the well potential control method, the same effect can be obtained by fixing the well potential to a potential at which the subthreshold current is reduced. (3) According to the above items (1) and (2), it is possible to obtain the effect that the configuration of the dynamic RAM is optimized and the effect of each sub-threshold current reduction method can be sufficiently exhibited. (4) In the above items (1) to (3), the effect that the parasitic capacitance coupled to the well region can be reduced by using an SOI structure for the semiconductor substrate as a formation base of the dynamic RAM or the like. Is obtained. (5) According to the above item (4), an effect is obtained that the recovery time, which is a drawback of the well potential control method, can be shortened, and the applicable range can be expanded.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say, there is. For example, in FIGS. 1 and 3, the dynamic RAM is
Any number of memory mats can be provided, and the bit configuration is also arbitrary. Memory mats MAT0-MAT
The seven memory arrays MARY can include any number of redundant elements. Furthermore, the dynamic RAM does not require the use of the address multiplex system, and its block configuration, the combination of the start control signal, the address signal and the internal control signal, the polarity and the specific potential of the power supply voltage, etc. Various embodiments can be adopted.

In FIG. 2 and FIG.
The AM does not make it mandatory to adopt the LOC package system, and the shape of the semiconductor substrate CHIP, the arrangement order of the memory mats MAT0 to MAT7, the specific arrangement of each part, and the like do not limit the present invention. In FIG. 5, the address decoder unit can include various logic gates, and the logic configuration and the logic level of each signal during standby are not limited to this. 6, a sub power supply voltage supply line SVCT and a sub ground potential supply line SVS
The potential difference between the potential when T is active and the potential during standby can be set arbitrarily. FIG.
8 and FIG. 8, the cross-sectional structure illustrated does not limit the actual specific device structure or shape of each element.

In the above description, the case where the invention made by the present inventor is mainly applied to the dynamic RAM, which is the field of application as the background, has been described.
The present invention is not limited to this, and can be applied to, for example, various memory integrated circuits such as a static RAM, and a logic integrated circuit device such as a single-chip microcomputer. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a semiconductor integrated circuit device including a plurality of blocks having different interests and disadvantages with respect to at least a subthreshold current reduction method, and a device or a system including such a semiconductor integrated circuit device.

[0058]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a dynamic RAM or the like employing a sub-threshold current reduction method, for example, an X address decoder, a word line drive circuit, a Y address decoder, etc. which require a short recovery time but have a small number of circuits which are simultaneously operated are included. The address decoder section employs a switched source method, and is not easily affected by the recovery time and has a large number of circuits that are simultaneously operated. By selectively combining two sub-threshold current reduction methods according to the characteristics of each block constituting a peripheral circuit such as a dynamic RAM by adopting a well potential control method, etc. Method or well potential control method Selectively employed to block that can be adapted, it is possible to optimize the structure of such a dynamic RAM, and sufficiently exhibit the effect of each sub-threshold current reduction scheme.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a dynamic RAM to which the present invention is applied.

FIG. 2 is a board layout diagram showing one embodiment of a dynamic RAM of FIG. 1;

FIG. 3 is a block diagram illustrating a dynamic RAM according to a second embodiment of the present invention;

FIG. 4 is a board layout diagram showing one embodiment of the dynamic RAM of FIG. 3;

FIG. 5 is a partial basic circuit diagram showing one embodiment of an address decoder section included in the dynamic RAM of FIG. 1;

FIG. 6 is a signal waveform diagram illustrating an embodiment of the address decoder unit of FIG. 5;

FIG. 7 is a partial basic sectional structural view showing a first embodiment of a random logic unit included in the dynamic RAM of FIG. 1;

FIG. 8 is a partial basic sectional structural view showing a second embodiment of the random logic section included in the dynamic RAM of FIG. 1;

FIG. 9 is an explanatory diagram for explaining the advantages and disadvantages of the switched source method and the well potential control method adopted in the dynamic RAM of FIG. 1;

[Explanation of symbols]

MAT0 to MAT7: Memory mat, MARY: Memory array, XD: X address decoder, WD: Word line drive circuit, SA: Sense amplifier, SD: Sense amplifier drive circuit, YD: Y address decoder, XP
... X predecoder, XB ... X address buffer, Y
P ... Y predecoder, YB ... Y address buffer,
IO: data input / output circuit, VG: internal voltage generation circuit, TG: timing generation circuit. D0 to D7 ... input or output data or input / output terminals thereof, RASB ...
Row address strobe signal or its input terminal, CAS
B: column address strobe signal or input terminal thereof, WEB: write enable signal or input terminal thereof, A0 to Ai: address signal or input terminal thereof, V
CC: power supply voltage or its input terminal, VSS: ground potential or its input terminal. CHIP: Semiconductor substrate, MAR
YL, MARYR: Sub-memory array, SAL, SA
R: sense amplifier, YDL, YDR: Y address decoder. P1 ... P-channel MOSFET, N1 ...
N-channel MOSFET, V1 to V4 CMOS inverter, SVCC power supply voltage supply wiring, VSSS
… Ground potential supply wiring, SVCT… sub power supply voltage supply wiring, SVST… sub ground potential supply wiring, CSP, CS
N: Internal control signal. PSUB ... P-type semiconductor substrate, P
WELL: P-type well region, NWELL: N-type well region, P ^+: P-type diffusion layer, N ^+: N-type diffusion layer, F
G: gate layer, IL: insulating film, PMOS: P-channel MOSFET, NMOS: N-channel MOS
FET, VWL: internal voltage, INS: insulating layer.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masatoshi Hasegawa 2326 Imai, Ome-shi, Tokyo Inside Device Development Center, Hitachi, Ltd.

Claims (9)

[Claims] 1. A logic gate whose input signal is fixed at a high level during standby is selectively lowered by a predetermined value to a high potential side power supply voltage, and / or a logic gate whose input signal is fixed at a low level. A first logic circuit in which a subthreshold current is reduced by selectively increasing a low-potential-side power supply voltage by a predetermined value, and a potential of a substantial substrate voltage with respect to an N-channel MOSFET during standby is selectively determined And the negative potential of
And / or substantially the same as the second logic circuit in which the sub-threshold current is reduced by selectively setting the substantial substrate voltage potential of the P-channel MOSFET to a positive potential equal to or higher than a predetermined source potential. A semiconductor integrated circuit device provided on a substrate. 2. The semiconductor integrated circuit device according to claim 1, wherein a semiconductor substrate serving as a formation base of the semiconductor integrated circuit device has an SOI structure. 3. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is a dynamic RAM, and the first logic circuit includes an address decoder and a sense amplifier driving circuit of the dynamic RAM. Wherein the second logic circuit includes a timing generation circuit, an address buffer, and an address predecoder. 4. The semiconductor integrated circuit device according to claim 1, wherein the signal amplitude of the first logic circuit is made larger than the signal amplitude of the second logic circuit. . 5. The power supply according to claim 4, wherein the predetermined negative potential and / or positive potential of the second logic circuit is substantially equal to a high potential power supply voltage and / or a low potential power supply voltage of the first logic circuit. A semiconductor integrated circuit device characterized by being equalized. 6. The logic gate whose input signal is fixed at a high level during standby is selectively lowered by a predetermined value, and / or the logic gate whose input signal is fixed at a low level. A first logic circuit in which the sub-threshold current is reduced by selectively increasing the low-potential-side power supply voltage by a predetermined value; and setting the substantial substrate voltage potential of the N-channel MOSFET to a predetermined negative potential, And / or providing a second logic circuit capable of reducing a subthreshold current by setting the substantial substrate voltage potential of the P-channel MOSFET to a positive potential equal to or higher than a predetermined source potential on substantially the same substrate. A semiconductor integrated circuit device comprising: 7. The semiconductor integrated circuit device according to claim 6, wherein the semiconductor integrated circuit device is a dynamic RAM, and the first logic circuit includes an address decoder and a sense amplifier driving circuit of the dynamic RAM. A semiconductor integrated circuit device, wherein the second logic circuit includes a timing generation circuit, an address buffer, and an address predecoder. 8. The semiconductor integrated circuit device according to claim 6, wherein the signal amplitude of the first logic circuit is made larger than the signal amplitude of the second logic circuit. 9. The method according to claim 8, wherein the predetermined negative potential and / or positive potential of the second logic circuit is substantially equal to a high potential power supply voltage and / or a low potential power supply voltage of the first logic circuit. A semiconductor integrated circuit device characterized by being equalized.