JPH11265577A - Semiconductor storage device - Google Patents

Abstract

(57) [Summary] To increase the speed of a dynamic RAM or the like including a sense amplifier. SOLUTION: In a large-capacity dynamic RAM or the like whose operating power supply is reduced in voltage, each complementary bit line BL
In addition to the normal unit sense amplifier UA provided in the sense amplifier SA corresponding to 0 * to BLn *, a predetermined size in the memory array ARYL has the same size as the address selection MOSFET Qa constituting the dynamic memory cell. And one or a plurality of auxiliary unit sense amplifiers AA formed by cross-connecting N-channel MOSFETs ND and NE and NF and NG formed at a low pitch and having a low pitch. In addition, these MO
In order to lower the threshold voltage of the SFET, the memory array and the MOSFETs directly around the memory array are all provided with a low threshold voltage by adopting an SOI structure or a negative word line method in which the non-selection level of the word line is set to a negative potential. Voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, a dynamic RAM (random access memory) having a sense amplifier and a low operating power supply, and is particularly effective when used for high speed operation. It is about technology.

[0002]

2. Description of the Related Art A memory array including a word line and a complementary bit line arranged orthogonally, and a dynamic memory cell arranged at the intersection of the word line and the complementary bit line, and a memory array corresponding to each complementary bit line. There is a semiconductor memory device such as a dynamic RAM including a sense amplifier including a unit sense amplifier provided in a memory. In recent years, the progress of technology for miniaturization and high integration of semiconductor integrated circuits has been remarkable,
Dynamic RAMs and the like are also becoming more highly integrated and larger in capacity. In order to reduce the power consumption of such a dynamic RAM or the like and prevent breakdown voltage breakdown of miniaturized elements, the operating power supply tends to be lower in voltage, and the memory array and its immediate peripheral parts The operating power supply has now been reduced to a voltage of, for example, about 1.5 V (volt).

[0003]

Prior to the present invention, the present inventors have attempted to develop a large-capacity dynamic RAM in which the operating power supply voltage is reduced, and have noticed the following problems. That is, this dynamic RAM is
As shown in FIGS. 13 and 14, a so-called shared sense method is employed, and the sense amplifier SA is provided inside a pair of memory arrays ARYL and ARYR. The sense amplifiers SA include complementary bit lines BL0 * -BLn * and BR0 * -B of the memory arrays ARYL and ARYR.
Rn * (Here, for example, the non-inverted bit BL0T and the inverted bit line BL0B are indicated by asterisks like a complementary bit line BL0 *. When they are enabled, they are selectively set to a high level. For example, a so-called non-inverted signal line or the like is indicated by adding a T to the end of its name, and a so-called inverted signal or the like that is selectively set to a low level when it is enabled is indicated by a B at the end of its name. And n + 1 unit circuits centered on a unit sense amplifier UA in which a pair of CMOS (complementary MOS) inverters are cross-coupled.

Each unit sense amplifier U of the sense amplifier SA
A is a P-channel drive MOSFET (metal oxide semiconductor field effect transistor; in this specification, MO
An internal voltage VDL is supplied from P1 via a common source line CSP, and an N-channel drive MOSF
Ground potential V from ETN1 via common source line CSN
When SS is supplied, the operating state is selectively and simultaneously performed, and the corresponding complementary bit lines BL0 * to BLn * or BR0 * to n + 1 memory cells coupled to the selected word line of the memory array ARYL or ARYR. BRn
*, And amplifies the small read signals output via the *, setting the internal voltage VDL to its high level and setting the ground potential V
Let SS be a binary read signal with its low level.

However, in a dynamic RAM or the like in which the operating power supply voltage has been reduced, the voltage between the drain and source of the pull-down N-channel MOSFETs N2 and N3 constituting each unit sense amplifier UA of the sense amplifier SA becomes small. However, there has been a problem that the amplifying operation is slowed and the speeding up of a dynamic RAM or the like is restricted. To deal with this, the common source line C
A so-called overdrive method in which the potential of the high-potential-side operation power supply supplied via the SP is temporarily higher than the final high level of the binary read signal has also been proposed. High speed has not been secured.

An object of the present invention is to provide a dynamic RAM
And to speed up the operation.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0008]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in a large-capacity dynamic RAM or the like whose operating power supply is reduced in voltage, a predetermined position in a memory array is provided separately from a normal unit sense amplifier provided in a sense amplifier corresponding to each complementary bit line. Auxiliary unit sense amplifiers, each having a cross-coupled low threshold voltage N-channel MOSFET formed at the same size and pitch as the address selection MOSFET constituting the dynamic memory cell, are provided for each complementary bit line.
Or a plurality of these auxiliary unit sense amplifiers,
For example, the operating state is set prior to the normal unit sense amplifier of the sense amplifier. In order to lower the threshold voltage of these MOSFETs, a so-called SOI structure in which a semiconductor layer is formed on a predetermined insulating film, or a negative word line method in which a non-selection level of a word line is set to a negative potential is adopted. As a result, the threshold voltage of the memory array and the MOSFETs directly in the peripheral portion are lowered as a whole.

According to the above-mentioned means, the operation of amplifying the read signal by each unit sense amplifier of the sense amplifier can be accelerated while suppressing an increase in the required area of the layout of the memory array, and the speed of a dynamic RAM or the like can be increased. At the same time, it is possible to promote lowering of the operating power supply voltage, lower power consumption, suppress increase in chip temperature, and improve pause refresh characteristics of dynamic RAMs and the like.

[0010]

FIG. 1 is a block diagram showing one embodiment of a dynamic RAM (semiconductor memory device) to which the present invention is applied. First, an outline of the configuration and operation of the dynamic RAM according to this embodiment will be described with reference to FIG. The circuit elements constituting each block in FIG. 1 are formed on a single semiconductor substrate surface such as single crystal silicon by a known MOSFET integrated circuit manufacturing technique.

In FIG. 1, the dynamic RAM of this embodiment includes, but is not limited to, eight memory mats MAT0 to MAT7. Dynamic type R
AM adopts a shared sense system and uses a memory mat MAT.
0 to MAT7, as represented by the memory mat MAT0, a pair of memory arrays ARYL and ARYR sandwiching the sense amplifier SA, and a pair of X address decoders XDL provided corresponding to each memory array.
And XDR. Memory mats MAT0-MAT
7 further includes a Y address decoder YD provided commonly to both memory arrays, a write amplifier WA and a main amplifier MA.

The memory arrays ARYL and ARYR of the memory mats MAT0 to MAT7 have a predetermined number of word lines arranged in parallel in the vertical direction and a predetermined number of complementary bit lines arranged in parallel in the horizontal direction. And respectively.
At the intersections of these word lines and complementary bit lines, a large number of dynamic memory cells composed of information storage capacitors and address selection MOSFETs are arranged in a lattice. In this embodiment, the memory arrays ARYL and ARYL are used.
YR includes auxiliary unit sense amplifiers provided four each corresponding to each complementary bit line and operating at the same time as a unit sense amplifier of a sense amplifier SA described later. The specific configuration and operation will be described later in detail.

The word lines forming the memory arrays ARYL and ARYR of the memory mats MAT0 to MAT7 are coupled to corresponding X address decoders XDL or XDR below them, and each of them is alternatively selected. To the X address decoders XDL and XDR of the memory mats MAT0 to MAT7, the i + 1-bit internal address signals X0 to Xi are commonly supplied from the X address buffer XB, and the internal control signal XG (not shown) is commonly supplied from the timing generation circuit TG. Supplied to Also,
The X address buffer XB receives an X address signal A from an external access device through address input terminals A0 to Ai.
X0 to AXi are supplied in a time-division manner, and an internal control signal XL is supplied from the timing generation circuit TG.

An X address buffer XB is provided with an X address signal AX supplied through address input terminals A0 to Ai.
0 to AXi are taken in according to the internal control signal XL, held, and based on these X address signals, internal address signals X0 to Xi are formed to generate a memory mat MAT.
0 to MAT7 to the X address decoders XDL and XDR. In addition, X of the memory mats MAT0 to MAT7
The address decoders XDL and XDR output internal control signals X
When G is set to the high level and, for example, the internal address signal Xi of the most significant bit is set to the low level or the high level, each of them selectively operates, and decodes the internal address signals X0 to Xi supplied from the X address buffer XB. Then, the designated word line of the memory array ARYL or ARYR is alternatively set to a selected level such as the internal voltage VPP.

Next, the complementary bit lines constituting the memory arrays ARYL and ARYR of the memory mats MAT0 to MAT7 are respectively connected to corresponding unit circuits of the sense amplifier SA inside. The sense amplifier SA is supplied with n + 1-bit bit line selection signals YS0 to YSn (not shown) from the Y address decoder YD, and shared control signals SHL and SHR, a precharge control signal PC and a sense amplifier drive from the timing generation circuit TG. Signals PA and PAB are provided. The Y address decoder YD is supplied with i + 1-bit internal address signals Y0 to Yi from a Y address buffer YB, and an internal control signal YG (not shown) from a timing generation circuit TG. Y address buffer YB
Have address input terminals A0 to A0 from an external access device.
I + 1-bit Y address signals AY0 to AY0 through Ai
Yi is supplied in a time-division manner, and an internal control signal YL is supplied from a timing generation circuit TG.

A Y address buffer YB is provided with a Y address signal AY supplied via address input terminals A0 to Ai.
0 to AYi in accordance with the internal control signal YL and hold the same, and form the internal address signals Y0 to Yi based on these Y address signals to obtain the memory mat MAT.
0 to MAT7 to the Y address decoder YD. The Y address decoders YD of the memory mats MAT0 to MAT7 are selectively activated in response to the high level of the internal control signal YG, decode the internal address signals Y0 to Yi, and provide a bit line selection signal to the sense amplifier SA. The corresponding bits YS0 to YSn are alternatively set to the high level.

Each of the sense amplifiers SA of the memory mats MAT0 to MAT7 includes a predetermined number of unit circuits provided corresponding to respective complementary bit lines of the memory arrays ARYL and ARYR, and each of these unit circuits is not particularly limited. A unit sense amplifier in which a pair of CMOS inverters are cross-coupled, a bit line precharge circuit in which three N-channel type precharge MOSFETs are connected in series and parallel, and a pair of N-channel type switches M
OSFET. A complementary input / output node of each unit circuit of the sense amplifier has an N-channel type shared MOS on its left side which receives a shared control signal SHL in common.
Other shared MOSFs respectively coupled to corresponding complementary bit lines of memory array ARYL via FETs and receiving, on the right side, shared control signal SHR in common.
Each is coupled to a corresponding complementary bit line of the memory array ARYR via ET.

The shared control signals SHL and SHR
As described later, when the dynamic RAM is set to the non-selected state, it is set to a predetermined high level. When the dynamic RAM is set to the selected state, one of them is set according to, for example, the internal address signal Xi of the most significant bit. One of them is selectively set to a predetermined low level. Thereby, the complementary input / output node of each unit circuit of the sense amplifier SA is connected to the non-selected state of the dynamic RAM.
Both are connected to the corresponding complementary bit lines of the memory arrays ARYL and ARYR via the corresponding shared MOSFETs, respectively. When the dynamic RAM is selected, only one of them is selectively selected according to the internal address signal Xi. Connected.

A precharge MOSFET constituting a bit line precharge circuit of each unit circuit of the sense amplifier SA
When the dynamic RAM is set to the non-selection state, it receives the high level of the precharge control signal PC and is selectively and simultaneously turned on, and the non-inverting and inverting input / output nodes of the corresponding unit circuit, that is, the memory array The non-inverted and inverted signal lines of the complementary bit lines of ARYL and ARYR are precharged to the intermediate voltage HV between the internal voltage VDL and the ground potential VSS.

On the other hand, the unit sense amplifier of each unit circuit of the sense amplifier SA receives the high level of the sense amplifier drive signal PA and the low level of the sense amplifier drive signal PAB, and is selectively and simultaneously operated, and the memory array is turned on. A small read signal output from a predetermined number of memory cells coupled to a selected word line of ARYL or ARYR via a corresponding complementary bit line is amplified, the internal voltage VDL is set to the high level, and the ground potential VSS is set. Is a low-level binary read signal. The switch MOSFET of each unit circuit is provided with bit line selection signals YS0 to YSn supplied from the Y address decoder YD.
Of the unit amplifiers corresponding to the sense amplifiers SA, and selectively connects the complementary input / output nodes of the corresponding unit sense amplifiers of the sense amplifiers SA and the complementary common data lines CD *.

The complementary common data lines CD * of the memory mats MAT0 to MAT7 are commonly connected to the output terminal of the corresponding write amplifier WA and the input terminal of the main amplifier MA, respectively. The input terminal of the write amplifier WA of each memory mat is coupled to the output terminal of the corresponding unit circuit of the data input buffer IB via the corresponding bit of the write data bus WDB0-WDB7, and the output terminal of the main amplifier MA of each memory mat. The terminal is connected to the read data bus RDB0.
RDB7 to the input terminal of the corresponding unit circuit of the data output buffer OB via the corresponding bit. An input terminal of each unit circuit of the data input buffer IB and an output terminal of each unit circuit of the data output buffer OB are commonly coupled to corresponding data input / output terminals D0 to D7, respectively. An internal control signal WP (not shown) is commonly supplied from a timing generation circuit TG to the write amplifiers WA of the memory mats MAT0 to MAT7, and an internal control signal OC is commonly supplied to each unit circuit of the data output buffer OB. .

Each unit circuit of the data input buffer IB includes:
When the dynamic RAM is set to the selected state in the write mode, 8-bit write data input through the data input / output terminals D0 to D7 is fetched and held, and the corresponding data is written via the write data buses WDB0 to WDB7. The signal is transmitted to the write amplifiers WA of the memory mats MAT0 to MAT7. At this time, the write amplifier WA of each memory mat is selectively activated in response to the high level of the internal control signal WP, and the write data buses WDB0 to WDB0 to WDB0 to WDB0 to
After the write data transmitted via DB7 is converted into a predetermined complementary write signal, the corresponding memory array ARYL is supplied from complementary common data line CD * via sense amplifier SA.
Alternatively, data is written into a selected one of ARYR, that is, a total of eight memory cells.

On the other hand, when the dynamic RAM is set to the read mode, the memory mats MAT0 to MAT7 supply complementary common data from a selected one of the memory arrays ARYL or ARYR, that is, a total of eight memory cells. The binary read signal output via the line CD * is further amplified and read data buses RDB0 to RDB0
The data is transmitted to the corresponding unit circuit of the data output buffer OB via the RDB 7. At this time, the data output buffer OB
Are selectively operated in response to the high level of the internal control signal OC, and the corresponding main amplifier MA
Read signals transmitted from the data input / output terminals D0 to D0
Output via D7.

The timing generation circuit TG generates various internal control signals and the like based on a row address strobe signal RASB, a column address strobe signal CASB, and a write enable signal WEB supplied as an activation control signal from an external access device. It is selectively formed and supplied to each part of the dynamic RAM.

Although not shown in FIG. 1, the dynamic RAM has predetermined internal voltages VPP and VDL and an intermediate voltage based on a power supply voltage VCC and a ground potential VSS supplied through predetermined external terminals. An internal voltage generation circuit for generating voltage HV is provided. Of these, the internal voltage VPP
Is mainly used as a selection level of a word line constituting the memory arrays ARYL and ARYR, and the internal voltage VDL
Are mainly used as an operating power supply for the memory arrays ARYL and ARYR and their direct peripheral circuits. Although not particularly limited, the power supply voltage VCC is a positive potential such as 2.5 V, for example. The internal voltage VPP is, for example, 4.
0 V, and the internal voltage VDL and the intermediate voltage HV are 1.5 V and 0.75 V, respectively.

FIG. 2 is a partial block diagram of the first embodiment of the memory arrays ARYL and ARYR and the sense amplifier SA included in the memory mats MAT0 to MAT7 of the dynamic RAM of FIG. FIG. 3 is a partial circuit diagram of an embodiment of the memory mat ARYL and the sense amplifier SA of FIG.
2 shows a signal waveform diagram of one embodiment. With reference to these drawings, the specific configuration and operation of the memory arrays ARYL and ARYR of the dynamic RAM and the sense amplifier SA and their characteristics will be described.

The following description is based on one sense amplifier SA and one memory array ARY provided on the left side thereof.
L, the memory array ARYR has a symmetric configuration with the memory array ARYL, and the memory arrays ARYL and ARYR and the sense amplifier S of the same configuration have the same configuration.
Needless to say, A is included in each of the memory mats MAT0 to MAT7 and operates similarly.
In the following signal waveform diagram, the case where the word line WL0 of the memory array ARYL on the left side of the sense amplifier SA is in a selected state is illustrated, which is arranged at the intersection of the word line WL0 and the complementary bit line BL0 * and has a logic “ The description of the operation will proceed with a focus on the memory cell holding the data “1”.
In the following circuit diagram, the channel (back gate)
MOSFETs with an arrow in the part are P-channel (second
Conductivity type) and is distinguished from an N-channel (first conductivity type) MOSFET without an arrow.

In FIG. 2, the memory array ARYL is
M + 1 word lines WL0 to WLm arranged in parallel
(WL8j-1) and (n + 1) sets of complementary bit lines BL0 * -BL arranged orthogonally and in parallel to these word lines.
Ln *. At the intersections of these word lines and complementary bit lines, as shown in FIG. 3, an information storage capacitor Cs and an N-channel type address selection MO are respectively provided.
(M + 1) × (n + 1) dynamic memory cells composed of SFETs Qa are arranged in a lattice. One electrode of the information storage capacitor Cs of the (m + 1) memory cells arranged in the same column of the memory array ARYL is connected to the complementary bit line BL0 via the corresponding address selection MOSFET Qa.
* To BLn * are alternately coupled to non-inverted or inverted signal lines with a predetermined regularity. In addition, the memory array ARYL
Of the address selection MOSFET Qa of the (n + 1) memory cells arranged on the same row
Commonly coupled to L0 to WLm. The intermediate voltage HV of 0.75 V is commonly supplied as a plate voltage to the other electrodes of the information storage capacitors Cs of all the memory cells constituting the memory array ARYL.

In this embodiment, the memory array ARY
L further includes a total of 4 × (n + 1) auxiliary unit sense amplifiers AA provided four by four corresponding to the complementary bit lines BL0 * to BLn *. On the left and right sides of these auxiliary unit sense amplifiers AA, a total of 2 × j word lines, that is, word lines WD0 to WD2j-1, WD2j to WD4j-
1, WD4j to WD6j-1 and WD6j to WD8
j-1 (WLm) are arranged. The four auxiliary unit sense amplifiers AA arranged in each column of the memory array ARYL are connected to the corresponding complementary bit lines BL from the N-channel drive MOSFET N1 of the sense amplifier SA.
A ground potential VSS serving as a low-potential-side operation power supply is selectively supplied via a common source line CSN (first common source line) extending between non-inverted and inverted signal lines of 0 * to BLn *. You.

Here, each of the auxiliary unit sense amplifiers AA of the memory array ARYL has a common source line CSN and complementary bit lines BL0 * to BL0 as illustrated in FIG.
Ln * are provided between the non-inverted and inverted signal lines, respectively.
So-called low threshold voltage N-channel MOSFETs ND and NE and N
F and NG (second MOSFET). Note that the MOSFETs ND and NE and NF and NG constituting the auxiliary unit sense amplifier AA are partially modified from those formed as address selection MOSFETs of the dynamic memory cell. It is the same as the MOSFET.

MO constituting auxiliary unit sense amplifier AA
The gates of SFETs ND and NE and NF and NG are connected to the corresponding complementary bit lines BL
0 * to BLn * are respectively coupled to the inverted and non-inverted signal lines and cross-coupled to each other. As described later, the non-inverted and inverted signal lines of the complementary bit lines BL0 * to BLn *
When the dynamic RAM is set to the non-selected state, it is precharged to the intermediate voltage HV. At the time when the selected word line of the memory array ARYL is alternatively set to the selected level, a minute read signal according to the data held in the (n + 1) memory cells coupled to the selected word line is supplied to each complementary bit line. Are output, and when these minute read signals are obtained, the ground potential V is applied to the common source line CSN.
The drive MOSFET N1 for supplying SS is turned on.

Thus, the MOSFETs ND and NE and NF and N which constitute the auxiliary unit sense amplifier AA
G is selectively activated at the same time as the unit sense amplifier UA of the sense amplifier SA when the ground potential VSS is supplied to the common source line CSN, and assists the amplifying operation of the corresponding unit sense amplifier UA. As a result, the amplification operation of each unit sense amplifier UA is accelerated, and the operation of the dynamic RAM is accelerated. This will be described later in detail.

Next, the sense amplifiers SA are connected to the complementary bit lines BL0 * to BLn of the memory arrays ARYL and ARYR.
* And n provided corresponding to BR0 * to BRn *
As shown in FIG. 3, these unit circuits include a P-channel MOSFET P2 (third unit circuit).
MOSFET) and N-channel MOSFET N2
(First MOSFET) and P-channel MOSF
ETP3 (third MOSFET) and N-channel MO
A pair of Cs composed of SFET N3 (first MOSFET)
The basic configuration is a unit sense amplifier UA in which MOS inverters are cross-coupled. Each unit circuit of the sense amplifier SA further includes three N-channel precharge M
A bit line precharge circuit in which OSFETs N6 to N8 are connected in series / parallel, a pair of N-channel type switch MOSFETs N9 and NA, and corresponding complementary bit lines BL0 * to BLn * of the memory arrays ARYL and ARYR.
And N-channel type shared MOSFETs N4 and N5 provided between BR0 * and BRn *, respectively.
And NB and NC, respectively.

Precharge MOSFET constituting bit line precharge circuit of each unit circuit of sense amplifier SA
The precharge control signal PC is commonly supplied from the timing generation circuit TG to the gates of N6 to N8, and the intermediate voltage HV is supplied to the commonly coupled sources of the precharge MOSFETs N6 and N7. The sources of the P-channel MOSFETs P2 and P3 constituting each unit sense amplifier UA are commonly coupled to a common source line CSP (second common source line), and are connected to an N-channel MOSFET.
The sources of TN2 and N3 are commonly coupled to a common source line CSN (first common source line). The common source line CSP has a sense amplifier drive signal PAB at its gate.
The common source line CSN is coupled to an internal voltage VDL (high-potential-side operation power supply) via a P-channel type drive MOSFET P1 receiving the sense amplifier drive signal PA at its gate.
1 is coupled to a ground potential VSS (low-potential-side operation power supply).

Further, the other one of the switch MOSFETs N9 and NA of each unit circuit of the sense amplifier SA is commonly connected to a non-inverted or inverted signal line of the complementary common data line CD *, and the common-coupled gate has a Y gate. The corresponding bit line selection signals YS0 to YS from the address decoder YD
Sn is supplied. The shared control signal SHL is commonly supplied from the timing generation circuit TG to the gates of the shared MOSFETs N4 and N5 of each unit circuit, and the shared control signal SHR is commonly supplied to the gates of the shared MOSFETs NB and NC.

Here, as shown in FIG. 4, the precharge control signal PC has a normal, that is, a dynamic RAM,
Are set to a high level such as the power supply voltage VCC when in the non-selected state, and are set to a low level such as the ground potential VSS at a predetermined timing when the dynamic RAM is set to the selected state. In addition, shared control signals SHL and SH
R is normally set to a high level like the power supply voltage VCC,
When the dynamic RAM is set to the selected state, one of them, that is, for example, the shared control signal SHR is set to a low level such as the ground potential VSS according to the internal address signal Xi of the most significant bit. The remaining one, that is, the shared control signal SHL is set to the internal voltage VPP when the amplification operation of the sense amplifier SA is completed, and
When AM is deselected, it is returned to a high level such as the power supply voltage VCC.

On the other hand, word lines WL0 to WLm and W
Normally, R0 to WRm are all set to a non-selection level such as the ground potential VSS, and when the dynamic RAM is set to the selected state, it is selectively set to the selection level such as the internal voltage VPP according to the internal address signals X0 to Xi. You. The sense amplifier drive signals PA and PAB are normally set to a low level such as the ground potential VSS and a high level such as the power supply voltage VCC, respectively, and are coupled to the selected word line WL0 and the like when the dynamic RAM is selected. N +
At the time when the minute read signal of one memory cell is output to the corresponding complementary bit lines BL0 * to BLn *, a high level such as the power supply voltage VCC and the ground potential VSS are respectively provided.
Is set to a low level.

When the dynamic RAM is deselected and the shared control signals SHL and SHR are at a high level such as the power supply voltage VCC, in the sense amplifier SA, the shared MOSFETs N4 and N5 and NB and NC of all unit circuits are It turns on. At this time, the precharge control signal PC is set to a high level such as the power supply voltage VCC, and in response thereto, the precharge MOSFETs N6 to N6 constituting the bit line precharge circuit of each unit circuit.
N8 is simultaneously turned on.

Thus, the non-inverted and inverted input / output nodes of the complementary input / output nodes S0 * to Sn * of each unit circuit of the sense amplifier SA, the complementary bit lines BL0 * to BLn * and BR0 * to the memory arrays ARYL and ARYR. BR
The n * non-inverted and inverted signal lines are all precharged to an intermediate voltage HV, such as 0.75V. In response to the low level of the sense amplifier drive signal PA and the high level of the sense amplifier drive signal PAB, the drive MOSFET
N1 and P1 are turned off, and the common source line CSP
And CSN are precharged to an intermediate voltage HV via a common source line precharge circuit (not shown). As a result, each unit sense amplifier UA of the sense amplifier SA and each auxiliary unit sense amplifier AA of the memory arrays ARYL and ARYR are all brought into a non-operation state.

When the dynamic RAM is selected, first, the precharge control signal PC is set to a low level such as the ground potential VSS at a predetermined timing, and the precharge control signal PC is precharged by the bit line precharge circuit of each unit circuit of the sense amplifier SA. The charging operation is stopped. Subsequently, for example, the unselected memory array AR not including the designated word line WL0
Shared control signal SHR corresponding to YR is at ground potential VS
S, the shared MOSFETs NB and NC of each unit circuit of the sense amplifier SA are simultaneously turned off, and the complementary input / output nodes S0 * to Sn * and the complementary bit lines BR0 * to BRn of the memory array ARYR are turned off. *
The connection to is broken.

In the memory array ARYL, when the decoding operation of the X address decoder XDL is completed, the word line WL0 designated by the internal address signals X0 to Xi
Is alternatively set to a selection level such as the internal voltage VPP,
All other word lines WL1 to WLm are kept at a non-selected level such as the ground potential VSS. Thereby, the complementary bit lines BL0 * to BLn * of the memory array ARYL, that is, the complementary input / output nodes S0 * to S0 of the sense amplifier SA are
As n *, a minute read signal corresponding to data held in n + 1 memory cells coupled to the selected word line WL0 is output. As a result, for example, a complementary bit line B to which a memory cell holding data of logic "1" is coupled.
The potential of the non-inverted signal line BL0T of L0 *, that is, the non-inverted input / output node S0T of the complementary input / output node S0 * slightly increases, and becomes slightly higher than the potential of the corresponding inverted signal line BL0B, ie, the inverted input / output node S0B.

When the operation of selecting word line WL0 is completed, for example, complementary bit lines BL0 * to BL0 of memory array ARYL
n *, that is, the complementary input / output node S0 * of the sense amplifier SA
When the minute read signal of the (n + 1) memory cells coupled to the selected word line WL0 is output to .about.Sn *, the sense amplifier drive signal PA is set to a high level like the power supply voltage VCC at a predetermined timing, and , The sense amplifier drive signal PAB is set to a low level such as the ground potential VSS.

In the sense amplifier SA, the drive MOSFET N1 is turned on in response to the high level of the sense amplifier drive signal PA, and a low-potential-side operation power supply, that is, the ground potential VSS is supplied to the common source line CSN. Drive MO in response to low level of PAB
SFETP1 is turned on, and the common source line CSP
Is supplied with a high-potential-side operation power supply, that is, an internal voltage VDL. As a result, in the sense amplifier SA, the MOSFETs P2 and P3 and N
2 and N3, the MOSFETs ND and NE, and NF and N, which constitute each auxiliary unit sense amplifier AA, also in the memory array ARYL.
The amplification operation by G is started. As a result, for example, the potential of the non-inverting input / output node S0T rapidly increases toward the internal voltage VDL, and the potential of the inverting input / output node S0B rapidly decreases toward the ground potential VSS.

As described above, in the dynamic RAM in which the operating power supply is lowered, the voltage between the drain and the source of the N-channel MOSFETs N2 and N3 of the unit sense amplifier UA, particularly on the pull-down side, is reduced as the voltage is lowered. And the amplification operation becomes slow. As in this embodiment, the complementary bit lines BL0 * to BLn * and BR0 * to BR of the memory arrays ARYL and ARYR are used.
n * and N-channel MOSFETs ND and N
E and four auxiliary unit sense amplifiers AA including NF and NG are provided, respectively, so that the amplification operation of each unit sense amplifier UA of the sense amplifier SA is accelerated, whereby the operation of the dynamic RAM is accelerated. Will be. As a result, while speeding up the dynamic RAM, it is possible to sufficiently lower the operating power supply to suppress a rise in the chip temperature, thereby greatly improving the refresh characteristics of the dynamic RAM.

The MOSFETs ND and NE and NF and NG which constitute the auxiliary unit sense amplifier AA are:
As described above, a part formed as an address selection MOSFET of a dynamic memory cell is partially modified, and its size and layout pitch are made the same as a normal address selection MOSFET. Therefore, the memory array AR provided by these MOSFETs
The increase in the required area of the YL and ARYR layouts is small enough to cause no problem, and the effect on the chip size of the dynamic RAM is small.

FIG. 5 shows a memory array ARYL and a second sense amplifier SA constituting memory mats MAT0 to MAT7 of a dynamic RAM to which the present invention is applied.
FIG. 6 is a block diagram of the embodiment, and FIG. 6 is a signal waveform diagram of the embodiment. In this example,
Since the embodiment basically follows the embodiment shown in FIGS. 1 to 4, only different parts will be described.

In FIG. 5, the memory array ARYL constituting the memory mats MAT0 to MAT7 of the dynamic RAM of this embodiment is connected to the complementary bit lines BL0 * to BLn *, similarly to the embodiment of FIGS. Correspondingly, a total of 4 × (n + 1) auxiliary unit sense amplifiers AA provided four by four are included. The (n + 1) auxiliary unit sense amplifiers AA arranged in each row of the memory array ARYL include:
A ground potential VSS as a low-potential-side operation power supply is selectively supplied to an N-channel type drive MOSFET NH receiving the sense amplifier drive signal PAA and a corresponding common source line CSNA (third common source line) at its gate. Is done.

In this embodiment, the sense amplifier drive signal PAA is supplied to the memory array A as shown in FIG.
At the time when the minute read signal according to the data held in the (n + 1) memory cells coupled to the selected word line WL0 of RYL is output to the corresponding complementary bit lines BL0 * to BLn *, the sense amplifier drive signal for the sense amplifier SA P
Prior to A, it is set to a high level like the power supply voltage VCC. For this reason, M constituting the auxiliary unit sense amplifier AA
OSFETs ND and NE and NF and NG are MOs constituting each unit sense amplifier UA of the sense amplifier SA.
The amplifying operation is started prior to the SFETs N2 and N3, and the potential between the non-inverting and inverting signal lines of the corresponding complementary bit lines BL0 * to BLn * is slightly lowered while the potential between both signal lines, that is, the signal amount of the minute read signal is reduced. Expanding.
As a result, each unit sense amplifier UA of the sense amplifier SA
The speed of the amplifying operation is further increased, and the same operation and effect as the embodiment of FIGS. 1 to 4 can be obtained.

FIG. 7 shows a memory array ARYL and a third sense amplifier SA constituting memory mats MAT0 to MAT7 of a dynamic RAM to which the present invention is applied.
FIG. 8 is a partial circuit diagram of the embodiment, and FIG. 8 is a sectional structural view of an embodiment of the auxiliary unit sense amplifier AA constituting the memory array ARYL of FIG. This embodiment basically follows the embodiment shown in FIGS. 1 to 4 and, therefore, a description will be added only for portions different from this.

In FIG. 7, the memory array ARYL constituting the memory mats MAT0 to MAT7 of the dynamic RAM of this embodiment is connected to the complementary bit lines BL0 * to BLn *, as in the embodiments of FIGS. Correspondingly, a total of 4 × (n + 1) auxiliary unit sense amplifiers AA are provided, and each of these auxiliary unit sense amplifiers AA receives ground potential VSS on its channel, that is, the back gate portion, and crosses each other. A pair of N-channel MOSFETs NI and NJ or NK to be coupled
And NL. MOs constituting four auxiliary unit sense amplifiers AA arranged in each column of the memory array ARYL
The ground potential VSS is selectively supplied from the drive MOSFET N1 to the commonly coupled sources of the SFETs NI and NJ and NK and NL via the corresponding common source line CSN.

In this embodiment, the dynamic RA
M is a so-called SOI (Silicon On Ins)
MOSFET NI which constitutes each auxiliary unit sense amplifier AA of the memory array ARYL.
, NJ and NK and NL are the MOSFETs of FIG.
As represented by NI and NJ, an SOI substrate formed by forming an insulating film such as a silicon oxide film SiO ₂ on a silicon chip is used as a base for forming the SOI substrate. On the SOI substrate surface, for example, three N-type diffusion layers N ^{+ serving} as sources and drains of MOSFETs NI and NJ, and two gate layers FG serving as gates thereof are formed.
Two P-type diffusion layers P ⁺ coupled to the P-type semiconductor region P serving as a channel of the OSFET are formed.

An N-type diffusion layer N ⁺ serving as a drain of MOSFET NI is coupled to a non-inverting bit line BLT via a predetermined contact, and a gate layer FG serving as a gate thereof is
It is coupled to inversion bit line BLB via a predetermined contact. Similarly, the N-type diffusion layer N ⁺ serving as the drain of the MOSFET J is connected to the inverted bit line B via a predetermined contact.
Gate layer FG, which is coupled to LB and serves as its gate, is coupled to non-inverting bit line BLT via a predetermined contact. Another N-type diffusion layer N ^{+ serving as} a common source of MOSFETs NI and NJ is coupled to a common source line CSN via a predetermined contact. The ground potential VSS is supplied to the two P-type diffusion layers P ⁺ coupled to the channel of each MOSFET via a predetermined contact.

As is well known, in a dynamic RAM having an SOI structure, the parasitic capacitance of a MOSFET can be sufficiently reduced, and its threshold voltage can be individually controlled and set. As a result, in this embodiment, the MOS constituting the auxiliary unit sense amplifier AA
The threshold voltages of the FETs NI and NJ and NK and NL can be reduced relatively easily, and the low threshold voltage MOSF
In addition to realizing ET, the speed of the amplification operation by these auxiliary unit sense amplifiers AA can be further increased, and the dynamic RAM can be further increased in speed. The dynamic RAM according to the present embodiment employs a negative word line system, and has an address selection MOSFET for each memory cell of the memory arrays ARYL and ARYR.
All MOSFETs are low threshold voltage MOS
This will be described in detail in the following fourth embodiment including its effect.

FIG. 9 shows the fourth embodiment of the memory array ARYL and the sense amplifier SA constituting the memory mats MAT0 to MAT7 of the dynamic RAM to which the present invention is applied.
FIG. 10 is a partial circuit diagram of the embodiment, and FIG. 10 is a signal waveform diagram of the embodiment. FIG. 11 is a partial layout diagram of an embodiment of the memory array of FIG. 9, and FIG. 12 is a sectional view taken along the line AB and a line CD of FIG.
A cross-sectional structural diagram is shown. Note that this embodiment basically follows the embodiment of FIGS. 1 to 8, and therefore, a description will be added only for parts different from this.

In FIG. 9, the memory array ARYL constituting the memory mats MAT0 to MAT7 of the dynamic RAM of this embodiment is connected to the complementary bit lines BL0 * to BLn * similarly to the embodiment of FIGS. Correspondingly, a total of 4 × (n + 1) auxiliary unit sense amplifiers AA are provided, and each of these auxiliary unit sense amplifiers AA includes a pair of N-channel MOSFETs NM and NN cross-coupled to each other and NO and NP
Consists of N arranged in each row of the memory array ARYL
MOSF forming +1 auxiliary unit sense amplifier AA
ETNM and NN and the commonly coupled sources of NO and NP have sense amplifier drive signals PA at their gates.
A ground potential VSS is selectively supplied from a driving MOSFET NQ receiving A via a corresponding common source line CSN.

In this embodiment, the memory array ARYL
MOSFETN constituting auxiliary unit sense amplifier AA
M to NP are the same as those in the first to third embodiments. However, as shown in FIGS. 11 and 12, the gates of the address selection MOSFETs of the memory cells conventionally connected to the word lines are connected. By being cross-coupled to the non-inverting bit line BL and the inverting bit line BLB, it can be realized easily and without disturbing the layout pitch of the memory cells. In the case of this embodiment, the MOs constituting the auxiliary unit sense amplifiers AA of the memory array ARYL are used.
SFETNM to NP, address selection MOSFETQ
a, MOSFEN1 to NC constituting the sense amplifier SA
P1 to P3 are all formed as low threshold voltage MOSFETs by a common process. As we all know,
When the address selection MOSFET of each memory cell comprises a low threshold voltage MOSFET, word lines WL0 to WL
In the embodiment shown in FIG. 3 in which the non-selection level of m is set to the ground potential VSS, the amount of charge leakage through the address selection MOSFET increases, and the refresh characteristic of the memory cell is greatly reduced. In order to cope with this, the dynamic RAM of this embodiment employs a negative word line system, and the non-selection level of the word lines WL0 to WLm is set to the level shown in FIG.
0, lower than the ground potential VSS, for example,-
The internal voltage VWN is a negative potential such as 1.0 V.

Thus, even when the word lines WL0 to WLm are at the non-selection level and the memory cells coupled to the non-selected word lines hold data of logic "0", the address selection MOSFET of each memory cell is inverted. By setting a bias state, the amount of leakage can be greatly improved. As a result, a low threshold voltage MOSFET can be easily realized by a common process, and the information retention characteristics of the memory cell can be improved, and the refresh characteristics of the dynamic RAM can be improved.

The functions and effects obtained from the above embodiments are as follows. (1) In a large-capacity dynamic RAM or the like in which the operating power supply voltage is reduced, a memory unit in a memory array is provided separately from a normal unit sense amplifier provided in a sense amplifier corresponding to each complementary bit line. At a predetermined position, an auxiliary unit sense amplifier cross-coupled with a low threshold voltage N-channel MOSFET formed with the same size and pitch as the address selection MOSFET constituting the dynamic memory cell corresponds to each complementary bit line. By providing one or a plurality of memory amplifiers, it is possible to obtain an effect that the operation of amplifying the read signal by each unit sense amplifier of the sense amplifier can be sped up, while suppressing an increase in the required area of the layout of the memory array. (2) According to the above item (1), an effect is obtained that the speed of a dynamic RAM or the like including a sense amplifier can be increased.

(3) In the above items (1) and (2), the auxiliary unit sense amplifier is activated before the unit sense amplifier of the sense amplifier, whereby the auxiliary unit sense amplifier is activated before the unit sense amplifier of the sense amplifier. The effect that the amplification operation of the unit sense amplifier is started and the speed of the dynamic RAM can be further increased can be obtained. (4) In the above items (1) to (3), a so-called SOI structure in which a semiconductor layer is formed on a predetermined insulating film is used to realize a MOSFET having a low threshold voltage required for the auxiliary unit sense amplifier. Alternatively, a negative word line method in which the non-selection level of the word line is set to a negative potential is used to lower the threshold voltage of the memory array and all the MOSFETs directly around the memory array, thereby lowering the necessary level for the auxiliary unit sense amplifier. The effect that the MOSFET having the threshold voltage can be easily realized is obtained. (5) According to the above items (1) to (4), the operating power supply of the dynamic RAM or the like is promoted to lower the voltage, the power consumption is promoted, the rise in the chip temperature is suppressed, and the pause refresh characteristic is improved. The effect of improvement can be obtained.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist of the invention. Needless to say, there is. For example, in FIG. 1, the dynamic RAM can have an arbitrary number of memory mats, and the memory arrays ARYL and ARYR constituting each memory mat are divided into a plurality of sub-arrays including their immediate peripheral portions. Can be. A dynamic RAM is a × 1 bit or × 1 bit.
An arbitrary bit line configuration such as 6 bits can be adopted, and adopting a shared sense system is not an essential condition. The Y address decoder YD may be provided commonly to all memory mats or a predetermined number of memory mats. The dynamic RAM can take an arbitrary block configuration. The names and combinations of the start control signals, the names and effective levels of the control signals and the like, and the polarities and absolute values of the power supply voltage and the respective internal voltages are different from those of the various embodiments. Can be taken.

2 to 3, FIG. 5, FIG. 7, and FIG. 9, the memory arrays ARYL and ARYR can include an arbitrary number of auxiliary unit sense amplifiers AA. Also,
In these embodiments, the auxiliary unit sense amplifier AA is included in the memory array ARYL or ARYR.
It may be provided as a part of A. Memory array A
RYL and ARYR and the sense amplifier SA can include any number of redundant elements. Further, the memory arrays ARYL and ARYR can adopt a so-called word line division system in which main word lines and sub word lines are hierarchically used. Driving MOSFETs P1, N1, NH and NQ are each provided with a plurality of driving
It may be constituted by an SFET, or a plurality of drive MOSFETs may be turned on while shifting in time series. Further, the memory array ARYL
ARYR, the specific configuration of the sense amplifier SA, the conductivity type of the MOSFET, and the like can employ various embodiments.

In FIGS. 4, 6 and 10, the absolute potential and time relationship of each signal does not affect the gist of the present invention. In FIG. 8, the auxiliary unit sense amplifier AA
Can take various embodiments.

In the above description, the case where the invention made by the present inventor is mainly applied to the dynamic RAM, which is the field of application as the background, has been described.
The present invention is not limited to this, and can be applied to, for example, various memory integrated circuit devices having a dynamic RAM as a basic configuration, and logic integrated circuit devices including such a memory integrated circuit device. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a semiconductor memory device having at least a sense amplifier and a device or system including the same.

[0064]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a large-capacity dynamic RAM or the like whose operating power supply is reduced in voltage, a predetermined position in a memory array is provided separately from a normal unit sense amplifier provided in a sense amplifier corresponding to each complementary bit line. One auxiliary unit sense amplifier corresponding to each complementary bit line, in which a low threshold voltage N-channel MOSFET formed at the same size and pitch as the address selection MOSFET constituting the dynamic memory cell is cross-coupled. Alternatively, a plurality of auxiliary unit sense amplifiers may be provided in an operating state prior to, for example, a normal unit sense amplifier of the sense amplifier. In order to lower the threshold voltage of these MOSFETs, a so-called SOI structure in which a semiconductor layer is formed on a predetermined insulating film, or a negative word line method in which a non-selection level of a word line is set to a negative potential is adopted. MOSFE in the memory array and its immediate peripheral part
The threshold voltage of all T is reduced. As a result, it is possible to speed up the operation of amplifying the read signal by each unit sense amplifier of the sense amplifier and increase the speed of the dynamic RAM and the like, while suppressing an increase in the required area of the layout of the memory array. It is possible to promote lowering of voltage, lower power consumption, suppress increase in chip temperature, and improve pause refresh characteristics of a dynamic RAM or the like.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a dynamic RAM to which the present invention is applied.

FIG. 2 is a partial block diagram showing a first embodiment of a memory array and a sense amplifier included in the dynamic RAM of FIG. 1;

FIG. 3 is a partial circuit diagram of the memory array and the sense amplifier of FIG. 2;

FIG. 4 is a signal waveform diagram showing one embodiment of the memory array and the sense amplifier of FIG. 2;

FIG. 5 is a partial block diagram showing a second embodiment of a memory array and a sense amplifier included in a dynamic RAM to which the present invention is applied;

FIG. 6 is a signal waveform diagram showing one embodiment of the memory array and the sense amplifier of FIG. 5;

FIG. 7 is a partial circuit diagram showing a third embodiment of a memory array and a sense amplifier included in a dynamic RAM to which the present invention is applied;

FIG. 8 is a sectional structural view showing one embodiment of an auxiliary unit sense amplifier included in the memory array of FIG. 7;

FIG. 9 is a partial circuit diagram showing a fourth embodiment of a memory array and a sense amplifier included in a dynamic RAM to which the present invention is applied.

FIG. 10 is a signal waveform diagram showing one embodiment of the memory array and the sense amplifier of FIG. 9;

FIG. 11 is a partial layout view showing one embodiment of the memory array of FIG. 9;

12A and 12B are a sectional view taken along the line AB and a sectional view taken along the line CD, respectively, showing an embodiment of the memory cells and the auxiliary unit sense amplifiers of the memory array of FIG. 9;

FIG. 13 is a partial block diagram showing an example of a memory array and a sense amplifier included in a dynamic RAM studied by the present inventors prior to the present invention.

FIG. 14 is a partial circuit diagram of the memory array and the sense amplifier of FIG. 13;

[Explanation of symbols]

MAT0 to MAT7: Memory mat, ARYL, AR
YR memory array, XDL, XDR X address decoder, XB X address buffer, SA sense amplifier, YD Y address decoder, YB Y
Address buffer, WA: Write amplifier, MA: Main amplifier, IB: Data input buffer, OB: Data output buffer, TG: Timing generation circuit. D0
~ D7 ... I / O data or its I / O terminal, RASB
... Row address strobe signal or its input terminal, C
ASB: a column address strobe signal or its input terminal; WEB: a write enable signal or its input terminal; A0 to Ai: an address signal or its input terminal. W
L0 to WLm (WL8j-1), WR0 to WRm ... word lines, BL0 * to BLn *, BR0 * to BRn * ...
Complementary bit line, AA ... Auxiliary unit sense amplifier, UA ...
... Unit sense amplifier, SHL, SHR ... Shared control signal, PC ... Precharge control signal, PA, PAB,
PAA: sense amplifier drive signal, CSP, CSN, C
SNA: Common source line. Qa: Address selection MO
SFET, Cs: Information storage capacitor, HV: Intermediate voltage, S0 * to Sn *: Sense amplifier complementary input / output node, YS0 to YSn: Bit line selection signal, CD *:
Complementary common data line. P1 to P3 ... P-channel MOS
FET, N1-NQ ... N-channel MOSFET. V
CC: power supply voltage, VSS: ground potential, VPP, VD
L: Internal voltage. SiO ₂ ... silicon oxide, P ... P
Type semiconductor region, P ⁺ ...... P-type diffusion layer, N ⁺ ...... N-type diffusion layer, FG ...... gate layer.

Claims (9)

[Claims] 1. A memory array comprising: a word line and a complementary bit line; and a dynamic memory cell including an address selection MOSFET of a first conductivity type and arranged in a grid at an intersection of the word line and the complementary bit line. A sense amplifier provided corresponding to each complementary bit line of the memory array and including a unit sense amplifier including a first MOSFET of a first conductivity type having a gate and a drain cross-coupled to each other; Auxiliary unit sense including a second MOSFET of a first conductivity type provided corresponding to a complementary bit line, having a gate and a drain cross-coupled to each other and having an element structure basically the same as the address selection MOSFET. A semiconductor memory device comprising: an amplifier. 2. The second MOSFE according to claim 1, wherein said second MOSFET comprises said auxiliary unit sense amplifier.
T is a semiconductor memory device provided in the memory array and having the same size and pitch as the address selection MOSFET. 3. The semiconductor memory device according to claim 1, wherein a plurality of the auxiliary unit sense amplifiers are provided at a predetermined distance in the memory array. 4. The normal MOSFET according to claim 1, wherein the second MOSFET is not subjected to a process for controlling a threshold voltage.
A semiconductor memory device having a threshold voltage smaller than that of the semiconductor memory device. 5. The memory array according to claim 1, wherein the MOSF comprises a memory array and a sense amplifier.
ET has a relatively small threshold voltage including the first MOSFET, and the semiconductor memory device adopts a negative word line system in which a non-selection level of a word line is set to a negative potential. A semiconductor memory device, comprising: 6. The semiconductor memory device according to claim 4, wherein the semiconductor memory device has an SOI structure in which a semiconductor layer is formed on a predetermined insulating film. 7. The second conductivity type according to claim 1, wherein said unit sense amplifier is cross-coupled with its gate and drain. And the third MOSFET is selectively operated by a low-potential-side and a high-potential-side operating power supply being selectively supplied to the first and second common source lines. Wherein the auxiliary unit sense amplifier is selectively operated by the low-potential-side operation power supply being selectively supplied to a third common source line. Storage device. 8. The semiconductor memory device according to claim 7, wherein a low-potential-side operation power supply is supplied to the third common source line prior to the first common source line. . 9. The semiconductor memory device according to claim 1, wherein the semiconductor memory device employs a shared sense system. A dynamic RAM, wherein the memory array is provided on both sides of the sense amplifier and is selectively connected to the sense amplifier via a shared MOSFET; A semiconductor memory device provided in each of arrays.