JPH0720765Y2 - Level detector - Google Patents

Description

[Detailed Description of the Invention] << Industrial Application Field >> The present invention relates to a level detection circuit for detecting the level of serially transmitted digital data, and particularly to a DAT start ID (hereinafter abbreviated as S-ID). It is suitable for use in a level detection circuit for an input digital signal required for recording.

<< Prior Art >> An example of a conventional level detection circuit will be described below with reference to a block diagram shown in FIG. 9 and a timing chart shown in FIG. The digital data is linearly quantized and represented by a 2'S complement code, and it is assumed that the level of this digital data is detected to be -40 dB or higher.

16-bit digital data serially transmitted in synchronization with the bit clock (BCK) and word clock (WCK) is input to the input terminal I ₁ of the serial / parallel conversion circuit 50, and the bit clock and word clock are input. Do
The output of AND51 is input to the input terminal I ₂ as the shift clock (SCK) via INV52, and the word clock is input to INV5.
It is input to the input terminal I ₃ as a latch clock (RCK) via 3. The serial / parallel conversion circuit 50 takes in digital data at the rising edge of the shift clock, performs serial / parallel conversion at the rising edge of the latch clock, and outputs it from the output terminals O _{1 to} O ₁₆ .

The digital data output from the output terminals O _{1 to} O ₇ are input to the AND 54 and the AND 62 via INV 55 to 61, respectively, and M
It is detected whether SB to 7SB have the same logic. Note that the linearly quantized digital data has a bit of about 6 dB, and when it is about -40 dB or less, MSB to 7SB always have the same logic. Then, the outputs of AND54 and AND62 are input to NOR63, and become "H" when the output of NOR63 is approximately -40 dB or more.

<Problems to be solved by the invention> The conventional level detection circuit described above converts serially transmitted digital data into serial / parallel data,
Since the logic state of each bit is detected at the same time, many gate circuits are required, and there is a drawback that the cost becomes high as a whole. In particular, when the detection level is low, such as when the detection level is set to -60 dB, more gate circuits are required, and the circuit configuration becomes complicated.

<< Means for Solving the Problems >> In order to solve this problem, the present invention inputs a delay circuit for delaying digital data, digital data and delayed digital data output from the delay circuit, and An adjacent bit signal output circuit that outputs an adjacent bit signal that is in the first state when the states are different and is in the second state when the states between adjacent bits are the same, and a clock for detecting the state of the adjacent bit signal. And a level detection circuit for detecting, based on the clock, that the adjacent bit signal corresponding to the most significant bit to the bit corresponding to the desired level of the digital data is in the first state. Provided is a level detecting device.

Also, the present invention inputs a delay circuit for delaying digital data and the digital data and the delayed digital data output from the delay circuit, and a state between adjacent bits corresponding to bits from the most significant bit to a bit corresponding to a desired level. Responding to an adjacent bit signal output circuit that outputs an adjacent bit signal that is in the first state when the adjacent bit signals are in the first state and that is in the second state when the states between adjacent bits are the same, and that the adjacent bit signal is in the first state. Then, there is provided a level detecting device including a level detecting circuit for detecting that the digital data has a desired level or higher.

The present invention also provides a delay circuit for delaying digital data, a selection circuit for selecting and outputting digital data and delayed digital data output from the delay circuit, and inputting digital data and digital data output from the selection circuit to adjacent bits. An adjacent bit signal output circuit that outputs an adjacent bit signal that becomes a first state when the states between adjacent bits are different and a second state when the states between adjacent bits are the same, and a desired level from the most significant bit of the digital data. The adjacent bit signal that does not correspond to the bit corresponding to
In response to the control signal output circuit for controlling the selection circuit to selectively output the digital data so as to bring the digital signal into the state 1 and the adjacent bit signal being in the first state, the digital data is at a desired level or higher. There is provided a level detecting device including a level detecting circuit for detecting that.

The present invention also provides a delay circuit for delaying digital data, a selection circuit for selecting and outputting the digital data and the delay digital data output from the delay circuit, and inputting the delay digital data and the digital data output from the selection circuit. An adjacent bit signal output circuit that outputs an adjacent bit signal that becomes a first state when the states between bits are different and a second state when the states between adjacent bits are the same;
Control signal output for controlling the selection circuit to selectively output delayed digital data in order to forcibly bring the adjacent bit signal that does not correspond to the most significant bit of the digital data to the bit corresponding to the desired level to the second state Circuit,
There is provided a level detecting device including a level detecting circuit for detecting that the digital data is at a desired level or higher in response to the adjacent bit signal being in the first state.

<< Operation >> According to the level detecting apparatus, the digital data represented by the 2'S complement code and serially transmitted is delayed by the delay circuit. The digital data and the delayed digital data are input to the adjacent bit signal output circuit, the adjacent bits of the digital data are compared, and when the states between the adjacent bits are different, the first state is entered, and when the states between the adjacent bits are the same, the second bit is output. It is output as an adjacent bit signal in the state of. The output adjacent bit signal is input to the level detection circuit, the state of the adjacent bit signal corresponding to the bit corresponding to the desired level from the most significant bit of the digital data is detected based on the clock, and in the first state. At some point, it is determined that the level is above the desired level.

Further, according to the level detecting apparatus, the digital data represented by the 2'S complement code and transmitted serially is delayed by the delay circuit. The digital data and the delayed digital data are input to the adjacent bit signal output circuit, the adjacent bit signals corresponding to the bits corresponding to the desired level from the most significant bit of the digital data are compared, and when the states between the adjacent bits are different, In the state of 1,
When the states between adjacent bits are the same, it is output as an adjacent bit signal which becomes the second state. The output adjacent bit signal is input to the level detection circuit, and is determined to be at or above the desired level when in the first state.

Further, according to the level detecting apparatus, the digital data represented by the 2'S complement code and transmitted serially is delayed by the delay circuit. The digital data and the delayed digital data are selectively output by the selection circuit. The digital data and the digital data output from the selection circuit are input to the adjacent bit signal output circuit, and become the first state when the states between the adjacent bits are different, and the second state when the states between the adjacent bits are the same. It is output as a bit signal. The control signal output circuit forcibly places the adjacent bit signal that does not correspond to the bit corresponding to the desired level from the most significant bit of the digital data to the second state,
The selection circuit controls so as to selectively output the digital data. On the other hand, the output adjacent bit signal is input to the level detection circuit and is determined to be at or above the desired level when in the first state.

Further, according to the device of the present invention, the digital data represented by the 2'S complement code and serially transmitted is delayed by the delay circuit. The digital data and the delayed digital data are selectively output by the selection circuit. The delayed digital data and the digital data output from the selection circuit are input to the adjacent bit signal output circuit, and become the first state when the states between the adjacent bits are different, and the second state when the states between the adjacent bits are the same. It is output as an adjacent bit signal. The control signal output circuit forcibly places the adjacent bit signal that does not correspond to the bit corresponding to the desired level from the most significant bit of the digital data to the second state,
The selection circuit controls so as to selectively output the delayed digital data. On the other hand, the output adjacent bit signal is input to the level detection circuit and is determined to be at or above the desired level when in the first state.

<Embodiment> The present invention provides a level detecting device which solves the above-mentioned problems, and hereinafter, a block shown in FIG. 1 when applied to a level detecting device required for S-ID recording of DAT. Description will be given with reference to the drawings.

Input digital data linearly quantized is input to the input terminal 1, a digital audio interface 2 decodes the DAIF format is input to the input terminal 2 ₁ (hereinafter, abbreviated as DAIF2) is carried out, digital signal processing LSI format from the output terminal 2 _2,
The audio data represented by the 2'S complement code is output. In addition, DAIF2 forms a PLL circuit by connecting a clock generation circuit to terminals 2 ₃ to ₂₅ ,
A master clock is generated based on the input digital data, internal signal processing is performed by various clocks based on the master clock, and a signal processing circuit 4 described later is also provided.
System clock (128FS), bit clock (BCK), word clock (WCK) and L / R clock (L
RCK) is output from the output terminal 2 _{6-2 9.} The DAIF2 outputs the unlock signal to "H" in the unlocking of the PLL circuit constituted of the output terminal 2 _10.

The system clock, bit clock, word clock, and L / R clock are each sampling frequency FS.
(48kHz for DAT) 128 times, 64 times, 2 times and 1
The audio data is serially transmitted from the MSB in synchronization with the bit clock while the word clock is “H”, the L / R clock is “L” and the audio data is Lch.
“H” indicates Rch. Audio data output from the (see FIG. 3) DAIF2 is input to the input terminal 4 _first signal processing circuit 4, a recording signal processing in accordance with the DAT format using RAM5 is performed, recorded RF from the output terminal 4 ₂ It is output as a signal. In addition, the signal processing circuit 4 uses the system clock, bit clock,
Input the word clock and L / R clock from input terminals 4 ₃ to 4 ₆ .

The recording RF signal output from the signal processing circuit 4 is input to the input terminal 6 ₁ of the recording equalizer amplifier 6, and output terminals 6 ₂ and 6 ₃
Are output as A head recording signals and B head recording signals. The A head recording signal and the B head recording signal are the plus azimuth recording head 8A, which is arranged to face the rotary drum 7,
Each is input to the recording head 8B of minus azimuth and recorded on the tape T wound around the rotary drum. The arrows A and B indicate the rotational direction of the rotary drum 7 and the tape T, respectively.
Shows the running direction of tape T, and the winding angle of tape T is 90 °
Is set to.

Reference numeral 9 denotes a microcomputer, and the microcomputer 9 is a normally open recording mode switch SW ₁ , whose one end is grounded to the input ports P _{1 to} P ₄ .
The reproduction mode switch SW ₂ , the pause mode switch SW _3, and the stop mode switch SW ₄ are connected to each other, and the unlock signal output from the DAIF 2 is input to the input port P ₅ . The microcomputer 9 enters each mode state by pressing each mode switch, but only when the unlock signal is "L"
Enter recording mode. The microcomputer 9, IDMUTE signal output during recording mode from the output port P _6, P _7, and to "H" RPLY signal, STID signal output from the AND23 to be described later is input to the input port P _8. Furthermore, the microcomputer 9 is DAIF
2. When the control line is connected between the signal processing circuits 4 and the input port P ₈ becomes "H", the tape T is given a predetermined period S-
The S-ID information is processed by the signal processing circuit 4 so that the ID signal is written.
In addition, sub-code information from DAIF2, operation mode information and the like are supplied to the signal processing circuit 4.

Here, the recording format of the DAT will be briefly described in order to know the recording location of the S-ID signal.

FIG. 2 (A) shows a track format when a drum of 30Φ, 90 ° wrap angle and 2000 rpm is used. In the figure, “[]” is the number of blocks (288 bits).

This SUB-1 has a subcode ID / SY as shown in (B).
NC / block address & subcode ID / each 8 bits /
The data (subcode data + parity) is composed of 256 bits, which is 288 bits in total. Note that the number inside "[]" in the figure is the number of bits. Further, as shown in (C), the format of SYNC / block address & subcode ID is different between the even track and the odd track.
Each TA ID / CONTROL ID consists of 4 bits / 1 / FORMAT ID consists of 3 bits / block address consists of 4 bits, and odd tracks have PNO ID (2) / PNO ID (3) of 4 bits / 1 / PN
O ID (1) is composed of 3 bits / block address is composed of 4 bits. Further, as shown in (D), the data ID of the even-numbered track is composed of 1 bit each of TOC-ID / S-ID / priority ID / shortening ID. Thus S-
It exists in the SUB code area of even-numbered tracks at the ID recording location, and it is regulated to write over 300 frames ± 30 frames. The SUB-2 is the same as the SUB-1.

Next, the level detection device and its peripheral circuits, which are the features of the present invention, will be described.

The D-type flip-flop (hereinafter abbreviated as D-FF) 10 is D
The IDMUTE signal output from the micro 9 is input to the terminal, the word clock is input to the CK terminal, and the Q terminal is connected to one input of the AND 11. AND11 inputs the audio data output from DAIF2 to the other input, and its output is D-FF
It is connected to the D terminal of 12 and one input of E-OR13. D-FF12
Bit clock is input to the CK terminal and its Q terminal is E-
It is connected to the other input of OR13, and the output of E-OR13 is connected to the B terminal of one-shot multivibrator (hereinafter abbreviated as O-MV) 14.

On the other hand, in D-FF15, a word clock is input to the D terminal and a bit clock is input to the CK terminal, and its Q terminal is connected to the CK terminal of D-FF16. The D terminal of D-FF16 is always "H", and the Q output is connected to one input of OR17. The bit clock is input to the other input of the OR17, and its output is connected to the terminal of the O-MV14.

Switch SW ₇ is on / off of S-ID recording and detection level -40dB / -6 provided on the front panel (not shown).
This switch is for selecting 0 dB, and is composed of switches SW ₅ and SW ₆ which are interlocked with each other. Switch SW ₅ has contacts T ₅₂ and T _54.
Is connected to the power supply via resistor R ₁ , contact T ₅₃ is connected to ground, and switch SW ₆ has contact T ₆₂ connected to the power supply via resistor R ₁ and contacts T ₆₂ and T ₆₄ are connected to ground. It is grounded. Therefore, when the switch SW ₇ is operated to the upper side of the drawing so that the S-ID is automatically recorded at the detection level of -40 dB, the contacts T ₅₁ and T _{61 of the} switches SW ₅ and SW ₆ become "H". , S-ID
When the switch SW ₇ is operated toward the side of the drawing so that is not automatically recorded, the contacts T ₅₁ and T _{61 of} each switch SW ₅ and SW ₆ become “L”, and the S-ID at the detection level −60 dB. When the switch SW ₇ is operated to the lower side of the drawing so as to automatically record, the contacts T ₅₁ and T _{61 of the} switches SW ₅ and SW ₆ become “H” and “L”, respectively. If the S-ID is not automatically recorded, the contact T ₆₃ of the switch SW ₆ may be connected to the power supply via the resistor R ₁ because it does not relate to the detection level.

The terminal T ₆₁ of the switch SW ₆ is connected to the D terminal of the counter 18 and INV1
It is connected to the C terminal and the A terminal via 9 and the B terminal is always grounded. The word clock is input to the ▲ ▼ terminal of the counter 18, the bit clock is input to the CK terminal via the INV 20, and the RC terminal is connected to the D terminal of the D-FF21. The bit clock is input to the CK pin of D-FF21,
The terminal is connected to the ▲ ▼ terminal of D-FF16. The counter 18 presets the count value in each state of the D to A terminals (the D terminal is the upper side). When the LOAD terminal becomes "L", the respective states of the D to A terminals are changed to the QD to QA terminals, respectively. When the LOAD pin goes to "H", it counts up from the preset count value for each clock input to the CK pin, and outputs the count value to the QD to QA pins. When the count value of the counter 18 is maximum (15),
The RC terminal is set to "H".

On the other hand, O-MV14 is connected to the RX / CX terminal via the capacitor C ₁ with CX terminal is grounded, also RX / CX terminal is connected to a power supply via a resistor R _2, R _3. Also, the emitter and collector of the PNP transistor TR ₁ are connected to the connection point of the power supply and the resistors R ₂ and R ₃ , respectively, and the transistor TR ₁ is the base,
A resistor R ₄ is connected between the emitters, and the RPLY signal is input to the base via the resistor R ₅ . In addition, O-MV14 is 0.463
The time constant is set by the formula of × C ₁ × (R ₂ + R ₃ ). Here, it takes about 2 seconds when the RPLY signal becomes “H”, and about 0.02 seconds when the RPLY signal becomes “L”. As C ₁ , R ₂ and R ₃
The value of is set.

The B terminal of the O-MV22 is connected to the Q terminal of the O-MV14, and the terminal is grounded to the ground.

The O-MV22 is connected to the RX / CX terminal via the capacitor C ₂ with CX terminal is grounded, also RX / CX terminal is connected to a power supply via a resistor R _6. O-MV22 is also O-
Similarly to the MV14, the time constant is set by the equation of 0.463 × C ₂ × R ₆ , and here, the values of C ₂ and R ₆ are set so as to be approximately 2 seconds. The O-MVs 14 and 22 are triggered when the B terminal is "H" and the terminal is "L", and when the terminal is "L" and the B terminal is "H".

AND23 to one input terminal Q of the O-MV22, the other input is connected to the terminal T ₅₁ of the switch SW _5, and outputs the STID signal to the input port P ₈ of the microcomputer 9.

Next, the operation of the level detecting device when the S-ID is automatically recorded at the detection level of -40 dB will be described. In this case, since the switch SW ₇ is operated to the upper side of the drawing, the switches SW ₅ and S
The contacts T ₅₁ and T _{61 of} W ₆ both become “H”, the other input of the AND 23 is “H”, and the count value of the counter 18 is preset to 8.

First, the operation in the stop mode will be described with reference to the timing chart shown in FIG.

In the stop mode, the microcomputer 9 sets both the IDMUTE signal and the RPLY signal to "L". The IDMUTE signal is latched by D-FF10 at the rising edge of WCK, and is output according to the MSB of audio data. Since the IDMUTE signal is "L", the Q terminal of D-FF10 also becomes "L", and the audio data is muted by AND11. When the RPLAY signal becomes “L”, the transistor TR ₁ is turned on, so that the time constant of the O-MV14 is set to about 0.02 seconds.

On the other hand, D-FF12, since audio data is slightly delayed with respect to the bit clock (not shown), bit clock each bit of the next audio data output from the AND11, for example the bit clock of the time t ₂ the MSB , 2SB is taken in at the bit clock at time t ₃ ..., and output from the Q terminal. Therefore, the E-OR13 receives the audio data and the audio data delayed by one cycle of the bit clock, and outputs the exclusive OR between the bits (MSB and 2SB, 2SB and 3SB, ..., 15SB and LSB). Since the audio data output from AND11 is muted here, the output of the Q terminal of D-FF12 and E-OR13 is also "L".

On the other hand, when at time t ₁ word clock becomes "H", the counter 18 starts counting up every falling time t ₁ after the bit clock. D-FF 15 takes in the "H" of the word clock at the bit clock time t _2, the Q-terminal to to "H". Since the bit clock is slightly behind the word clock (not shown), D-FF15 is set at time t ₁
Cannot capture word clock "H" with the bit clock of. When the Q terminal of D-FF15 becomes "H", D-FF16 sets the terminal to "L" and thereafter the output of OR16 becomes the same as the bit clock. A bit clock time t _8, the counter 18 the count value reaches the maximum "15", the RC terminal from time t ₈ to "H" between the bit clock one cycle. D-FF 21 is a pin with a bit clock of the time t ₃ to "L", D-FF16 is set to "H" terminal is reset. Therefore, the output of OR17 is also "H"
become. In the bit clock time t _10, D-FF 15 is the "L" of the word clock uptake, and the Q terminal "L".

Thus, from E-OR13 to MSB and 2SB, 2SB and 3SB, ……… 6S
At time t ₃ ~t ₈ logical result of B and 7SB is combined with timing to be outputted, the output of OR17 is "L".

Even if the output of OR17 becomes the "L" at a time t ₃ ~t _8, output so is always "L" of the E-OR13, O-MV14 is kept of the Q terminal not triggered "L". Therefore, the O-MV22 is not triggered either and the Q terminal remains "L", and the input port _{8 of the} microcomputer 9 is also "L".
The condition continues.

Next, the operation in the recording mode will be described with reference to the timing chart shown in FIG.

In the recording mode, the microcomputer 9 sets both the IDMUTE signal and the RPLY signal to "H". The IDMUTE signal is latched by the D-FF10 at the rising edge of the word clock, and is output according to the MSB of audio data. ID-MUTE signal is "H", so D-FF
The Q terminal of 10 also becomes "H", and audio data is output via AND11. It is assumed that the value of the audio data in FIG. 3B is "0000001011000000" and the detection level (-40 dB) is exceeded for the first time after the recording mode is entered. When the RPLAY signal becomes "H", the transistor TR ₁ is turned off and the time constant of O-MV14 is set to about 2 seconds.

Similar to the above, D-FF12 takes in each bit of the audio data output from AND11 at the next bit clock and outputs it from the Q terminal, and E-OR13 outputs between bits (MSB and 2SB, 2SB and 3SB, ...
Outputs the exclusive OR of 15SB and LSB). Since the audio data here is "0000001011000000", E-OR1
3 is audio data 6SB and 7SB, 7SB and 8SB, 8SB and 9S
Outputs "H" when B, 10SB and 11SB are input. In addition, the time t _{13 to} t, which is the timing when the logical results of MSB and 2SB, 2SB and 3SB, ... 6SB and 7SB are output from E-OR13
_{At 18} , the output of OR17 goes low.

Even if the output of OR17 becomes the "L" at a time t ₁₃ ~t _17, output so is always "L" of the E-OR13, O-MV14 is kept of the Q terminal not triggered "L". Therefore, the O-MV22 is not triggered either and the Q terminal remains "L", and the input port _{8 of the} microcomputer 9 is also "L".
The condition continues. However, at time t ₁₈ , the output “L” of OR17
Then, because the output of E-OR13 is "H", O-MV14 is triggered and Q terminal is set to "H". Thus, O-MV22 also triggers the Q terminal and "H", the input port P ₇ of the microcomputer 9 is "H". The microcomputer 9 detects this and sends information to the signal processing circuit 4 so that the S-ID is written. O-MV22 is Q
Set the terminal to “L” 2 seconds after the time t _{18 when the} terminal is triggered.

After that, the above operation is repeated and the time constant of O-MV14 (2 seconds)
If audio data of -40 dB or more (MSB to 7SB are not the same logic) continues within, the O-MV14 is triggered again and the Q terminal remains "H".

Also, O-MV14 is -40 dB or less (MSB to 7SB
If the audio data of the same logic) continues for 2 seconds or more, the Q terminal is set to "L", and when audio data of -40 dB or more is input again, it is triggered and the Q terminal is set to "H", and the O-MV22 is also triggered. Set the Q terminal to "H". Therefore, the input port P ₇ of the microcomputer 9 becomes “H”, and the microcomputer 9 sends information to the signal processing circuit 4 so that the S-ID is written again.

Next, the operation at the time of changing each mode will be described with reference to the timing chart shown in FIG.

In stop mode, IDMUTE signal, RPLY as described above
Since the signal is "L", the digital data output from AND11 is muted, and the O-MVs 14 and 22 are not triggered and the Q terminal remains "L".

When the recording mode is entered at time t ₂₁ , the IDMUTE signal, RPLY
The signal becomes "H", and digital data is output from AND11. When digital data at time t ₂₂ is detected to be at detection level or more, O-MV14 is set to "H" is triggered Q terminal, O-MV22 also be triggered to "H" Q terminal. Therefore, the input port P ₇ of the microcomputer 9 is "H".
Then, the microcomputer 9 sends information to the signal processing circuit 4 so that the S-ID is written. Also, O-MV22 is 2 from time t _22.
After a few seconds, set the Q terminal to "L". After that, digital data above the detection level continues, and the O-MV14 is triggered many times to keep the Q terminal at "H". Thereafter, when the digital data is below the detection level, O-MV14 is to "L" Q terminal from the last trigger the time t ₂₃ after 2 seconds.

When transitioning to the suspend mode at time t ₂₄ , the IDMUTE signal and RPLY signal go to "L" as in the suspend mode, the digital data output from AND11 is muted, and the O-MV14,22
Is not triggered and the Q terminal remains "L". When the RPLY signal goes low, the O-MV14 time constant is set to 0.02 seconds.

When the pause mode is canceled at time t ₂₅ and the mode is changed to the recording mode again, the IDMUTE signal and RPLY signal become “H”, and AN
Digital data will be output from D11. When it is detected that the digital data is equal to or higher than the detection level at the time t ₂₆ , the O-MV14 is triggered to set the Q terminal to "H", and the O-MV22 is also triggered to set the Q terminal to "H". Therefore,
The input port P ₇ of the microcomputer 9 becomes “H”, and the microcomputer 9 sends information to the signal processing circuit 4 so that the S-ID is written again. In addition, O-MV22 is to "L" Q terminal from the time t ₂₆ after 2 seconds. After that, digital data above the detection level continues, and the O-MV14 is triggered many times to keep the Q terminal at "H".

At time t ₂₇ , when digital data of the detection level or higher continues, if the mode changes to the pause mode, the IDMUTE signal,
The RPLY signal goes "L", the digital data output from AND11 is muted, and the O-MV14 time constant is set to 0.02 seconds. Therefore, the O-MV 14 sets the Q terminal to “L” 0.02 seconds after the time t ₂₇ last triggered.

When the pause mode is released at time t ₂₈ and the recording mode is entered again, the IDMUTE signal and RPLY signal go to “H”, and AN
Digital data is output from D11. Since the digital data is already above the detection level, the O-MV14 is immediately triggered to set the Q terminal to "H", and the O-MV22 is also triggered to set the Q terminal to "H". Therefore, the input port of the microcomputer 9
P ₇ becomes “H”, and the microcomputer 9 sends information to the signal processing circuit 4 so that the S-ID is written again. In addition, O-MV22 is to "L" Q terminal from the time t ₂₈ after 2 seconds. After that, AND11 outputs digital data above the detection level, and O-MV
14 is triggered many times and the Q terminal remains "H".

As described above, when the IDMUTE signal and the RPLY signal are set to "L" except in the recording mode, the O-MV14 immediately sets the Q terminal to "L", and shifts to the recording mode when the audio data is above the detection level. If so, O-MV14,22 is triggered immediately. If the audio data is below the detection level and the recording mode is entered, the O-MV14,22 is not triggered until the audio data reaches the detection level or higher, and the O-MV14,22 is not triggered until the audio data reaches the detection level or higher. Is triggered. Also,
When transitioning to recording mode, pause mode, or recording mode while digital data above the detection level continues, the O-MV14 will output the RPLY signal even if the pause mode is short (2 seconds or less). As a result, the time constant is set to be short, so when the Q terminal is immediately set to "L" and the recording mode is entered again to be triggered, the Q terminal is set to "H" and the O-MV22 is triggered. Therefore, even if the pause mode is short, the S-ID is surely written in the recording mode.

In the above operation example, the detection level is −40 dB. However, when the detection level is −60 dB, the counter 18 is preset to 5, so that the E-OR 13 outputs MSB and 2SB, 2SB and 3SB, ...
The output of OR17 goes to "L" at the time when the logical results of 9SB and 10SB are output, and the other operations are the same as at -40dB, so a detailed explanation of the operation is omitted.

Next, another embodiment of the level detecting device of the present invention will be described with reference to FIGS. The same components as those shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

The embodiment shown in FIG. 1 detects the states of adjacent bit signals from MSB to the bit corresponding to 7SB by detecting the states of MSB to L.
The adjacent bit signal of all bits across SB is output from E-OR13, and the clock is output from OR17 only during the period corresponding to the adjacent bit signal from MSB to 7SB, while the embodiment shown in FIG. , The output of E-OR13 is connected to one input of AND24, the Q terminal of D-FF16 is connected to the other input of AND24, and the output of AND24 is connected to the B terminal of O-MV14. -By controlling AND24 with the signal output from the Q terminal of FF16, the adjacent bit signal that does not correspond to the detection level is set to "L", and the bit clock is always supplied to the terminal of O-MV14. .

Also, since only the adjacent bit signal corresponding to the detection level is supplied to the B terminal of the O-MV14, as shown in FIG.
14 terminals may be connected to ground. In this case O-
MV14 is triggered by the state change of the B terminal, that is, the state change of the adjacent bit signal.
It is necessary to sufficiently consider the delay time of each logic circuit so that only adjacent bit signals up to are output.

Fig. 7 shows the output of AND11 to one input of AND25 and the output of D-FF12 to one input of AND26 so that only the adjacent bit signal corresponding to the detection level is output from E-OR13.
Connect the Q terminal of F16 and the output of the terminal to the other input of AND25 and 26 respectively, and the output of AND25 and 26 via E27 to E-OR13.
Connected to the other input of D-FF16, and the AND2
By controlling 5,26, the output data of AND11 is supplied to both inputs of E-OR13 for a predetermined period, the adjacent bit signal which does not correspond to the detection level is set to "L", and O-MV14
The bit clock is always supplied to the terminal.

Fig. 8 shows the output of AND11 to one input of AND28, the output of D-FF12 to one input of AND29, and DF so that only the adjacent bit signal corresponding to the detection level is output from E-OR13.
Connect the output of the F16's Q terminal and terminal to the other input of AND28, 29, respectively, and the output of AND28, 29 via OR30 to E-OR13
Connected to the other input of D-FF16, and the AND2
By controlling 8, 29, the output data of D-FF13 is supplied to both inputs of E-OR13 for a predetermined period, and the adjacent bit signal which does not correspond to the detection level is set to "L", and O is the same as in FIG. -MV14
The bit clock is always supplied to the terminal.

In addition, in FIGS. 7 and 8 as well, as shown in FIG.
It is possible to connect the terminal of
When the same output data is supplied to both inputs of OR13, when the state between adjacent bits is different due to the delay time of AND25 and OR27 in FIG. 7 and AND29 and OR30 in FIG.
There is a period when the output of OR13 becomes "H", which causes malfunction and is not desirable.

The present invention is not limited to the above-mentioned embodiment, and various modes are obtained.

For example, in the above embodiment, it is used in the level detecting device for S-ID recording of DAT, but it is not limited to this and can be used in various applications and is limited to the above circuit configuration. It is not a thing, and its detection level is -40d
Not limited to B, −60 dB.

<< Advantages of the Invention >> According to the level detection device of the present invention, the level is detected while the digital data is kept in the serial state, so that many gate circuits are not required and the circuit configuration is simple. Will be things.

[Brief description of drawings]

FIG. 1 is a circuit diagram of the level detecting device of the present invention when applied to a DAT, FIG. 2 is a track format diagram of the DAT, and FIG. 3 (A) is a stop mode of the device of the present invention shown in FIG. FIG. 3B is a timing chart showing an operating state, FIG. 3B is a timing chart showing an operating state in the recording mode of the apparatus of the present invention shown in FIG. 1, and FIG. 4 is a mode of the apparatus of the present invention shown in FIG. Timing chart showing operating state during change, fifth
8 to 12 are circuit diagrams showing another embodiment of the device of the present invention when applied to a DAT, FIG. 9 is a conventional level detecting device, and FIG. 10 is a conventional level detecting device shown in FIG. 3 is a timing chart of each signal of FIG. Explanation of symbols 1 ... Input terminal, 2 ... DAIF, 4 ... Signal processing circuit, 9
...... Microcomputer, 10,12,15,16,21 …… D-FF, 11,23,24,25,
26,28,29 …… AND, 13 …… E-OR, 17,27,30 …… OR, 18…
… Counter, 19,20 …… INV.

Claims (4)

[Scope of utility model registration request] 1. A level detector for detecting the level of serially transmitted digital data represented by a 2'S complement code, comprising a delay circuit for delaying the digital data, the digital data and the delay circuit. An adjacent bit signal output that inputs the output delayed digital data and outputs an adjacent bit signal that enters the first state when the states between adjacent bits are different and outputs the second state when the states between adjacent bits are the same A circuit, a clock generation circuit for outputting a clock for detecting the state of the adjacent bit signal, and the adjacent bit signal corresponding to a bit corresponding to a desired level from the most significant bit of the digital data to the first bit. A level detection circuit for detecting that the clock is in a state based on the clock. Detector. 2. A level detector for detecting the level of serially transmitted digital data represented by a 2'S complement code, comprising a delay circuit for delaying the digital data, the digital data and the delay circuit. The delayed digital data that has been output is input to the first state when the states between adjacent bits corresponding to the most significant bit to the bit corresponding to the desired level are different, and the second state when the states between adjacent bits are the same. And an adjacent bit signal output circuit for outputting an adjacent bit signal in the state of ## EQU1 ## and a level detection for detecting that the digital data is above a desired level in response to the adjacent bit signal in the first state. A level detection device comprising a circuit. 3. A level detector for detecting the level of serially transmitted digital data represented by a 2'S complement code, comprising a delay circuit for delaying the digital data, the digital data and the delay circuit. The selected delay digital data output and the selection circuit for outputting and the digital data and the digital data output from the selection circuit are input, and when the state between adjacent bits is different, the first state is set, and the state between adjacent bits is set. An adjacent bit signal output circuit that outputs an adjacent bit signal that is in the second state at the same time and the adjacent bit signal that does not correspond to the bit corresponding to the desired level from the most significant bit of the digital data are forcibly The control circuit controls the selection circuit to selectively output the digital data so that the state 2 is obtained. A control signal output circuit and a level detection circuit for detecting that the digital data is at a desired level or higher in response to the adjacent bit signal being in the first state. Level detector. 4. A level detector for detecting the level of serially transmitted digital data represented by a 2'S complement code, comprising a delay circuit for delaying the digital data, the digital data and the delay circuit. Select the output delayed digital data Selective output, and input the delayed digital data and the digital data output from the selection circuit, to the first state when the state between adjacent bits is different, the state between adjacent bits And an adjacent bit signal output circuit that outputs an adjacent bit signal that is in the second state when the same is the same, and the adjacent bit signal that does not correspond to the bit corresponding to the desired level from the most significant bit of the digital data. The selection circuit is controlled so as to selectively output the delayed digital data so as to be in the second state. And a level detection circuit for detecting that the digital data is at a desired level or higher in response to the adjacent bit signal being in the first state. And level detector.