JPH0725726Y2 - Address application device for semiconductor test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION "Industrial Application Field" The present invention relates to an address application device of a semiconductor test device for selecting a test address and a refresh address by a selection circuit and supplying the selected dynamic RAM to a dynamic RAM under test.

"Prior Art" In dynamic RAM, so-called refreshing is required to repeatedly read data in addition to actually writing or reading data, in order not to erase the memory. Therefore, even in the semiconductor test equipment that tests the dynamic RAM, the refresh address is dynamically set while the test address is not applied to the dynamic RAM.
Must be applied to RAM. For this reason, the address applying device of the conventional semiconductor test device is constructed as shown in FIG. That is, the lower 6 bits of the test address X0 to 11
X0 to 5 are supplied to the selection circuit 11, and the upper 6 bits X6 to 11 are supplied to the selection circuit 12. Also, the lower 6 of the refresh addresses RF0 to 11 from the refresh address generator 13
Bits RF0-5 are supplied to the selection circuit 11 and the upper 6 bits R
F6 to 11 are supplied to the selection circuit 12. The selection circuit 11 is a 2-input 1-output multiplexer, and the selection circuit 12 is 3-input 1-output.
Output multiplexer, one input of which output is fed back. When the refresh enable is applied in the selection circuits 11 and 12, the refresh address is selected respectively, and when the refresh enable is not applied, the test address is selected. Selection circuit 1
The addresses selected in 1 and 12 are applied addresses M0 to
5, M6 ~ 11. The selection circuit 12 can mask refresh address interrupts to the applied addresses M6 to 11 depending on the contents of the interrupt format register 14. The refresh address generator 13 only performs either an increment or a hold operation during the test.

[Problems to be solved by the invention] The bit pattern when the refresh address interrupts the applied address M0 to 11 outputs only the bit pattern of increment or hold (similar to the previous refresh cycle). Therefore, depending on the RAM, it is difficult to refresh the target cell. In other words, depending on the RAM 1,2,3 ...
When an address that continuously changes is applied, the physical positions on the memory may skip everywhere without sequentially accessing adjacent positions. However, I want to perform refreshing sequentially at the adjacent places. The present invention is to provide continuously changing addresses so as to generate applied addresses capable of sequentially accessing adjacent locations.

"Means for Solving the Problem" In the present invention, a refresh address generator that generates sequentially stepped addresses is used, and a bit replacement circuit is provided between the refresh address generator and the selection circuit. This bit exchange circuit makes it possible to sequentially access adjacent places.

[Embodiment] FIG. 1 shows an embodiment of the present invention, in which parts corresponding to those in FIG. In this embodiment, the upper 6 bits RF6 to RF11 of the refresh address from the refresh address generator 13 are supplied to the bit exchange circuit 21. Bit exchange circuit 21 has 6 inputs 1 as shown in FIG.
Six output multiplexers are used, and 6-bit RF6 to 11 are supplied as the 6 inputs of each of the 6 multiplexers, and one of the 6 inputs is selected and output by each one multiplexer. In other words, 6-bit RF6-11
Any one bit of can be selected and taken out. 6-bit RF consisting of 1 bit for each of the 6 multiplexers taken out
X6 to 11 can be obtained by exchanging the bit positions of 6-bit RF6 to 11. The bit exchange setting is made by the contents of the address select register 22.

The addresses RFX6 to 11 whose bits have been replaced in this way
Is supplied to the selection circuit 12, and when the refresh enable is applied, this is selected and becomes the applied addresses M6 to 11.

In the above description, the upper 6 bits of the refresh address RF6
Bit replacement was performed only for ~ 11, but all bits RF
Bit replacement may be performed for 0 to 11.

[Advantage of Device] As described above, in this device, the bit positions of the consecutive refresh addresses are interchanged arbitrarily. Therefore, by selecting the interchange, the applied addresses M0 to 11 are adjacent to the RAM. The locations can be accessed sequentially.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a concrete example of the bit replacing circuit, and FIG. 3 is a block diagram showing a conventional address applying device.

Claims (1)

[Scope of utility model registration request] 1. An address applying device of a semiconductor test device for selecting a test address and a refresh address from a refresh address generator by a selection circuit and supplying the refresh address to a dynamic RAM under test. An address applying device for a semiconductor test device, which is for generating an address, wherein a bit replacement circuit is provided between the refresh address generator and the selection circuit.