JPH0732256B2 - Method of manufacturing thin film transistor - Google Patents

Description

DETAILED DESCRIPTION [Overview] To improve the ON / OFF ratio of an inverted staggered thin film transistor, the amount of diborane added to silane is gradually increased when forming an amorphous silicon layer by plasma enhanced chemical vapor deposition. A method of gradually changing the conductivity type of the amorphous silicon layer from the electron conductivity type to the intrinsic conductivity type by forming the amorphous silicon layer.

[Industrial application field]

The present invention relates to a method for manufacturing a thin film transistor with reduced OFF current.

A thin film transistor (abbreviated as TFT) is formed from amorphous silicon (abbreviated as a-Si) on an insulating substrate such as glass by using a thin film forming technique such as plasma chemical vapor deposition (abbreviated as P-CVD) or vacuum deposition. Forming a semiconductor layer, an insulating layer such as silicon nitride or silicon dioxide, or a metal layer,
It is made by combining this with a photo-etching technique (photolithography) to selectively etch a fine pattern.

Since a transistor array can be formed over a large area by using such a technique, the TFT is used as a switching element in an active matrix type liquid crystal display panel or an electroluminescence (abbreviated as EL) display panel.

In such applications, each transistor must be defect-free and have an excellent ON / OFF ratio.

[Conventional technology]

Inverted staggered type is often used for TFTs used in active matrix type liquid crystal display panels and EL display panels.

Figure 2 shows the cross-sectional structure of an inverted staggered TFT.
The manufacturing method will be briefly described as follows.

Chrome (Cr) is formed on the glass substrate 1 by a vacuum deposition method to a thickness of about 1000Å, and the gate electrode 2 is patterned by using a photo-etching technique.

Next, the silicon nitride layer (SiN layer) is deposited to about 3000 Å using the P-CVD method.
And the gate insulating layer 3 is formed.

Next, a P-CVD method is used to form an a-Si layer on the surface of about 1000.
After the semiconductor layer 4 is formed to a thickness of Å, a silicon dioxide (SiO ₂ ) layer is also formed thereon by the P-CVD method in the same manner as about 1000 Å.
To be the channel protective layer 5.

Next, a resist pattern is formed immediately above the gate electrode 2, and the SiO ₂ layer is removed by chemical etching to leave only the channel protection layer 5, and then the P-CV film is left as it is.
The contact layer 6 is formed by forming an n + a.Si layer with a thickness of about 500Å by the D method.

Next, after forming aluminum (Al) to a thickness of about 1000 Å by a vacuum evaporation method on this, the resist on the channel protective layer 5 is dissolved and removed.

Next, the drain electrode 7 and the source electrode 8 are formed by coating the resist only on the TFT formation region, and using the mask as a mask to sequentially etch the Al layer, the n + a-Si layer, the a-Si layer, and the SiN layer to perform element isolation. An inverted staggered TFT with a top is formed.

In such a staggered TFT, in the ON state, current flows between the source electrode 8 and the drain electrode 7 through the semiconductor layer 4 formed on the gate electrode 2, but reacts with silane (SiH ₄ ). The a-Si layer formed by plasma decomposition as gas is a semiconductor of n type conductivity until then, so the resistance between the electrodes is not sufficiently high even in the OFF state, which causes ON / OFF. Since the ratio can be only about 6 to 7 digits, this improvement has been demanded.

[Problems to be solved by the invention]

As described above, the conventional TFT has a problem that the ON / OFF ratio is not high during switching because the OFF current is not sufficiently small.

[Means for solving problems]

The above problem is that in the manufacturing process of the inverted staggered TFT, when the a-Si layer is formed by the P-CVD method, the amount of diborane added to the silane is gradually increased to initially change the conductivity type of the a-Si layer. This can be solved by adopting a manufacturing method of a TFT, which is formed by gradually changing from the electronic conductivity type to the intrinsic conductivity type.

[Action]

The present invention is realized by increasing the resistance of the semiconductor layer 4 on the side close to the channel protection layer 5 as a method of reducing the OFF current while keeping the ON current as it is.

That is, when a voltage is applied between the gate electrode 2 and ground, a channel is formed in the semiconductor layer 4 and the drain electrode 7 and the source electrode 8 are turned on, while when no voltage is applied to the gate electrode, it is turned off. But silane (SiH ₄ )
Since the a-Si semiconductor layer obtained by the plasma decomposition of (1) originally has a slight n-type conductivity, the OFF current cannot be made sufficiently low.

Therefore, the present invention is to introduce a trivalent element little by little into SiH ₄ when the semiconductor layer 4 is formed by the P-CVD method so that the semiconductor layer 4 becomes an intrinsic conductivity type when the layer formation is completed. .

That is, by supplying SiH ₄ as a reaction gas to the P-CVD apparatus, P
-Start the addition of diborane (B ₂ H ₆ ) from the stage where CVD is performed to grow to about 1/2 of the planned film thickness and gradually increase this amount to increase the resistivity of the a-Si layer grown. The final conductor is an intrinsic conductor.

By doing so, the current value when the TFT is turned off is determined by the resistance of the semiconductor layer 4 in contact with the channel protection layer 5.
A reduction in OFF current is realized.

〔Example〕

In manufacturing an inverted staggered TFT, until now, the semiconductor layer has been formed by setting the substrate to be processed on which the gate insulating layer 3 has been formed in a P-CVD device and using hydrogen (H ₂ ) gas as a carrier.
H ₄ concentration of 10%, flow rate of 200 (SCCM Standard Cubic C
It was adjusted to entimeter).

Therefore, in the present invention, when the a-Si has grown to a film thickness of about 500Å, which is half the expected film thickness of 1000Å, the concentration of 0.01
% B ₂ H ₆ introduction was started, and the flow rate was 0.01 SCCM at the final stage.

By doing so, the amount of B ₂ H ₆ added to SiH _{4 in the} final stage is 0.5 ppm, and a-Si becomes an intrinsic conductivity type.

FIG. 1 is an embodiment showing the relationship between the amount of SiH ₄ and B ₂ H ₆ added with respect to the treatment time. The horizontal axis represents the plasma CVD treatment time, and the vertical axis represents the SiH ₄ flow rate and B. The flow rate of ₂ H ₆ is shown.

It has an a-Si layer with a thickness of 1000Å formed in this way,
Gate length 10 [mu] m, were measured ON current and OFF current 10V to the gate electrode for TFT gate width 200 [mu], a voltage of 10V to the drain electrode is applied, but ON current is not different from 10 ^-5 A and the conventional The OFF current was 10 ^-13 A, which was two orders of magnitude higher than the conventional 10 ^-11 A.

As described above, by implementing the present invention, the ON / OFF ratio could be improved to 8 digits.

〔The invention's effect〕

As described above, by implementing the present invention, the OFF current can be reduced and the quality of the TFT can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an explanatory view showing conditions for forming an a-Si semiconductor layer, and FIG. 2 is a sectional structure view of an inverted staggered TFT. In the figure, 2 is a gate electrode, 4 is a semiconductor layer, 5 is a channel protective layer,
6 is a contact layer, 7 is a drain electrode, 8 is a source electrode,

Claims (1)

[Claims] 1. In the manufacturing process of an inverted staggered thin film transistor, when an amorphous silicon layer is formed by plasma enhanced chemical vapor deposition, the amount of diborane added to silane is gradually increased to increase the conductivity of the amorphous silicon layer. A method of manufacturing a thin film transistor, which is formed by gradually changing a shape from an original electronic conductivity type to an intrinsic conductivity type.