JPH0777232B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0777232B2 JPH0777232B2 JP61238453A JP23845386A JPH0777232B2 JP H0777232 B2 JPH0777232 B2 JP H0777232B2 JP 61238453 A JP61238453 A JP 61238453A JP 23845386 A JP23845386 A JP 23845386A JP H0777232 B2 JPH0777232 B2 JP H0777232B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- bpsg
- semiconductor device
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 33
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 20
- 238000000926 separation method Methods 0.000 claims description 9
- 238000009792 diffusion process Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 15
- 238000000034 method Methods 0.000 description 9
- 230000005855 radiation Effects 0.000 description 9
- 239000011347 resin Substances 0.000 description 8
- 229920005989 resin Polymers 0.000 description 8
- 239000012535 impurity Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Element Separation (AREA)
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に人工衛星搭載用等強い
放射線をうける環境での使用に適する、放射線に強い半
導体装置に関する。The present invention relates to a semiconductor device, and more particularly to a radiation-resistant semiconductor device suitable for use in an environment where it is exposed to strong radiation such as for mounting on an artificial satellite.
強い放射線をうけた半導体装置は電子・正孔対の発生等
により動作状態に変化が生じる。A semiconductor device that receives strong radiation changes its operating state due to generation of electron-hole pairs.
変化を最小限に抑えるには熱酸化膜の代りにCVD(chemi
cal vapor deposition)法を用いた絶縁膜、特にBPSG
(boro−phospho−silicate glass)膜の使用が有効で
あり、従来の耐放射線半導体装置の絶縁分離膜は第3図
に示した通り、半導体基板41上に熱酸化膜42を形成した
後、CVD法によって形成したBPSG膜43の不要部分をエッ
チング除去し、BPSG膜43を高温リフローして作られる構
造になっていた。To minimize the change, CVD (chemi
Insulating film using cal vapor deposition), especially BPSG
It is effective to use a (boro-phospho-silicate glass) film, and the insulation isolation film of the conventional radiation resistant semiconductor device is formed by forming a thermal oxide film 42 on a semiconductor substrate 41 and then using a CVD film as shown in FIG. The BPSG film 43 has a structure formed by removing unnecessary parts of the BPSG film 43 by etching and reflowing the BPSG film 43 at a high temperature.
また、第3図におけるBPSG膜43のエッチングの制御を容
易にするため、第4図に示した様な構造も用いられてい
た。この構造を作るには半導体基板51上に熱酸化膜52を
形成した後、多結晶シリコン膜53を積層し、さらにBPSG
膜54を形成する。次に、BPSG膜54の不要部分を多結晶シ
リコン膜53が露出するまでエッチングするが、この際多
結晶シリコン膜53がエッチングのストッパーとして働く
ため、エッチング除去残りや半導体基板表面への損傷を
防止することが可能となる。BPSG膜54のエッチング後、
多結晶シリコン膜53を等方性エッチング除去し、BPSG膜
54を高温リフローして絶縁分離膜が得られる。Further, in order to facilitate the control of the etching of the BPSG film 43 in FIG. 3, the structure as shown in FIG. 4 was also used. To make this structure, a thermal oxide film 52 is formed on a semiconductor substrate 51, a polycrystalline silicon film 53 is laminated, and then BPSG is added.
The film 54 is formed. Next, the unnecessary portion of the BPSG film 54 is etched until the polycrystalline silicon film 53 is exposed. At this time, since the polycrystalline silicon film 53 acts as an etching stopper, etching removal residue and damage to the semiconductor substrate surface are prevented. It becomes possible to do. After etching the BPSG film 54,
The polycrystalline silicon film 53 is isotropically removed by etching to remove the BPSG film.
54 is reflowed at a high temperature to obtain an insulating separation film.
上述した従来の半導体装置は、その絶縁分離膜の構造
が、半導体基板上の熱酸化膜を薄くした代りに、耐放射
線特製の優れたBPSG膜を用いて放射線の影響を最小限に
抑えるようになっており、従って、半導体基板上の熱酸
化膜をできるだけ薄くする必要があるため、熱処理時に
BPSG膜からのリン,ボロン等の不純物の拡散を抑えるこ
とができず、これらの不純物が半導体基板中に拡散し、
絶縁分離膜としての効果がなくなり、MOSトランジスタ
のしきい電圧が変動する等の欠点がある。In the conventional semiconductor device described above, the structure of the insulating separation film is such that, instead of thinning the thermal oxide film on the semiconductor substrate, the effect of radiation is minimized by using a superior BPSG film with special radiation resistance. Therefore, it is necessary to make the thermal oxide film on the semiconductor substrate as thin as possible.
It is not possible to suppress the diffusion of impurities such as phosphorus and boron from the BPSG film, and these impurities diffuse into the semiconductor substrate,
There is a defect that the effect as an insulating separation film is lost and the threshold voltage of the MOS transistor changes.
上述した従来の半導体装置に対し、本発明は半導体基板
上の熱酸化膜を薄くすることによって放射線が半導体装
置に与えを影響を減らし、かつ、熱酸化膜上に耐放射線
特性が、BPSG膜よりは劣るものの、熱酸化膜より優れた
CVD酸化膜を積層することにより、絶縁分離用BPSG膜の
高温リフローの際に生じる半導体基板内への不純物拡散
を防止することが可能であるという独創的内容を有す
る。In contrast to the conventional semiconductor device described above, the present invention reduces the influence of radiation on the semiconductor device by thinning the thermal oxide film on the semiconductor substrate, and the radiation resistance characteristics on the thermal oxide film are better than those of the BPSG film. Is inferior, but better than thermal oxide film
It has an original content that it is possible to prevent the impurity diffusion into the semiconductor substrate which occurs during the high temperature reflow of the insulating BPSG film by stacking the CVD oxide films.
本発明の半導体装置は、半導体基板上にフィールド絶縁
分離膜を形成し、このフィールド絶縁分離膜を形成した
領域以外の領域にN型またはP型の拡散層を形成した半
導体装置において、前記フィールド絶縁分離膜を厚さ30
0Å以下の熱酸化膜と、CVD酸化膜と、BPSG膜との3層の
膜から形成し、これら3層の膜を同一形状にパターニン
グして構成される。The semiconductor device of the present invention is a semiconductor device in which a field insulating separation film is formed on a semiconductor substrate, and an N-type or P-type diffusion layer is formed in a region other than the region where the field insulating separation film is formed. Separation membrane thickness 30
A thermal oxide film of 0 Å or less, a CVD oxide film, and a BPSG film are formed of three layers, and these three layers are patterned into the same shape.
次に本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第1図(a)は本発明の第一の実施例の縦断面図であ
る。図において、1は半導体基板、2は熱酸化法によっ
て形成したシリコン酸化膜(以下熱酸化膜という)、3
はCVD法によって形成したシリコン酸化膜(以下CVD酸化
膜という)、4はCVD法によって形成したBPSG膜、6は
ゲート用の多結晶シリコン膜、7・8はP型もしくはN
型の不純物を拡散することによって形成したソース領域
およびドレイン領域、9はシリコン酸化膜等の絶縁膜、
10はソース・ドレイン・ゲートのコンタクト部に形成し
た電極用金属膜、11はPSG膜等で形成した半導体装置表
面の保護膜である。FIG. 1 (a) is a longitudinal sectional view of the first embodiment of the present invention. In the figure, 1 is a semiconductor substrate, 2 is a silicon oxide film formed by a thermal oxidation method (hereinafter referred to as a thermal oxide film), 3
Is a silicon oxide film formed by a CVD method (hereinafter referred to as a CVD oxide film), 4 is a BPSG film formed by a CVD method, 6 is a polycrystalline silicon film for a gate, and 7 and 8 are P-type or N-type.
Source and drain regions formed by diffusing a type impurity, 9 is an insulating film such as a silicon oxide film,
Reference numeral 10 is a metal film for electrodes formed on the contact portions of the source / drain / gate, and 11 is a protective film formed on the surface of the semiconductor device, such as a PSG film.
次に、第1図(a)に示す実施例を製造方法により、第
1図(b)〜(g)を参照して詳細に説明する。Next, the embodiment shown in FIG. 1 (a) will be described in detail by a manufacturing method with reference to FIGS. 1 (b) to (g).
第1図(b)は、半導体基板1の一表面に熱酸化法によ
って熱酸化膜2を50〜300Åに設け、次にCVD法によって
CVD酸化膜3を500〜1500Åの厚さに形成し、BPSG膜4を
CVD法により3000〜6000Åの厚さに積層後、感光性樹脂
5をスピンナ法等によって塗布する工程を示している。In FIG. 1 (b), a thermal oxide film 2 is formed on one surface of a semiconductor substrate 1 by a thermal oxidation method to a thickness of 50 to 300 Å, then by a CVD method
The CVD oxide film 3 is formed to a thickness of 500 to 1500Å, and the BPSG film 4 is formed.
It shows a process in which the photosensitive resin 5 is applied by a spinner method or the like after being laminated to a thickness of 3000 to 6000Å by the CVD method.
次に、絶縁分離領域に相当する部分を残した感光性樹脂
5をマスクとしてBPSG膜4およびCVD酸化膜3をエッチ
ング除去する工程を第1図(c)に示す。このとき、エ
ッチング後に残ったCVD酸化膜3の膜厚が熱酸化膜2と
共にBPSG膜4の高温リフローの際に生じる不純物拡散を
防止するのに十分な厚さとなるようにCVD酸化膜3のエ
ッチング量を調節する。Next, FIG. 1 (c) shows a step of etching away the BPSG film 4 and the CVD oxide film 3 using the photosensitive resin 5 that leaves a portion corresponding to the insulating isolation region as a mask. At this time, etching of the CVD oxide film 3 is performed so that the film thickness of the CVD oxide film 3 remaining after the etching is sufficient to prevent impurity diffusion that occurs during high temperature reflow of the BPSG film 4 together with the thermal oxide film 2. Adjust the amount.
第1図(d)に、マスク用の感光性樹脂5を除去した
後、BPSG膜4を高温の熱処理でリフローし、このパター
ニングされたBPSG膜4をマスクとして、CVD酸化膜3お
よび熱酸化膜2を半導体基板1の表面が露出するまでエ
ッチング除去する工程を示す。In FIG. 1 (d), after removing the photosensitive resin 5 for the mask, the BPSG film 4 is reflowed by a high temperature heat treatment, and the patterned BPSG film 4 is used as a mask to form the CVD oxide film 3 and the thermal oxide film. A step of etching and removing 2 until the surface of the semiconductor substrate 1 is exposed is shown.
次に、ゲート酸化膜となるシリコン酸化膜を熱酸化法に
よって形成した後、ゲート用の多結晶シリコン膜6を形
成する。(第1図(e))。Next, after forming a silicon oxide film to be a gate oxide film by a thermal oxidation method, a polycrystalline silicon film 6 for a gate is formed. (FIG. 1 (e)).
第1図(f)に、感光性樹脂を用いてゲート用の多結晶
シリコン膜6の不要部分をエッチング除去した後に、P
型もしくはN型の不純物を拡散することによりソース領
域7およびドレイン領域8を形成する工程を示す。In FIG. 1 (f), after removing an unnecessary portion of the gate polycrystalline silicon film 6 by etching using a photosensitive resin, P
A process of forming the source region 7 and the drain region 8 by diffusing a type or N type impurity is shown.
次に、シリコン酸化膜等の絶縁膜9をCVD法によって形
成し、ソース,ドレイン,ゲートのコンタクト部を感光
性樹脂のマスクを用いてエッチング除去する(第1図
(g))。Next, an insulating film 9 such as a silicon oxide film is formed by the CVD method, and the contact portions of the source, drain and gate are removed by etching using a mask of photosensitive resin (FIG. 1 (g)).
ついで、電極用金属膜10の形成とパターニングを公知の
方法によって行ない、表面に保護膜11を形成することに
よって第1図(a)に示す実施例が得られる。Then, the metal film 10 for electrodes is formed and patterned by a known method, and the protective film 11 is formed on the surface to obtain the embodiment shown in FIG. 1 (a).
第2図(a)は本発明の第二の実施例の縦断面図であ
る。図において、21は半導体基板、22は熱酸化膜、23は
CVD酸化膜、24はBPSG膜のエッチングの際にストッパー
として用いる多結晶シリコン膜、25はCVD法によって形
成したBPSG膜、27はゲート用の多結晶シリコン膜、28・
29はソース領域およびドレイン領域、30はシリコン酸化
膜等の絶縁膜、31はソース・ドレイン・ゲートのコンタ
クト部に形成した電極用金属膜、32は表面の保護膜であ
る。FIG. 2 (a) is a vertical sectional view of the second embodiment of the present invention. In the figure, 21 is a semiconductor substrate, 22 is a thermal oxide film, and 23 is
CVD oxide film, 24 is a polycrystalline silicon film used as a stopper during etching of the BPSG film, 25 is a BPSG film formed by a CVD method, 27 is a polycrystalline silicon film for a gate, 28.
Reference numeral 29 is a source region and drain region, 30 is an insulating film such as a silicon oxide film, 31 is an electrode metal film formed at the source / drain / gate contact portions, and 32 is a surface protective film.
次に、第2図(a)に示す実施例を製造方法により、第
2図(b)〜(e)を参照して詳細に説明する。Next, the embodiment shown in FIG. 2A will be described in detail with reference to FIGS. 2B to 2E by the manufacturing method.
第2図(b)は、前述の第1図(a)に示す実施例にお
けると同様に半導体基板21上に熱酸化膜22とCVD酸化膜2
3を形成した後、多結晶シリコン膜24を500〜2000Åの厚
さに形成し、さらにBPSG膜25を積層後、感光性樹脂26を
塗布する工程を示している。FIG. 2B shows the thermal oxide film 22 and the CVD oxide film 2 on the semiconductor substrate 21 as in the embodiment shown in FIG.
After forming 3, the polycrystalline silicon film 24 is formed to a thickness of 500 to 2000Å, the BPSG film 25 is further laminated, and then the photosensitive resin 26 is applied.
第2図(c)に、絶縁分離領域に相当する部分を残した
感光性樹脂26をマスクとしてBPSG膜25を多結晶シリコン
膜24が露出するまでエッチングする工程を示す。このと
き、BPSG膜25の下にエッチングのストッパとなるべき多
結晶シリコン膜24が存在するため、前述の実施例で問題
となる下地基板の損傷等を生ずることなく、BPSG膜25の
エッチングを容易に行なうことができる。FIG. 2C shows a process of etching the BPSG film 25 until the polycrystalline silicon film 24 is exposed, using the photosensitive resin 26 that leaves a portion corresponding to the insulation isolation region as a mask. At this time, since the polycrystalline silicon film 24 to serve as an etching stopper is present under the BPSG film 25, the BPSG film 25 can be easily etched without causing damage to the underlying substrate, which is a problem in the above-described embodiment. Can be done
次に、多結晶シリコン膜24を等方性エッチング除去した
後、感光性樹脂26を除去する工程を第2図(d)に示
す。Next, FIG. 2D shows a step of removing the photosensitive resin 26 after the polycrystalline silicon film 24 is removed by isotropic etching.
第2図(e)に、BPSG膜25を高温の熱処理でリフローし
た後、このパターニングされたBPSG膜25をマスクとして
CVD酸化膜23と熱酸化膜22を半導体基板21の表面が現れ
るまでエッチング除去する工程を示す。In FIG. 2 (e), after the BPSG film 25 is reflowed by a high temperature heat treatment, the patterned BPSG film 25 is used as a mask.
A process of etching and removing the CVD oxide film 23 and the thermal oxide film 22 until the surface of the semiconductor substrate 21 appears.
ついで、前述の第1図(a)に示す実施例におけると同
様にしてゲート用の多結晶シリコン膜27、電極用金属膜
31等を形成することによって第2図(a)に示す実施例
が得られる。Then, in the same manner as in the embodiment shown in FIG. 1A, the polycrystalline silicon film 27 for the gate and the metal film for the electrode are formed.
By forming 31 etc., the embodiment shown in FIG. 2 (a) is obtained.
以上説明したように本発明は、絶縁分離領域の半導体基
板上に薄い熱酸化膜を形成した後にCVD酸化膜を形成
し、さらにBPSG膜を積層することにより、半導体装置の
耐放射線特性を保持したまま、絶縁分離用のBPSG膜の高
温リフローの際に生じる不純物拡散が基板へ達するのを
防ぐことができる効果がある。As described above, the present invention maintains the radiation resistance of the semiconductor device by forming a CVD oxide film after forming a thin thermal oxide film on the semiconductor substrate in the isolation region and further stacking a BPSG film. As it is, there is an effect that it is possible to prevent the impurity diffusion generated during the high temperature reflow of the BPSG film for insulation separation from reaching the substrate.
第1図(a)は本発明の第一の実施例の縦断面図、第1
図(b)〜(g)は第1図(a)に示す実施例の製造工
程を示す断面図、第2図(a)は本発明の第二の実施例
の縦断面図、第2図(b)〜(e)は第2図(a)に示
す実施例の製造工程を示す断面図、第3図・第4図は従
来の半導体装置の二つの例のそれぞれの断面図である。 1・21……半導体基板、2・22……熱酸化膜、3・23…
…CVD酸化膜、4・25……BPSG膜、6・24・27……多結
晶シリコン膜、7・28……ソース領域、8・29……ドレ
イン領域、9・30……絶縁膜、10・31……電極用金属
膜。FIG. 1 (a) is a longitudinal sectional view of the first embodiment of the present invention,
FIGS. 2 (b) to 2 (g) are sectional views showing the manufacturing process of the embodiment shown in FIG. 1 (a), and FIG. 2 (a) is a longitudinal sectional view of the second embodiment of the present invention. 2B to 2E are cross-sectional views showing the manufacturing process of the embodiment shown in FIG. 2A, and FIGS. 3 and 4 are cross-sectional views of two conventional semiconductor devices. 1.21 ... Semiconductor substrate, 2.22 ... thermal oxide film, 3.23 ...
... CVD oxide film, 4.25 ... BPSG film, 6.24.27 ... Polycrystalline silicon film, 7.28 ... Source region, 8.29 ... Drain region, 9.30 ... Insulating film, 10・ 31 …… Metallic film for electrodes.
Claims (1)
成し、このフィールド絶縁分離膜を形成した領域以外の
領域にN型またはP型の拡散層を形成した半導体装置に
おいて、前記フィールド絶縁分離膜を厚さ300Å以下の
熱酸化膜と、CVD酸化膜と、BPSG膜との3層の膜から形
成し、これら3層の膜を同一形状にパターニングしたこ
とを特徴とする半導体装置。1. A semiconductor device in which a field insulating separation film is formed on a semiconductor substrate, and an N-type or P-type diffusion layer is formed in a region other than the region in which the field insulating separation film is formed. A semiconductor device in which a thermal oxide film having a thickness of 300 Å or less, a CVD oxide film, and a BPSG film are formed in three layers, and these three layers are patterned into the same shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61238453A JPH0777232B2 (en) | 1986-10-06 | 1986-10-06 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61238453A JPH0777232B2 (en) | 1986-10-06 | 1986-10-06 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6392028A JPS6392028A (en) | 1988-04-22 |
| JPH0777232B2 true JPH0777232B2 (en) | 1995-08-16 |
Family
ID=17030446
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61238453A Expired - Lifetime JPH0777232B2 (en) | 1986-10-06 | 1986-10-06 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0777232B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04215432A (en) * | 1990-12-14 | 1992-08-06 | Mitsubishi Electric Corp | Microfabrication method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5324289A (en) * | 1976-08-19 | 1978-03-06 | Toshiba Corp | Production of semiconductor device |
| JPS566452A (en) * | 1979-06-27 | 1981-01-23 | Toshiba Corp | Production of semiconductor device |
| JPS59155127A (en) * | 1983-02-24 | 1984-09-04 | Toshiba Corp | Manufacture of semiconductor device |
-
1986
- 1986-10-06 JP JP61238453A patent/JPH0777232B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6392028A (en) | 1988-04-22 |
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