JPH0818033A - Negative differential resistance FET - Google Patents

Abstract

(57) [Abstract] [Purpose] To improve the electron mobility in the channel of a negative differential resistance FET to enable higher speed operation. [Structure] A buffer layer (2), a channel layer (3), an electron supply layer (4), a gate electrode (5), and first and second cap layers 6-1 and 6-2 sandwiching the gate electrode. The quantum well structure 9 in which an electron subband is generated is stacked on the second cap layer 6-2 of the selectively doped FET. By setting the impurity concentration in the cap layer to 1 × 10 ¹⁸ / cm ³ or more, the contact resistivity between the cap layer and the channel is set to 1
It can be reduced to the level of 0 ^-7 Ωcm ² , and ohmic contact can be realized without providing an alloy region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor (hereinafter abbreviated as FET), and more particularly to a negative differential resistance (negative differential resistance) based on a resonance tunnel effect.
neutral resistance (hereinafter referred to as NDR)).

[0002]

2. Description of the Related Art FIG. 7 is a sectional view showing a main part of a conventional negative differential resistance FET. Such FETs, for example,
By AR Bonnefoi et al., IEEE Electron Device Letters.
ers), EDL-6, p. 636, 1985.

In the figure, 201 is a semi-insulating GaAs substrate, 203 is an N-type GaAs layer constituting a channel layer, 2
08 is GaAs / Al _u Ga _1-u As / GaAs / Al
quantum well structure having a _u Ga _1-u As / GaAs double barrier 209 is an N-type GaAs layer constituting the contact layer. A source electrode 210 is formed on the N-type GaAs layer 209.
However, a drain electrode 207 is formed by vapor deposition on the surface 203S of the channel layer exposed by etching away the contact layer (N-type GaAs layer 209) and part of the quantum well structure 208. There is. Further, the gate electrode 2 is sandwiched between the quantum well structure 208 and the drain electrode 207 on the surface 203S of the channel layer.
05 is formed by vapor deposition.

[0004] FET having a quantum well structure in this way the source region, based on the resonant tunneling effect in quantum well structure, the drain current (I _d) - caused an NDR to the gate voltage (V _gs) characteristics, like this Attention has been paid to the fact that by utilizing the characteristics, a frequency multiplier circuit, a flip-flop circuit, and various logic operation circuits can be realized with a very small number of elements.

[0005]

The conventional negative differential resistance F
The ET had a configuration in which a MESFET and a resonance tunnel diode were joined. In such a structure, the carriers in the channel travel in the N-type semiconductor layer having low electron mobility, so that the average carrier velocity is low and the channel delay time increases. Therefore, it is difficult to improve the cutoff frequency and the power gain, and there is a problem that sufficient characteristics cannot be obtained when such an FET is applied to a high speed digital circuit, a microwave or a millimeter wave circuit.

An object of the present invention is to improve electron mobility in a channel of a negative differential resistance FET having a quantum well structure in a source region, thereby enabling higher speed operation.

[0007]

A first negative differential resistance FET of the present invention comprises a buffer layer, a channel layer and an electron supply layer, which are sequentially laminated on one main surface of a semiconductor substrate, and an electron supply layer. A Schottky junction gate electrode and an N-type impurity concentration of at least 1 × 10 ¹⁸ / cm ³ , preferably at least 5 × 10 ¹⁸ / cm ³ , which is provided on the surface of the electron supply layer with the gate electrode interposed therebetween. A selectively doped FET having a first cap layer and a second cap layer, and a drain electrode in ohmic contact with the first cap layer, and an electron subband provided to cover the second cap layer Resonant tunnel diode having a quantum well structure, a contact layer laminated on the quantum well structure, and a source electrode in ohmic contact with the contact layer Is that Ranaru. In this case, it is preferable that the electron affinity of the supply layer increases from the channel layer side to the first cap layer and the second cap layer side.

Further, the second negative differential resistance FET of the present invention
Is a buffer layer, an electron supply layer, and a channel layer that are sequentially stacked on one main surface of a semiconductor substrate, a gate electrode that makes a Schottky junction with the channel layer, and a gate electrode that is provided on the channel layer surface with the gate electrode interposed therebetween. A selectively doped FET having a first cap layer and a second cap layer provided therein and a drain electrode in ohmic contact with the first cap layer, and an electron sub-layer provided to cover the second cap layer. The resonant tunnel diode has a quantum well structure having a band, a contact layer laminated on the quantum well structure, and a source electrode in ohmic contact with the contact layer. In this case, it is preferable that the electron affinity of the channel layer decreases from the electron supply layer side to the first cap layer and the second cap layer side.

[0009]

The speed of the negative differential resistance FET can be increased since the selective doping FET and the resonant tunneling diode which operate at high speed are connected.

In the first negative differential resistance FET of the present invention, the first
Since the N-type impurity concentration of the cap layer and the second cap layer is at least 1 × 10 ¹⁸ / cm ³ , the first and second cap layers and the electron storage layer (in the vicinity of the electron supply layer interface in the channel layer). (Formed) is mainly governed by tunnel conduction and ohmic contact can be realized. When the electron affinity of the electron supply layer is increased toward the first and second cap layers, the ohmic contact is further improved because there is no conduction band barrier between the electron supply layer and these cap layers. become.

In the second negative differential resistance FET, the first and second
Since there is no high-resistance electron supply layer between the cap layer and the channel layer, it is unnecessary to limit the N-type impurity concentration of the first and second cap layers. If the electron affinity of the channel layer is reduced toward the first and second cap layers, a conduction band barrier can be prevented from being present between the channel layer and these cap layers.

[0012]

FIG. 1A is a sectional view showing a main part of a first embodiment of the present invention, and FIG. 1B is an enlarged view of a part A in FIG. 1A.

This embodiment uses a semi-insulating GaAs substrate 1
An undoped GaAs layer 2 (buffer layer) and an undoped In _x Ga layer sequentially stacked on one main surface of a (semiconductor substrate)
_1-x As layer 3 (channel layer) and N-type Al _y Ga _1-y
An As layer 4 (electron supply layer), a gate electrode 5 that forms a Schottky junction with the electron supply layer (4), and 5 × 10 ¹⁸ / provided on the surface of the electron supply layer (4) with the gate electrode 5 interposed therebetween.
a first cap layer 6-1 and a second cap layer 6-2 made of an N-type GaAs layer containing an N-type impurity concentration of ³ cm ³ ;
And a drain electrode 7 (made of AuGe / Ni / Au) in ohmic contact with the first cap layer 6-1 and the second cap layer 6
-2, a quantum well structure 8 having a subband of electrons, a contact layer 9 laminated on the quantum well structure 8, and a source electrode 10 (AuGe / Ni / Au) in ohmic contact with the contact layer 9. ). Near the interface between the channel layer (3) and the electron supply layer (4), an electron storage layer (not shown) in which the two-dimensional electron gas E is stored is induced.

FIG. 2 shows the distribution of the InAs composition ratio x and the AlAs composition ratio y of each semiconductor layer in a direction perpendicular to the substrate surface in this embodiment. In this example, undoped InGa
_The InAs composition ratio x in the _1-y As layer 3 is 0.25, and the AlAs composition ratio y in the Al _y Ga _1-y As layer 4 is
Is 0.15.

Such an FET is manufactured as follows. An undoped GaAs layer 2 having a thickness of 1 μm and a thickness of 1 μm are formed on the (100) plane of the semi-insulating GaAs substrate 1 by, for example, a molecular beam epitaxial (hereinafter referred to as MBE) growth method.
0 nm undoped In _0.25 Ga _0.75 As layer 3, thickness 3
0 nm, N-type Al _0.15 Ga _0.85 As layer 4 doped with Si as an impurity at a concentration of 2 × 10 ¹⁸ / cm ³ , thickness of 50 nm, and Si as an impurity at a concentration of 5 × 10 ¹⁸ / cm ³
A N-type doped GaAs layer is deposited. Next, an undoped GaAs layer 8a1 having a thickness of 10 nm (first
Undoped AlAs layer 8 having a thickness of 3 nm
b1 (first barrier layer), 5 nm thick undoped GaA
s layer 8c (quantum well layer), undoped Al 3 nm thick
An As layer 8b2 (second barrier layer) and an undoped GaAs layer 8a2 (second spacer layer) having a thickness of 10 nm
The quantum well structure 8 is formed by deposition by the BE method. Next, an N-type GaAs layer 9 with a thickness of 50 nm doped with Si at a concentration of 5 × 10 ¹⁸ / cm ³ as an impurity is formed.

Here, although In _x Ga _{1 -x} As and GaAs have different lattice constants, undoped In _0.25 Ga _0.75 As
The layer 3 is made to have a critical thickness (about 12 n) at which misfit dislocations occur.
By setting the value to m) or less, the elastic strain becomes a strain lattice layer that alleviates lattice irregularities, and a good interface is formed.

Next, the contact layer (9) and a part of the quantum well structure 8 are removed by etching to expose the cap layer surface 6S. On the contact layer 9, the source electrode 1
After the drain electrode 7 is formed on the cap layer surface 6S by vapor deposition, the source electrode 1 is formed by ordinary alloying.
Ohmic contacts are made between the contact layer 9 and the contact layer 9 and between the drain electrode 7 and the cap layer 6-1. This alloy processing does not destroy the quantum well structure 8. Further, the cap layer 4
The surface 4S of the electron supply layer (4) exposed by etching away a part of the region sandwiched by the quantum well structure 8 and the drain electrode 7 is exposed by, for example, an electron beam (hereinafter referred to as EB) exposure method. The gate electrode 5 is formed by depositing a gate metal using the formed resist pattern (not shown) as a mask. In this way,
The FET as shown in FIG. 1 is manufactured.

Here, the impurity concentration of the cap layer is 5 × 1
Since it is as high as 0 ¹⁸ / cm ³ , the first and second cap layers 6-
The contact resistivity between 1, 6-2 and the channel layer 3 is 10 ^-7 Ωc.
It can be reduced to about m ² . A cap layer / electron supply layer / channel layer heterojunction exists between the cap layer of the selectively doped FET and the electron storage layer in which the two-dimensional electron gas E is stored. The fact that electrons are transported mainly by tunnel conduction and that an alloy region does not need to be provided from the cap layer to the channel layer by setting it to 1 × 10 ¹⁸ / cm ³ or more means that, for example, IEE Electron Device Letters ( IEEE Electron Device
e Letters), EDL-8, 389-391, 1987. Also in the selectively doped FET of this embodiment, the quantum well structure is destroyed by setting the impurity concentration of the first and second cap layers to at least 1 × 10 ¹⁸ / cm ³ , preferably at least 5 × 10 ¹⁸ / cm ^3. The contact resistance with the channel layer could be reduced to about 10 ⁻⁷ Ω · cm ² without forming an alloy region. In the selectively doped FET, the sheet carrier concentration (impurity concentration × film thickness) in the cap layer is set to 5
× With 10 ¹² / cm ^2, it is JP-A can reduce the access resistance of the cap layer and the channel layers 2
As described in JP-A-12928, the sheet carrier concentration of the selectively doped FET of this embodiment is also at least 5 × 10 ¹² / cm ² , preferably at least 5 × 10 ¹² / cm ² .
By setting it to ¹³ / cm ² , the access resistance was sufficiently reduced.

This embodiment is similar to the prior art shown in FIG.
_d- V _gs characteristic has NDR. Further, while the conventional example uses an N-type semiconductor as the channel layer, the electron mobility is low. On the other hand, according to the present invention, the electron storage layer having a high electron mobility is used as the channel. High-speed operation becomes possible.

Next, a second embodiment will be described.

In FIG. 1, undoped In _x Ga _{1 -x} A
The In composition ratio x of the s layer 3 is 0.2, and the N-type Al _y Ga _1-y A
As shown in FIG. 3, the Al composition ratio y of the s layer was changed from the interface of the channel layer (3) to the interface of the cap layer.
From 0 to 0. The electron affinity of the electron supply layer (4) increases from the channel layer side to the cap layer side. Such a gradual change of x can be easily realized by the MBE method. Other than that, it is the same as the first embodiment.

In this embodiment, since the AlAs composition ratio at the interface between the electron supply layer 4 and the cap layer is 0, the interface is a homojunction, so that there is no conduction band barrier, and the gap between the cap layer and the channel layer is low. Has the advantage that the ohmic contact of the first embodiment can be obtained better than in the first embodiment.

Next, a third embodiment will be described.

FIG. 4 (a) is a sectional view showing the main part of the third embodiment, and FIG. 4 (b) is an enlarged view of part A of FIG. 4 (a).

In this embodiment, the semi-insulating GaAs substrate 10 is used.
Undoped Al _0.22 Ga _0.75 As layer 102 (buffer layer), N-type Al _y Ga _1-y As layer 104 (electron supply layer) and channel layer 103 (undoped) In _0.25 Ga _0.75 As layer 10
3a and an undoped GaAs layer 103b), and a gate electrode 105 (Ti
/ Al. ) And N-type Ga provided on the surface of the channel layer 103 with the gate electrode 105 interposed therebetween.
The first cap layer 106-1 made of an As layer and the second
Of the first cap layer 106-
Drain electrode 107 (AuGe /
Ni / Au).
A quantum well structure 108 having a subband of electrons provided over the T and the second cap layer 106-2;
Contact layer 109 laminated on quantum well structure 108
And a source electrode 110 (made of AuGe / Ni / Al) in ohmic contact with the contact layer 109. Near the interface between the channel layer (103) and the electron supply layer (104), an electron storage layer (not shown) in which the secondary electron gas E is stored is induced.

FIG. 5 shows the distribution of the InAs composition ratio x and the AlAs composition ratio y of each semiconductor layer in the direction perpendicular to the substrate surface of this embodiment. AlA in the electron supply layer (104)
The s composition ratio y is 0.22.

The InAs composition ratio x of the part (103a) of the channel layer 103 which is joined to the electron supply layer is 0.25 to 0 in the part (103b) of which the 0.25 cap layer is joined.
The two-dimensional electron gas is localized in the undoped In _0.25 Ga _0.75 As layer 103a having a high electron affinity.

Such an FET is manufactured as follows. On the (100) plane of the semi-insulating GaAs substrate 10, an undoped Al _0.25 Ga _0.75 As layer 102 having a thickness of 0.5 μm and Si as impurities are formed by MBE growth, for example.
-Type Al doped with a concentration of 2 × 10 ¹⁸ / cm ³
_0.22 Ga _0.78 As layer 104, undoped In _0.25 Ga _0.75 As layer 103a with a thickness of 10 nm, undoped GaAs layer 103b with a thickness of 30 nm, thickness of 50 nm, N doped with Si as an impurity to a concentration of 5 × 10 ¹⁸ / cm ^3.
Type GaAs layers are sequentially deposited. Next, an undoped GaAs layer 108a1 (first spacer layer) having a thickness of 10 nm and an undoped AlAs layer 108b1 having a thickness of 2 nm are formed.
(First barrier layer), undoped GaAs layer 108c (quantum well layer) having a thickness of 7 nm, undoped Al having a thickness of 2 nm
An As layer 108b2 (second barrier layer) and an undoped GaAs layer 108a2 (second spacer layer) having a thickness of 10 nm are sequentially deposited by MBE to form the quantum well structure 108. Next, a concentration of 5 × 10 ¹⁸ / c of Si is used as an impurity.
An n-type GaAs layer 109 with a thickness of 50 nm doped with m ³ is formed.

Here, although In _x Ga _1-x As and GaAs have different lattice constants, elastic strain is reduced by making the In _0.25 Ga _0.75 As layer a critical film thickness (about 12 nm) or less at which misfit dislocations occur. Becomes a strained lattice layer that relaxes the lattice irregularity, and a good interface is formed.

Next, the cap layer surface 106S is exposed by etching away the contact layer 109 and part of the quantum well structure 108. A source electrode 110 is formed on the contact layer 109 and the surface 1 of the cap layer (106-1).
After the drain electrode 107 is formed by vapor deposition on the 06S, ohmic contact between the source electrode 110 and the contact layer 106 and between the drain electrode 107 and the cap layer 106-1 are performed by ordinary alloy processing as in the first embodiment. Take. Further, the surface 103 of the electron supply layer exposed by etching away a part of the region between the quantum well structure 108 of the cap layer and the drain electrode 107 is removed.
In S, for example, a gate electrode 105 is formed by depositing a gate metal using a resist pattern (not shown) formed by the EB exposure method as a mask. Thus, the FET as shown in FIG. 4 is manufactured.

In this embodiment, the InAs composition ratio is 0 near the interface of the cap layer of the channel layer 103 and the interface between the cap layer and the channel layer is a homojunction. The contact resistivity with the channel layer 103a becomes extremely low. Also, the product of (impurity concentration × film thickness) in the cap layer is 2.5 × 10 ¹³ / cm ²
Therefore, the access resistance between the cap layer and the channel layer is sufficiently reduced, and an ohmic contact can be obtained without forming an alloy region.

Further, In _x Ga _{1 -x having} a high electron affinity
If the gate electrode is formed in contact with As, the height of the Schottky barrier decreases and the gate leakage current increases. However, in this embodiment, the gate electrode 105 is formed of a GaAs layer (103b) having a relatively small electron affinity. Since it is formed above, the height of the Schottky barrier is sufficiently high, and such a problem does not occur.

Such an FET is a conventional FE shown in FIG.
Like T, it has NDR in the I _d -V _gs characteristic. Further, while the conventional FET uses an N-type semiconductor as the channel layer, the electron mobility is low. On the other hand, according to the present invention, the electron storage layer having a high electron mobility is used as the channel. Can operate at high speed.

Next, a fourth embodiment will be described.

In the third embodiment, the channel layer 103 is divided into two layers. In this embodiment, the In composition ratio x of the undoped In _x Ga _{1 -x} As layer forming the channel layer 103 is shown in FIG.
As shown in FIG. 5, the value is changed from 0.2 to 0 from the electron supply layer 104 side to the cap layer side. The electron affinity also decreases from the electron supply layer side to the cap layer side. Therefore, the two-dimensional electron gas E is localized near the interface of the electron supply layer having a high electron affinity.

In this embodiment, as in the third embodiment, the cap layer (106-1, 106-2) and the channel layer 10
Since the interface of No. 3 is a homojunction, there is no conduction band barrier, and ohmic contact between the cap layer and the electron storage layer can be satisfactorily obtained without forming an alloy region.

Similarly, since the gate electrode 105 is in contact with the GaAs layer having a relatively small electron affinity, the height of the Schottky barrier is sufficiently high, and there is no problem that the gate leakage current increases.

[0038] In the above description, the undoped term does not intentionally doped with an impurity, means capable technical level purity, in each semiconductor layer in the present circumstances 1 × 10 ¹⁴
A purity of about / cm ³ can be easily achieved.

As described above, AlGaAs / I on the GaAs substrate
Although the description has been made using the nGaAs strain-based FET, the present invention is, of course, not limited to the AlGaAs / GaAs-based and InGaP / InGaAs-based on the GaAs substrate, or the InA-based substrate on the InP substrate.
lAs / InGaAs system and InGaP / InGaAs
The present invention is also applicable to FETs of other material systems such as a system.

[0040]

As described above, according to the present invention, a resonant tunneling diode can be integrated with a source of a selectively doped FET having high electron mobility while maintaining ohmic contact.
There is an effect that a negative differential resistance FET that can operate at higher speed can be realized.

[Brief description of drawings]

FIG. 1 is a cross-sectional view (FIG. 1 (a)) showing a main part of a first embodiment of the present invention and an enlarged view of a portion A in FIG. 1 (a) (FIG. 1).
(B)).

FIG. 2 is a graph showing distributions of InAs composition ratio x and AlAs composition ratio y in the first example.

FIG. 3 is a graph showing a distribution of an InAs composition ratio x and an AlAs composition ratio y in a second example.

FIG. 4 is a sectional view showing a main part of the third embodiment (FIG. 4);
FIG. 5A is an enlarged view of part A of FIG.

FIG. 5 is a graph showing a distribution of an InAs composition ratio x and an AlAs composition ratio y in the third example.

FIG. 6 is a graph showing a distribution of an InAs composition ratio x and an AlAs composition ratio y in the fourth embodiment.

FIG. 7 is a sectional view showing a main part of a conventional negative differential resistance FET.

[Explanation of symbols]

1, 101, 201 semi-insulating GaAs substrate 2 undoped GaAs layer 102 undoped Al _0.22 Ga _0.78 As layer 3 undoped In _x Ga _{1 -x} As layer 103 channel layer 103 a undoped In _0.25 Ga _0.75 As layer 103 b undoped GaAs layer 203 N-type GaAs layer 4 N-type Al _y Ga _1-y As layer 104 N-type Al _0.22 Ga _0.78 As layer 5, 105, 205 Gate electrode 6-1, 106-1 First cap layer 6-1, 106-2 Second 7, 107 drain electrode 8, 108, 208 quantum well structure 8a1, 108a1 undoped GaAs layer 8b1, 108b1 undoped AlAs layer 8c, 108 undoped GaAs layer 8b2, 108b2 undoped AlAs layer 9, 109, 209 contact layer 10, 110 , 210 Thaw Electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/80

Claims (6)

[Claims] 1. A buffer layer, a channel layer, and an electron supply layer, which are sequentially stacked on one main surface of a semiconductor substrate, a gate electrode that forms a Schottky junction with the electron supply layer, and the gate electrode on the surface of the electron supply layer. A first cap layer and a second cap layer each containing an N-type impurity concentration of at least 1 × 10 ¹⁸ / cm ³ and a drain electrode in ohmic contact with the first cap layer. A quantum well structure having an electron sub-band provided to cover the selectively doped FET and the second cap layer, and a contact layer laminated on the quantum well structure,
A negative differential resistance FET comprising a resonant tunneling diode having a source electrode in ohmic contact with the contact layer. 2. The product of the N-type impurity concentration and the film thickness of the first cap layer and the second cap layer is at least 5 × 10.
The negative differential resistance FET according to claim 1, which is ¹² / cm ² . 3. The differential negative resistance FET according to claim 1, wherein the electron affinity of the electron supply layer increases from the channel layer side to the first cap layer and the second cap layer side. 4. A buffer layer, an electron supply layer, and a channel layer, which are sequentially stacked on one main surface of a semiconductor substrate, a gate electrode that makes a Schottky junction with the channel layer, and the gate electrode is sandwiched on the surface of the channel layer. A selectively doped FET having a first cap layer and a second cap layer, respectively, and a drain electrode in ohmic contact with the first cap layer, and the second cap layer. Negative differential resistance comprising a resonant tunnel diode having a quantum well structure having a sub-band of electrons, a contact layer laminated on the quantum well structure, and a source electrode in ohmic contact with the contact layer. FET. 5. The negative differential resistance FE according to claim 4, wherein the electron affinity of the channel layer decreases from the electron supply layer side to the first cap layer and the second cap layer side.
T. 6. A channel layer formed of an In _x Ga _{1 -x} As layer (0
≦ x <1) and the electron supply is an N-type Al _y Ga _1-y As layer (0
≦ y <1), the first cap layer and the second cap layer are a first N-type GaAs layer, and the contact layer is a second N-type G layer.
an aAs layer, a first GaAs spacer layer having a quantum well structure,
First AlAs barrier layer, GaAs quantum well layer, second A
6. The negative differential resistance FET according to claim 1, wherein the negative differential resistance FET is a laminated film of an GaAs barrier layer and a second GaAs spacer layer.