JPH0821581B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JPH0821581B2
JPH0821581B2 JP1162510A JP16251089A JPH0821581B2 JP H0821581 B2 JPH0821581 B2 JP H0821581B2 JP 1162510 A JP1162510 A JP 1162510A JP 16251089 A JP16251089 A JP 16251089A JP H0821581 B2 JPH0821581 B2 JP H0821581B2
Authority
JP
Japan
Prior art keywords
layer
insulating material
semiconductor device
region
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1162510A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0251232A (ja
Inventor
ヨセフス・マルテイヌス．フランシスカス．ゲラルドゥス・ファン・ラールホーベン
ウィルヘルムス・フランシスカス・マリー・ゴーツェン
ミヒャエル・フリードリッヒ・ブルーノ・ベラーセン
トルング・トリ・ドアン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronics NV filed Critical Philips Electronics NV
Publication of JPH0251232A publication Critical patent/JPH0251232A/ja
Publication of JPH0821581B2 publication Critical patent/JPH0821581B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H10W20/0633—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material using subtractive patterning of the conductive members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/082—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being tapered via holes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/945—Special, e.g. metal

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
JP1162510A 1988-06-29 1989-06-23 半導体装置の製造方法 Expired - Fee Related JPH0821581B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8815442A GB2220298A (en) 1988-06-29 1988-06-29 A method of manufacturing a semiconductor device
GB8815442 1988-06-29

Publications (2)

Publication Number Publication Date
JPH0251232A JPH0251232A (ja) 1990-02-21
JPH0821581B2 true JPH0821581B2 (ja) 1996-03-04

Family

ID=10639557

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1162510A Expired - Fee Related JPH0821581B2 (ja) 1988-06-29 1989-06-23 半導体装置の製造方法

Country Status (7)

Country Link
US (1) US5001079A (fr)
EP (1) EP0349070B1 (fr)
JP (1) JPH0821581B2 (fr)
KR (1) KR900000992A (fr)
CN (1) CN1039151A (fr)
DE (1) DE68919549T2 (fr)
GB (1) GB2220298A (fr)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0405850A3 (fr) * 1989-06-30 1991-03-13 AT&T Corp. Procédé de formation de diélectriques et composants ainsi produits
FR2658362A1 (fr) * 1990-02-09 1991-08-16 Philips Electronique Lab Procede de realisation par autoalignement, d'un dispositif semiconducteur integre, comprenant au moins la formation d'un premier contact d'electrode encapsule et muni d'espaceurs et d'un second contact d'electrode autoaligne sur celui-ci.
KR950002948B1 (ko) * 1991-10-10 1995-03-28 삼성전자 주식회사 반도체 장치의 금속층간 절연막 형성방법
DE69217838T2 (de) * 1991-11-19 1997-08-21 Philips Electronics Nv Herstellungsverfahren für eine Halbleitervorrichtung mit durch eine Aluminiumverbindung seitlich voneinander isolierten Aluminiumspuren
EP0543449B1 (fr) * 1991-11-19 1997-03-05 Koninklijke Philips Electronics N.V. Procédé de fabrication d'un dispositif semi-conducteur comportant des pistes d'aluminium isolées l'une de l'autre latéralement par un composé d'aluminium
TW219407B (fr) * 1992-06-24 1994-01-21 American Telephone & Telegraph
JP2611615B2 (ja) * 1992-12-15 1997-05-21 日本電気株式会社 半導体装置の製造方法
US5532191A (en) * 1993-03-26 1996-07-02 Kawasaki Steel Corporation Method of chemical mechanical polishing planarization of an insulating film using an etching stop
US5641711A (en) * 1994-04-28 1997-06-24 Texas Instruments Incorporated Low dielectric constant insulation in VLSI applications
US5407860A (en) * 1994-05-27 1995-04-18 Texas Instruments Incorporated Method of forming air gap dielectric spaces between semiconductor leads
WO1996038859A1 (fr) * 1995-06-02 1996-12-05 Advanced Micro Devices, Inc. Couche isolante de conditionnement de surface pour reseau de conducteurs a lignes fines
US5599745A (en) 1995-06-07 1997-02-04 Micron Technology, Inc. Method to provide a void between adjacent conducting lines in a semiconductor device
US5641712A (en) * 1995-08-07 1997-06-24 Motorola, Inc. Method and structure for reducing capacitance between interconnect lines
US5789314A (en) * 1995-12-05 1998-08-04 Integrated Device Technology, Inc. Method of topside and inter-metal oxide coating
US5677241A (en) * 1995-12-27 1997-10-14 Micron Technology, Inc. Integrated circuitry having a pair of adjacent conductive lines and method of forming
US5953626A (en) * 1996-06-05 1999-09-14 Advanced Micro Devices, Inc. Dissolvable dielectric method
US5814555A (en) 1996-06-05 1998-09-29 Advanced Micro Devices, Inc. Interlevel dielectric with air gaps to lessen capacitive coupling
US6376330B1 (en) * 1996-06-05 2002-04-23 Advanced Micro Devices, Inc. Dielectric having an air gap formed between closely spaced interconnect lines
JPH10107140A (ja) * 1996-09-26 1998-04-24 Nec Corp 多層配線半導体装置とその製造方法
US6303464B1 (en) 1996-12-30 2001-10-16 Intel Corporation Method and structure for reducing interconnect system capacitance through enclosed voids in a dielectric layer
US6576976B2 (en) 1997-01-03 2003-06-10 Integrated Device Technology, Inc. Semiconductor integrated circuit with an insulation structure having reduced permittivity
US5869379A (en) * 1997-12-08 1999-02-09 Advanced Micro Devices, Inc. Method of forming air gap spacer for high performance MOSFETS'
US6133142A (en) * 1997-12-18 2000-10-17 Advanced Micro Devices, Inc. Lower metal feature profile with overhanging ARC layer to improve robustness of borderless vias
US6160316A (en) * 1998-03-04 2000-12-12 Advanced Micro Devices, Inc. Integrated circuit utilizing an air gap to reduce capacitance between adjacent metal linewidths
US6387797B1 (en) * 1999-01-20 2002-05-14 Philips Electronics No. America Corp. Method for reducing the capacitance between interconnects by forming voids in dielectric material
US6365489B1 (en) * 1999-06-15 2002-04-02 Micron Technology, Inc. Creation of subresolution features via flow characteristics
US6482688B2 (en) * 2001-03-30 2002-11-19 Texas Instruments Incorporated Utilizing amorphorization of polycrystalline structures to achieve T-shaped MOSFET gate
US6740549B1 (en) 2001-08-10 2004-05-25 Integrated Device Technology, Inc. Gate structures having sidewall spacers using selective deposition and method of forming the same
DE10201178A1 (de) * 2002-01-15 2003-06-26 Infineon Technologies Ag Verfahren zur Maskierung einer Ausnehmung einer Struktur mit einem großen Aspektverhältnis
US6846740B2 (en) * 2003-06-14 2005-01-25 Intel Corporation Wafer-level quasi-planarization and passivation for multi-height structures
US7294572B2 (en) * 2005-11-24 2007-11-13 United Microelectronics Corp. Method of forming contact
CN101202226B (zh) * 2006-12-11 2010-05-12 上海华虹Nec电子有限公司 一种改善金属前介质pmd填充特性的集成方法
KR20090000324A (ko) * 2007-06-28 2009-01-07 주식회사 하이닉스반도체 반도체 소자의 콘택 플러그 형성 방법
US8696922B2 (en) * 2009-06-22 2014-04-15 Micron Technology, Inc. Methods of plasma etching platinum-comprising materials, methods of processing semiconductor substrates in the fabrication of integrated circuitry, and methods of forming a plurality of memory cells
US8575000B2 (en) 2011-07-19 2013-11-05 SanDisk Technologies, Inc. Copper interconnects separated by air gaps and method of making thereof
US9449871B1 (en) 2015-11-18 2016-09-20 International Business Machines Corporation Hybrid airgap structure with oxide liner

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4507853A (en) 1982-08-23 1985-04-02 Texas Instruments Incorporated Metallization process for integrated circuits
US4666737A (en) 1986-02-11 1987-05-19 Harris Corporation Via metallization using metal fillets

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55138260A (en) * 1979-04-13 1980-10-28 Toshiba Corp Manufacture of semiconductor device
JPS5646263A (en) * 1979-09-25 1981-04-27 Fuji Xerox Co Ltd Original lighting device of electronic copying machine
JPS5690525A (en) * 1979-11-28 1981-07-22 Fujitsu Ltd Manufacture of semiconductor device
JPS59113630A (ja) * 1982-12-20 1984-06-30 Fujitsu Ltd 半導体装置の製造方法
JPS60110142A (ja) * 1983-11-18 1985-06-15 Matsushita Electronics Corp 半導体装置の製造方法
JPS60124951A (ja) * 1983-12-12 1985-07-04 Fujitsu Ltd 半導体装置の製造方法
US4481070A (en) * 1984-04-04 1984-11-06 Advanced Micro Devices, Inc. Double planarization process for multilayer metallization of integrated circuit structures
US4641420A (en) * 1984-08-30 1987-02-10 At&T Bell Laboratories Metalization process for headless contact using deposited smoothing material
JPS6233445A (ja) * 1985-08-07 1987-02-13 Nec Corp 多層配線とその製造方法
JPS63179548A (ja) * 1987-01-21 1988-07-23 Mitsubishi Electric Corp 半導体集積回路装置の配線構造
US4755477A (en) * 1987-03-24 1988-07-05 Industrial Technology Research Institute Overhang isolation technology

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4507853A (en) 1982-08-23 1985-04-02 Texas Instruments Incorporated Metallization process for integrated circuits
US4666737A (en) 1986-02-11 1987-05-19 Harris Corporation Via metallization using metal fillets

Also Published As

Publication number Publication date
EP0349070A2 (fr) 1990-01-03
EP0349070A3 (fr) 1991-02-20
US5001079A (en) 1991-03-19
GB8815442D0 (en) 1988-08-03
GB2220298A (en) 1990-01-04
EP0349070B1 (fr) 1994-11-30
DE68919549T2 (de) 1995-06-14
KR900000992A (ko) 1990-01-31
DE68919549D1 (de) 1995-01-12
JPH0251232A (ja) 1990-02-21
CN1039151A (zh) 1990-01-24

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Legal Events

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LAPS Cancellation because of no payment of annual fees