JPH08249268A - Direct memory access method - Google Patents

Abstract

PURPOSE: To support a DMA transferring system controlled by two pair of registers while keeping the interchangeability of software by allocating respectively the same IO addresses to the two pair of registers within a direct memory access controller (DMAC) so as to set a transfer address and the number of transfer bytes to the two pair of registers with single writing. CONSTITUTION: DMAC 4 is provided inside with a first register R1 consisting of a system-side address register (SAD) 8 and a system-side count register (SCT) 9 and a second register R2 consisting of an IO-side address register (LAD) 10 and an IO-side count register (ICT) 11. By setting a transfer destination address to SAD 8 and IAD 10 and the number of the transfer bytes to SCT 9 and LCT 11 at the time of starting DMA transfer, software can support DMA transfer without recognizing the two registers R1 and R2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct memory access method for performing direct memory access of data through a direct memory access controller (hereinafter referred to as DMAC) provided between a memory and a peripheral device, and more particularly, , System bus and I between memory and peripherals
The present invention relates to a direct memory access method performed via two buses, an O bus.

[0002]

2. Description of the Related Art The general computer system is expanding due to the improvement of CPU performance and the advent of high-speed buses. As described in JP-A-5-94404, C
A configuration in which a high-speed system bus to which a PU and a main memory are connected and an IO bus to which peripheral devices are connected are connected to a bus controller has become mainstream.

[0003]

Even in the DMA transfer system, the conventional DMA transfer system, in which the transfer address and the number of transfer bytes are controlled by a pair of registers provided in the DMAC, is transferred from the system bus to the IO bus. The transfer of
There is a need to support a DMA transfer scheme that is controlled by two pairs of registers. DM controlled by two pairs of registers
If the A transfer method is supported, the software is DMA
At the start of transfer, it is necessary to write IO to each of the two pairs of registers and set the transfer address and the number of transfer bytes.

Software that supports the DMA transfer method controlled by two pairs of registers uses the DMAC when setting the transfer address and the number of transfer bytes at the start of the DMA transfer.
Recognize that there are 2 pairs of registers in the IO write 2
You have to do it once. That is, the software supporting the conventional DMA transfer method controlled by a pair of registers cannot be used as it is, and the compatibility of the software cannot be maintained.

The present invention has been made in view of the above-mentioned problems of the prior art. While maintaining the compatibility of software,
An object is to provide a direct memory access method capable of supporting a DMA transfer method controlled by two pairs of registers.

[0006]

According to a direct memory access method of the present invention, a memory and a direct memory access controller are connected via a system bus, and I
A direct memory access method in which a peripheral device and a direct memory access controller are connected via an O bus, and direct data memory access of data is performed via a buffer in the system bus and the direct memory access controller and an IO bus. A first register for storing a data transfer destination address and the number of transfer data in the direct memory access transfer performed in the above, and a first register for storing the data transfer destination address and the number of transfer data in the direct memory access transfer performed on the IO bus. Direct memory for controlling the transfer destination address and the transfer data number of direct memory access transfer performed between the memory and the peripheral device by using the first register and the second register. Intended to be applied to the access method, it has the following characteristics.

That is, the same address is assigned to the IO address of the transfer destination address register in the first register and the IO address of the transfer destination address register in the second register, and the IO address of the transfer data number register in the first register. And the same address is assigned to the IO address of the transfer data number register in the second register, and the transfer destination address and the transfer data number are simultaneously set in the first register and the second register by one IO write, Further, by providing a 1-bit flag, it is possible to read only one of the first register and the second register.

[0008]

[Operation] 2 in the direct memory access controller
By assigning the same address as the IO address to each of the registers of the group (the group of the transfer destination address register and the group of the transfer data number register), the software sets the first register and the second register by one IO write. A transfer address and the number of transfer bytes can be set. Further, when reading the values of the first register and the second register, even if the assigned IO addresses are the same, a 1-bit flag is provided to distinguish the first register from the second register. Therefore, the software does not need to recognize that the first and second registers are included in the direct memory access controller. Therefore, when supporting the DMA transfer method controlled by the first and second registers (two pairs of registers),
Software that supports the DMA transfer method of controlling the transfer address and the number of transfer bytes by a pair of registers can be used as it is, and the compatibility of the software can be maintained.

[0009]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an example of a schematic configuration of a computer system to which the direct memory access method of the present invention is applied. The computer system shown in FIG. 1 includes an MPU 1 that performs information processing, a main memory (hereinafter referred to as MM) 3 that stores data, a main memory controller (hereinafter referred to as MCU) 2 that controls the MM 3, and a system bus. Direct memory access controller (hereinafter referred to as D
4) and a DMAC 4 via the IO bus 7.
And a peripheral device 5 connected to. DMA
In C4, a system side address register (hereinafter, referred to as SAD) 8 in which a transfer destination address of data to be DMA-transferred on the system bus is set, and a system bus side count register in which the number of transfer bytes is set (hereinafter, referred to as SAD) S
(Referred to as CT) 9 consisting of a first register R1 and IO
It is composed of an IO side address register (hereinafter referred to as IAD) 10 in which a transfer destination address of data transferred by DMA on the bus is set, and an IO side count register (hereinafter referred to as ICT) 11 in which the number of transfer bytes is set. Second
Register R2, a DMA transfer write buffer (hereinafter referred to as a DMAW buffer) 12 for temporarily storing the data transferred from the peripheral device 5 to the MM3, and the data transferred from the MM3 to the peripheral device 5 temporarily. D to save
MA read buffer (hereinafter referred to as DMAR buffer) 13 and register switching flag 1 at IO read
4 are provided. Here, the same IO address is assigned to SAD8 and IAD10, and SCT9 and ICT
The same IO address is assigned to 11.

In more detail, referring to FIG.
When performing a DMA transfer from the system bus 6 side to the IO bus 7 side, the transfer destination address of the memory (not shown) in the peripheral device 5 is set in the SAD 8 and IAD 10, and conversely IO
When performing DMA transfer from the bus 7 side to the system bus 6 side, the transfer destination address of the MM 3 is set in SAD 8 and IAD 10. Further, in FIG. 1, SCT9 and IC
The number of transfer bytes is set in T11 at the start of transfer, but after the start of transfer, a value obtained by subtracting the number of bytes actually transferred from the number of transfer bytes is set. For example, if DMA transfer is performed from the system bus 6 side to the IO bus 7 side and the number of transfer bytes is 256 bytes, S
Initially, "256" is set in CT9 and ICT11. Then, when data is transferred to the DMAC 4 via the system bus 6 in units of 4 bytes, for example, the SCT
The values of “252”, “248”, ... Further, when data is transferred from the DMAC 4 to the peripheral device 5 via the IO bus 7 in units of 1 byte, for example,
The ICT 11 has “255”, “254”, and “25” in order.
3 ”is set. In this case, DM of DMAC4
The AW buffer 12 receives data from the system bus 6 in 4-byte units and outputs the data to the IO bus 7 in 1-byte units.

FIG. 2 shows the IO bus 7 from the system bus 6 side.
When data is DMA-transferred to the side, the first register R1 and the second register R2 in the DMAC at the start of the DMA transfer.
FIG. 6 is a block diagram showing the setting of a path when setting a transfer destination address and a transfer byte number in the.

At the start of the DMA transfer, the software uses the S of the first register in the DMAC 4 via the system bus 6.
The transfer destination address (for example, address 1000) is IO-written to both the registers of AD8 and IAD10 of the second register. Here, since the IO address of the SAD8 and the IO address of the IAD10 are the same address (for example, the address AAAA), the software sends "1" once to the address AAAA.
By writing the value "address 000" to IO, pass 2
"1000" is set in the two registers of SAD8 and IAD10 via 1, 22, and 23.

Next, the software IO-writes the number of transfer bytes (for example, 256) to both the registers SCT9 of the first register and ICT11 of the second register via the system bus 6 in the DMAC4. Where SCT9
Since the IO address of the ICT11 and the IO address of the ICT11 are the same address (for example, BBBB address), the software writes the value "256" to the BBBB address once, and the IO is written through the paths 21, 22 and 24. SCT
"256" is set in the two registers of 9 and ICT11.

According to the above embodiment, when the DMA transfer is started,
It is possible to set the transfer destination address in SAD8 and IAD10 and the transfer byte number in SCT9 and ICT11 by one IO write, and the software can support the DMA transfer without recognizing the two registers.
Software compatibility can be maintained.

FIG. 3 shows the first register R in the DMAC4.
It is a figure which shows the setting of the path at the time of reading the content of the 1st and 2nd register R2. In FIG. 3, SAD8 and IA
When D10 and SCT9 and ICT11 are IO-read, the same IO address is assigned to these two sets of registers. Therefore, in this embodiment, the value of the register switching flag 14 in the DMAC 4 is used to specify the IO read register on the hardware. Unless the normal register switching flag 14 is set, the register switching flag 14 is "0", and the second register R2 is designated. In this case, the software sets the address AAAA to I in order to know the transfer destination address set in the register in the DMAC4.
When O is read, the register value of the IAD 10 is read via the paths 28, 30, 32, 33 and 34. Also, D
If the BBBB address is IO read to know the number of transfer bytes set in the register in MAC4, the path 2
The register value of the ICT 11 is read via 9, 30, 32, 33, and 34. Here, if it is necessary to read the register value of SAD8 or SCT9 for operation analysis due to a malfunction, etc., if the register switching flag 14 is set to "1" in the operation analysis tool, the first When 1 register R1 is specified and IO is read from the address AAAA, paths 25, 27, 31, 33, 3
When the register value of the SAD8 is read through IO and the address BBBB is IO-read, the paths 26, 27, 31, 33, 34 are passed.
The register value of SCT9 is read via.

According to the above embodiment, when reading the values of the first register and the second register, the assigned IO
Even if the addresses are the same, the first register and the second register can be discriminated by providing a 1-bit flag.
You don't have to be aware that
It becomes possible to support software compatibility.

[0018]

As described above, according to the present invention, it is carried out on the IO bus and the first register for controlling the data transfer destination address and the number of transferred data in the DMA transfer carried out on the system bus. Even in the system of two pairs of registers of the second register that controls the transfer destination address and the number of pieces of data to be transferred in the DMA transfer, one IO is performed in the same manner as the conventional DMA transfer method in which the DMA transfer is controlled by the pair of registers. The destination address and the number of transfer bytes can be set by writing. In addition, when reading the values of the first register and the second register, even if the assigned IO addresses are the same, by providing a 1-bit flag
Since it is possible to discriminate between the first register and the second register, the software does not need to recognize that the first and second registers are present in the direct memory access controller. Therefore, software compatibility can be maintained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a schematic configuration of a computer system to which a direct memory access method of the present invention is applied.

FIG. 2 is a diagram showing a case of setting a transfer destination address and a transfer byte number in a first register and a second register in a DMAC at the start of DMA transfer when data is DMA-transferred from a system bus side to an IO bus side. Block diagram showing the setting of the path.

FIG. 3 is a diagram showing a path setting when reading the contents of a first register R1 and a second register R2 in the DMAC4.

[Explanation of symbols]

1 ... MPU, 2 ... Main memory controller (MC
U), 3 ... Main memory (MM), 4 ... Direct memory access controller (DMAC), 5 ... Peripheral device,
6 ... System bus, 7 ... IO bus, 8 ... System bus side address register (SAD), 9 ... System bus side count register (SCT), 10 ... IO bus side address register (IAD), 11 ... IO bus side count register (ICT), 12 ... DMA write buffer, 13 ... D
MA read buffer, 14 ... Register switching flag.

Claims (1)

[Claims] 1. A memory and a direct memory access controller are connected via a system bus, a peripheral device and a direct memory access controller are connected via an IO bus, and a buffer in the system bus and the direct memory access controller and an IO bus. A direct memory access method for performing direct memory access of data via, a first register for storing a transfer destination address and a transfer data number of data in a direct memory access transfer performed on a system bus, and an IO A second register for storing the data transfer destination address and the number of transferred data in the direct memory access transfer performed on the bus is provided in the direct memory access controller, and the memory is provided around the memory using the first and second registers. Dress In a direct memory access method for controlling a transfer destination address and a transfer data number of a direct memory access transfer performed in a space, an IO of a transfer destination address register in a first register is provided.
The same address is assigned to the address and the IO address of the transfer destination address register in the second register, and the IO address of the transfer data number register in the first register and the IO address of the transfer data number register in the second register are the same. By assigning an address and setting the transfer destination address and the number of transfer data in the first register and the second register at the same time by one IO write, and further by providing a 1-bit flag, A direct memory access method, characterized in that only one of the second registers is read.